setupEM 0.1.13__tar.gz
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- setupem-0.1.13/PKG-INFO +59 -0
- setupem-0.1.13/README.md +47 -0
- setupem-0.1.13/pyproject.toml +26 -0
- setupem-0.1.13/setup.cfg +4 -0
- setupem-0.1.13/src/setupEM/__init__.py +9 -0
- setupem-0.1.13/src/setupEM/__main__.py +5 -0
- setupem-0.1.13/src/setupEM/data/SG13G2_100um.xml +61 -0
- setupem-0.1.13/src/setupEM/data/SG13G2_200um.xml +61 -0
- setupem-0.1.13/src/setupEM/data/SG13G2_nosub.xml +57 -0
- setupem-0.1.13/src/setupEM/examples/pcb_lowpass/palace_pcb_lowpass.py +120 -0
- setupem-0.1.13/src/setupEM/examples/sg13_balun_140-170/palace_balun_mesh2.py +120 -0
- setupem-0.1.13/src/setupEM/examples/sg13_microstrip_fast/palace_demo_line.py +117 -0
- setupem-0.1.13/src/setupEM/examples/sg13_rfcmim/palace_rfcmim.py +114 -0
- setupem-0.1.13/src/setupEM/setupEM.py +2702 -0
- setupem-0.1.13/src/setupEM.egg-info/PKG-INFO +59 -0
- setupem-0.1.13/src/setupEM.egg-info/SOURCES.txt +18 -0
- setupem-0.1.13/src/setupEM.egg-info/dependency_links.txt +1 -0
- setupem-0.1.13/src/setupEM.egg-info/entry_points.txt +2 -0
- setupem-0.1.13/src/setupEM.egg-info/requires.txt +4 -0
- setupem-0.1.13/src/setupEM.egg-info/top_level.txt +1 -0
setupem-0.1.13/PKG-INFO
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Metadata-Version: 2.4
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Name: setupEM
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Version: 0.1.13
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Summary: Python tool for configuration of gds2palace workflow with GUI.
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Author-email: Volker Muehlhaus <volker@muehlhaus.com>
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Requires-Python: >=3.9
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Description-Content-Type: text/markdown
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Requires-Dist: gds2palace>=0.1.8
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Requires-Dist: PySide6
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Requires-Dist: scipy
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Requires-Dist: requests
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# Create EM Simulation model from GDSII layout files
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setupEM provides a graphical user interface (Qt based) to configured gds2palace workflow.
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gds2palace enables an RFIC FEM simulation workflow based on the Palace FEM solver by AWS.
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# Installation
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To install the setupEM, activate the venv where you want to install.
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Documentation for the gds2palace workflow assumes that you have created a Python venv
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named "palace" in ~/venv/palace and installed the modules there.
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If you follow this, you would first activate the venv:
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```
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source ~\venv\palace\bin\activate
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```
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and then install setupEM and dependencies via PyPI:
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```
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pip install setupEM
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```
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To upgrade to the latest version, do
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```
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pip install setupEM --upgrade
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```
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## Missing libraries on installation
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If you see this error message when trying to run setupEM:
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```
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qt.qpa.plugin: From 6.5.0, xcb-cursor0 or libxcb-cursor0 is needed to load the Qt xcb platform plugin. qt.qpa.plugin: Could not load the Qt platform plugin "xcb" in "" even though it was found.
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```
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you need to install additional Qt libraries:
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```
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sudo apt update
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sudo apt install libxcb-cursor0 libxcb-xinerama0 libxcb-xkb1 libxcb-icccm4 libxcb-image0 libxcb-keysyms1 libxcb-randr0 libxcb-render-util0 libxcb-render0 libxcb-shape0 libxcb-shm0 libxcb-sync1 libxcb-xfixes0 libxcb-xinput0 libxcb-xv0 libxcb-util1 libxkbcommon-x11-0
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```
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# Dependencies
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This module also installs these dependencies:
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gds2palace
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PySide6
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setupem-0.1.13/README.md
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# Create EM Simulation model from GDSII layout files
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setupEM provides a graphical user interface (Qt based) to configured gds2palace workflow.
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gds2palace enables an RFIC FEM simulation workflow based on the Palace FEM solver by AWS.
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# Installation
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To install the setupEM, activate the venv where you want to install.
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Documentation for the gds2palace workflow assumes that you have created a Python venv
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named "palace" in ~/venv/palace and installed the modules there.
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If you follow this, you would first activate the venv:
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```
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source ~\venv\palace\bin\activate
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```
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and then install setupEM and dependencies via PyPI:
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```
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pip install setupEM
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```
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To upgrade to the latest version, do
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```
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pip install setupEM --upgrade
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```
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## Missing libraries on installation
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If you see this error message when trying to run setupEM:
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```
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qt.qpa.plugin: From 6.5.0, xcb-cursor0 or libxcb-cursor0 is needed to load the Qt xcb platform plugin. qt.qpa.plugin: Could not load the Qt platform plugin "xcb" in "" even though it was found.
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```
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you need to install additional Qt libraries:
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```
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sudo apt update
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sudo apt install libxcb-cursor0 libxcb-xinerama0 libxcb-xkb1 libxcb-icccm4 libxcb-image0 libxcb-keysyms1 libxcb-randr0 libxcb-render-util0 libxcb-render0 libxcb-shape0 libxcb-shm0 libxcb-sync1 libxcb-xfixes0 libxcb-xinput0 libxcb-xv0 libxcb-util1 libxkbcommon-x11-0
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```
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# Dependencies
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This module also installs these dependencies:
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gds2palace
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PySide6
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[build-system]
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requires = ["setuptools>=61.0"]
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build-backend = "setuptools.build_meta"
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[project]
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name = "setupEM"
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version = "0.1.13"
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description = "Python tool for configuration of gds2palace workflow with GUI."
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readme = "README.md"
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authors = [
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{ name = "Volker Muehlhaus", email = "volker@muehlhaus.com" }
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]
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dependencies = [
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"gds2palace>=0.1.8",
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"PySide6",
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"scipy",
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"requests"
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]
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requires-python = ">=3.9"
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[project.scripts]
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setupEM = "setupEM.setupEM:main"
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[tool.setuptools.package-data]
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"setupEM" = ["examples/*.py","examples/*.gds","examples/*.xml","data/*.xml"]
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setupem-0.1.13/setup.cfg
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<Stackup schemaVersion="2.0">
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<Materials>
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<Material Name="Activ" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="357141.0" Color="00ff00"/>
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<Material Name="Metal1" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="21640000.0" Color="39bfff"/>
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<Material Name="Metal2" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="23190000.0" Color="ccccd9"/>
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<Material Name="Metal3" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="23190000.0" Color="d80000"/>
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<Material Name="Metal4" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="23190000.0" Color="93e837"/>
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<Material Name="Metal5" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="23190000.0" Color="dcd146"/>
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<Material Name="TopMetal1" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="27800000.0" Color="ffe6bf"/>
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<Material Name="TopMetal2" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="30300000.0" Color="ff8000"/>
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<Material Name="TopVia2" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="3143000.0" Color="ff8000"/>
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<Material Name="TopVia1" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="2191000.0" Color="ffe6bf"/>
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<Material Name="Via4" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="1660000.0" Color="deac5e"/>
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<Material Name="Via3" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="1660000.0" Color="9ba940"/>
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<Material Name="Via2" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="1660000.0" Color="ff3736"/>
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<Material Name="Via1" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="1660000.0" Color="ccccff"/>
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<Material Name="Cont" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="2390000.0" Color="00ffff"/>
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<Material Name="Passive" Type="Dielectric" Permittivity="6.6" DielectricLossTangent="0.0" Conductivity="0" Color="a0a0f0"/>
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<Material Name="SiO2" Type="Dielectric" Permittivity="4.1" DielectricLossTangent="0.0" Conductivity="0" Color="fffcad"/>
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<Material Name="Substrate" Type="Semiconductor" Permittivity="11.9" DielectricLossTangent="0" Conductivity="2.0" Color="01e0ff"/>
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<Material Name="EPI" Type="Semiconductor" Permittivity="11.9" DielectricLossTangent="0" Conductivity="5.0" Color="294fff"/>
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<Material Name="AIR" Type="Dielectric" Permittivity="1.0" DielectricLossTangent="0.0" Conductivity="0" Color="d0d0d0"/>
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<Material Name="Vmim" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="2191000.0" Color="ffe6bf"/>
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<Material Name="MIM" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="500000.0" Color="e6ffbf"/>
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<Material Name="LOWLOSS" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="1E10" Color="ff0000"/>
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</Materials>
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<ELayers LengthUnit="um">
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<Dielectrics>
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<Dielectric Name="AIR" Material="AIR" Thickness="200.0000" />
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<Dielectric Name="Passive" Material="Passive" Thickness="0.4000" />
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<Dielectric Name="SiO2" Material="SiO2" Thickness="15.7303" />
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<Dielectric Name="EPI" Material="EPI" Thickness="3.7500" />
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<Dielectric Name="Substrate" Material="Substrate" Thickness="80.0000" />
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</Dielectrics>
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<Layers>
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<Substrate Offset="83.75"/>
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<Layer Name="Activ" Type="conductor" Zmin="0.0000" Zmax="0.4000" Material="Activ" Layer="1" />
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<Layer Name="Metal1" Type="conductor" Zmin="1.0400" Zmax="1.4600" Material="Metal1" Layer="8" />
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<Layer Name="Metal2" Type="conductor" Zmin="2.0000" Zmax="2.4900" Material="Metal2" Layer="10" />
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<Layer Name="Metal3" Type="conductor" Zmin="3.0300" Zmax="3.5200" Material="Metal3" Layer="30" />
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<Layer Name="Metal4" Type="conductor" Zmin="4.0600" Zmax="4.5500" Material="Metal4" Layer="50" />
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<Layer Name="Metal5" Type="conductor" Zmin="5.0900" Zmax="5.5800" Material="Metal5" Layer="67" />
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<Layer Name="TopMetal1" Type="conductor" Zmin="6.4303" Zmax="8.4303" Material="TopMetal1" Layer="126" />
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<Layer Name="TopMetal2" Type="conductor" Zmin="11.2303" Zmax="14.2303" Material="TopMetal2" Layer="134" />
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<Layer Name="TopVia2" Type="via" Zmin="8.4303" Zmax="11.2303" Material="TopVia2" Layer="133" />
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<Layer Name="TopVia1" Type="via" Zmin="5.5800" Zmax="6.4303" Material="TopVia1" Layer="125" />
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<Layer Name="Via4" Type="via" Zmin="4.5500" Zmax="5.0900" Material="Via4" Layer="66" />
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<Layer Name="Via3" Type="via" Zmin="3.5200" Zmax="4.0600" Material="Via3" Layer="49" />
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<Layer Name="Via2" Type="via" Zmin="2.4900" Zmax="3.0300" Material="Via2" Layer="29" />
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<Layer Name="Via1" Type="via" Zmin="1.4600" Zmax="2.0000" Material="Via1" Layer="19" />
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<Layer Name="Cont" Type="via" Zmin="0.4000" Zmax="1.0400" Material="Cont" Layer="6" />
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<Layer Name="SUBGND" Type="conductor" Zmin="-3.75" Zmax="0" Material="LOWLOSS" Layer="250" />
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<Layer Name="BACKSIDEGND" Type="conductor" Zmin="-90" Zmax="-83.75" Material="LOWLOSS" Layer="251" />
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<Layer Name="MIM" Type="conductor" Zmin="5.6043" Zmax="5.7540" Material="MIM" Layer="36" />
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<Layer Name="Vmim" Type="via" Zmin="5.7540" Zmax="6.4303" Material="Vmim" Layer="129" />
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<Layer Name="LBE" Type="dielectric" Zmin="-83.75" Zmax="0" Material="Air" Layer="157" />
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</Layers>
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</ELayers>
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</Stackup>
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<Stackup schemaVersion="2.0">
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<Materials>
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<Material Name="Activ" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="357141.0" Color="00ff00"/>
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<Material Name="Metal1" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="21640000.0" Color="39bfff"/>
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<Material Name="Metal2" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="23190000.0" Color="ccccd9"/>
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<Material Name="Metal3" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="23190000.0" Color="d80000"/>
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<Material Name="Metal4" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="23190000.0" Color="93e837"/>
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<Material Name="Metal5" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="23190000.0" Color="dcd146"/>
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<Material Name="TopMetal1" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="27800000.0" Color="ffe6bf"/>
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<Material Name="TopMetal2" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="30300000.0" Color="ff8000"/>
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<Material Name="TopVia2" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="3143000.0" Color="ff8000"/>
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<Material Name="TopVia1" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="2191000.0" Color="ffe6bf"/>
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<Material Name="Via4" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="1660000.0" Color="deac5e"/>
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<Material Name="Via3" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="1660000.0" Color="9ba940"/>
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<Material Name="Via2" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="1660000.0" Color="ff3736"/>
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<Material Name="Via1" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="1660000.0" Color="ccccff"/>
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<Material Name="Cont" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="2390000.0" Color="00ffff"/>
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<Material Name="Passive" Type="Dielectric" Permittivity="6.6" DielectricLossTangent="0.0" Conductivity="0" Color="a0a0f0"/>
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<Material Name="SiO2" Type="Dielectric" Permittivity="4.1" DielectricLossTangent="0.0" Conductivity="0" Color="fffcad"/>
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+
<Material Name="Substrate" Type="Semiconductor" Permittivity="11.9" DielectricLossTangent="0" Conductivity="2.0" Color="01e0ff"/>
|
|
22
|
+
<Material Name="EPI" Type="Semiconductor" Permittivity="11.9" DielectricLossTangent="0" Conductivity="5.0" Color="294fff"/>
|
|
23
|
+
<Material Name="AIR" Type="Dielectric" Permittivity="1.0" DielectricLossTangent="0.0" Conductivity="0" Color="d0d0d0"/>
|
|
24
|
+
<Material Name="Vmim" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="2191000.0" Color="ffe6bf"/>
|
|
25
|
+
<Material Name="MIM" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="500000.0" Color="e6ffbf"/>
|
|
26
|
+
<Material Name="LOWLOSS" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="1E10" Color="ff0000"/>
|
|
27
|
+
</Materials>
|
|
28
|
+
<ELayers LengthUnit="um">
|
|
29
|
+
<Dielectrics>
|
|
30
|
+
<Dielectric Name="AIR" Material="AIR" Thickness="200.0000" />
|
|
31
|
+
<Dielectric Name="Passive" Material="Passive" Thickness="0.4000" />
|
|
32
|
+
<Dielectric Name="SiO2" Material="SiO2" Thickness="15.7303" />
|
|
33
|
+
<Dielectric Name="EPI" Material="EPI" Thickness="3.7500" />
|
|
34
|
+
<Dielectric Name="Substrate" Material="Substrate" Thickness="180.0000" />
|
|
35
|
+
</Dielectrics>
|
|
36
|
+
<Layers>
|
|
37
|
+
<Substrate Offset="183.75"/>
|
|
38
|
+
<Layer Name="Activ" Type="conductor" Zmin="0.0000" Zmax="0.4000" Material="Activ" Layer="1" />
|
|
39
|
+
<Layer Name="Metal1" Type="conductor" Zmin="1.0400" Zmax="1.4600" Material="Metal1" Layer="8" />
|
|
40
|
+
<Layer Name="Metal2" Type="conductor" Zmin="2.0000" Zmax="2.4900" Material="Metal2" Layer="10" />
|
|
41
|
+
<Layer Name="Metal3" Type="conductor" Zmin="3.0300" Zmax="3.5200" Material="Metal3" Layer="30" />
|
|
42
|
+
<Layer Name="Metal4" Type="conductor" Zmin="4.0600" Zmax="4.5500" Material="Metal4" Layer="50" />
|
|
43
|
+
<Layer Name="Metal5" Type="conductor" Zmin="5.0900" Zmax="5.5800" Material="Metal5" Layer="67" />
|
|
44
|
+
<Layer Name="TopMetal1" Type="conductor" Zmin="6.4303" Zmax="8.4303" Material="TopMetal1" Layer="126" />
|
|
45
|
+
<Layer Name="TopMetal2" Type="conductor" Zmin="11.2303" Zmax="14.2303" Material="TopMetal2" Layer="134" />
|
|
46
|
+
<Layer Name="TopVia2" Type="via" Zmin="8.4303" Zmax="11.2303" Material="TopVia2" Layer="133" />
|
|
47
|
+
<Layer Name="TopVia1" Type="via" Zmin="5.5800" Zmax="6.4303" Material="TopVia1" Layer="125" />
|
|
48
|
+
<Layer Name="Via4" Type="via" Zmin="4.5500" Zmax="5.0900" Material="Via4" Layer="66" />
|
|
49
|
+
<Layer Name="Via3" Type="via" Zmin="3.5200" Zmax="4.0600" Material="Via3" Layer="49" />
|
|
50
|
+
<Layer Name="Via2" Type="via" Zmin="2.4900" Zmax="3.0300" Material="Via2" Layer="29" />
|
|
51
|
+
<Layer Name="Via1" Type="via" Zmin="1.4600" Zmax="2.0000" Material="Via1" Layer="19" />
|
|
52
|
+
<Layer Name="Cont" Type="via" Zmin="0.4000" Zmax="1.0400" Material="Cont" Layer="6" />
|
|
53
|
+
<Layer Name="SUBGND" Type="conductor" Zmin="-3.75" Zmax="0" Material="LOWLOSS" Layer="250" />
|
|
54
|
+
<Layer Name="BACKSIDEGND" Type="conductor" Zmin="-190" Zmax="-183.75" Material="LOWLOSS" Layer="251" />
|
|
55
|
+
<Layer Name="MIM" Type="conductor" Zmin="5.6043" Zmax="5.7540" Material="MIM" Layer="36" />
|
|
56
|
+
<Layer Name="Vmim" Type="via" Zmin="5.7540" Zmax="6.4303" Material="Vmim" Layer="129" />
|
|
57
|
+
<Layer Name="LBE" Type="dielectric" Zmin="-183.75" Zmax="0" Material="Air" Layer="157" />
|
|
58
|
+
</Layers>
|
|
59
|
+
</ELayers>
|
|
60
|
+
</Stackup>
|
|
61
|
+
|
|
@@ -0,0 +1,57 @@
|
|
|
1
|
+
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
|
2
|
+
<Stackup schemaVersion="2.0">
|
|
3
|
+
<Materials>
|
|
4
|
+
<Material Name="Activ" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="357141.0" Color="00ff00"/>
|
|
5
|
+
<Material Name="Metal1" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="21640000.0" Color="39bfff"/>
|
|
6
|
+
<Material Name="Metal2" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="23190000.0" Color="ccccd9"/>
|
|
7
|
+
<Material Name="Metal3" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="23190000.0" Color="d80000"/>
|
|
8
|
+
<Material Name="Metal4" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="23190000.0" Color="93e837"/>
|
|
9
|
+
<Material Name="Metal5" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="23190000.0" Color="dcd146"/>
|
|
10
|
+
<Material Name="TopMetal1" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="27800000.0" Color="ffe6bf"/>
|
|
11
|
+
<Material Name="TopMetal2" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="30300000.0" Color="ff8000"/>
|
|
12
|
+
<Material Name="TopVia2" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="3143000.0" Color="ff8000"/>
|
|
13
|
+
<Material Name="TopVia1" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="2191000.0" Color="ffe6bf"/>
|
|
14
|
+
<Material Name="Via4" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="1660000.0" Color="deac5e"/>
|
|
15
|
+
<Material Name="Via3" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="1660000.0" Color="9ba940"/>
|
|
16
|
+
<Material Name="Via2" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="1660000.0" Color="ff3736"/>
|
|
17
|
+
<Material Name="Via1" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="1660000.0" Color="ccccff"/>
|
|
18
|
+
<Material Name="Cont" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="2390000.0" Color="00ffff"/>
|
|
19
|
+
<Material Name="Passive" Type="Dielectric" Permittivity="6.6" DielectricLossTangent="0.0" Conductivity="0" Color="a0a0f0"/>
|
|
20
|
+
<Material Name="SiO2" Type="Dielectric" Permittivity="4.1" DielectricLossTangent="0.0" Conductivity="0" Color="fffcad"/>
|
|
21
|
+
<Material Name="Substrate" Type="Semiconductor" Permittivity="11.9" DielectricLossTangent="0" Conductivity="2.0" Color="01e0ff"/>
|
|
22
|
+
<Material Name="EPI" Type="Semiconductor" Permittivity="11.9" DielectricLossTangent="0" Conductivity="5.0" Color="294fff"/>
|
|
23
|
+
<Material Name="AIR" Type="Dielectric" Permittivity="1.0" DielectricLossTangent="0.0" Conductivity="0" Color="d0d0d0"/>
|
|
24
|
+
<Material Name="LOWLOSS" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="1E10" Color="ff0000"/>
|
|
25
|
+
<Material Name="Vmim" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="2191000.0" Color="ffe6bf"/>
|
|
26
|
+
<Material Name="MIM" Type="Conductor" Permittivity="1" DielectricLossTangent="0" Conductivity="500000.0" Color="e6ffbf"/>
|
|
27
|
+
</Materials>
|
|
28
|
+
<ELayers LengthUnit="um">
|
|
29
|
+
<Dielectrics>
|
|
30
|
+
<Dielectric Name="AIR" Material="AIR" Thickness="300.0000" />
|
|
31
|
+
<Dielectric Name="Passive" Material="Passive" Thickness="0.4000" />
|
|
32
|
+
<Dielectric Name="SiO2" Material="SiO2" Thickness="15.7303" />
|
|
33
|
+
<Dielectric Name="Spacing" Material="SiO2" Thickness="2.0" />
|
|
34
|
+
</Dielectrics>
|
|
35
|
+
<Layers>
|
|
36
|
+
<Substrate Offset="2.0"/>
|
|
37
|
+
<Layer Name="Activ" Type="conductor" Zmin="0.0000" Zmax="0.4000" Material="Activ" Layer="1" />
|
|
38
|
+
<Layer Name="Metal1" Type="conductor" Zmin="1.0400" Zmax="1.4600" Material="Metal1" Layer="8" />
|
|
39
|
+
<Layer Name="Metal2" Type="conductor" Zmin="2.0000" Zmax="2.4900" Material="Metal2" Layer="10" />
|
|
40
|
+
<Layer Name="Metal3" Type="conductor" Zmin="3.0300" Zmax="3.5200" Material="Metal3" Layer="30" />
|
|
41
|
+
<Layer Name="Metal4" Type="conductor" Zmin="4.0600" Zmax="4.5500" Material="Metal4" Layer="50" />
|
|
42
|
+
<Layer Name="Metal5" Type="conductor" Zmin="5.0900" Zmax="5.5800" Material="Metal5" Layer="67" />
|
|
43
|
+
<Layer Name="TopMetal1" Type="conductor" Zmin="6.4303" Zmax="8.4303" Material="TopMetal1" Layer="126" />
|
|
44
|
+
<Layer Name="TopMetal2" Type="conductor" Zmin="11.2303" Zmax="14.2303" Material="TopMetal2" Layer="134" />
|
|
45
|
+
<Layer Name="TopVia2" Type="via" Zmin="8.4303" Zmax="11.2303" Material="TopVia2" Layer="133" />
|
|
46
|
+
<Layer Name="TopVia1" Type="via" Zmin="5.5800" Zmax="6.4303" Material="TopVia1" Layer="125" />
|
|
47
|
+
<Layer Name="Via4" Type="via" Zmin="4.5500" Zmax="5.0900" Material="Via4" Layer="66" />
|
|
48
|
+
<Layer Name="Via3" Type="via" Zmin="3.5200" Zmax="4.0600" Material="Via3" Layer="49" />
|
|
49
|
+
<Layer Name="Via2" Type="via" Zmin="2.4900" Zmax="3.0300" Material="Via2" Layer="29" />
|
|
50
|
+
<Layer Name="Via1" Type="via" Zmin="1.4600" Zmax="2.0000" Material="Via1" Layer="19" />
|
|
51
|
+
<Layer Name="Cont" Type="via" Zmin="0.4000" Zmax="1.0400" Material="Cont" Layer="6" />
|
|
52
|
+
<Layer Name="MIM" Type="conductor" Zmin="5.6043" Zmax="5.7540" Material="MIM" Layer="36" />
|
|
53
|
+
<Layer Name="Vmim" Type="via" Zmin="5.7540" Zmax="6.4303" Material="Vmim" Layer="129" />
|
|
54
|
+
</Layers>
|
|
55
|
+
</ELayers>
|
|
56
|
+
</Stackup>
|
|
57
|
+
|
|
@@ -0,0 +1,120 @@
|
|
|
1
|
+
# MODEL FOR GMSH WITH PALACE
|
|
2
|
+
|
|
3
|
+
import os
|
|
4
|
+
import sys
|
|
5
|
+
import subprocess
|
|
6
|
+
|
|
7
|
+
# we expect gds2palace in the same directory as this model file
|
|
8
|
+
sys.path.insert(0, os.path.abspath(os.path.join(os.path.dirname(__file__), 'gds2palace')))
|
|
9
|
+
from gds2palace import *
|
|
10
|
+
|
|
11
|
+
# Model comments
|
|
12
|
+
#
|
|
13
|
+
# PCB low pass example, everything is in unit micron (GDS and XML stackup)
|
|
14
|
+
# Port excitation only, so that we get S11 and S21. Reverse path data is padded with zeros.
|
|
15
|
+
|
|
16
|
+
|
|
17
|
+
# ======================== workflow settings ================================
|
|
18
|
+
|
|
19
|
+
#start solver after creating the model?
|
|
20
|
+
start_simulation = False
|
|
21
|
+
run_command = ['./run_sim']
|
|
22
|
+
|
|
23
|
+
# ===================== input files and path settings =======================
|
|
24
|
+
|
|
25
|
+
gds_filename = "pcb_lowpass.gds" # geometries
|
|
26
|
+
XML_filename = "pcb_ro4003.xml" # stackup
|
|
27
|
+
|
|
28
|
+
# preprocess GDSII for safe handling of cutouts/holes?
|
|
29
|
+
preprocess_gds = True
|
|
30
|
+
|
|
31
|
+
# merge via polygons with distance less than .. microns, set to 0 to disable via merging.
|
|
32
|
+
merge_polygon_size = 0
|
|
33
|
+
|
|
34
|
+
# get path for this simulation file
|
|
35
|
+
script_path = utilities.get_script_path(__file__)
|
|
36
|
+
|
|
37
|
+
# use script filename as model basename
|
|
38
|
+
model_basename = utilities.get_basename(__file__)
|
|
39
|
+
|
|
40
|
+
# set and create directory for simulation output
|
|
41
|
+
sim_path = utilities.create_sim_path (script_path,model_basename)
|
|
42
|
+
print('Simulation data directory: ', sim_path)
|
|
43
|
+
|
|
44
|
+
# change path to models script path
|
|
45
|
+
modelDir = os.path.dirname(os.path.abspath(__file__))
|
|
46
|
+
os.chdir(modelDir)
|
|
47
|
+
|
|
48
|
+
# ======================== simulation settings ================================
|
|
49
|
+
|
|
50
|
+
settings = {}
|
|
51
|
+
|
|
52
|
+
settings['unit'] = 1e-6 # geometry is in MILLIMETER for PCB example
|
|
53
|
+
settings['margin'] = 2000 # distance in microns from GDSII geometry boundary to simulation boundary
|
|
54
|
+
settings['air_around'] = [1000,1000,1000,1000,2000, 10000] # airbox size to simulation boundary
|
|
55
|
+
|
|
56
|
+
|
|
57
|
+
settings['fstart'] = 0.1e9
|
|
58
|
+
settings['fstop'] = 6.0e9
|
|
59
|
+
settings['fstep'] = 0.05e9
|
|
60
|
+
|
|
61
|
+
settings['refined_cellsize'] = 200 # mesh cell size in conductor region
|
|
62
|
+
settings['cells_per_wavelength'] = 10 # how many mesh cells per wavelength, must be 10 or more
|
|
63
|
+
|
|
64
|
+
settings['meshsize_max'] = 5000 # in project units, override cells_per_wavelength
|
|
65
|
+
settings['adaptive_mesh_iterations'] = 0
|
|
66
|
+
settings['z_thickness_factor'] = 1
|
|
67
|
+
|
|
68
|
+
# settings['nogui'] = True # create files without showing 3D model
|
|
69
|
+
# settings['nogui'] = ('nogui' in sys.argv) # check if nogui specified on command line, then create files without showing 3D model
|
|
70
|
+
|
|
71
|
+
|
|
72
|
+
# Ports from GDSII Data, polygon geometry from specified special layer
|
|
73
|
+
# Excitations can be switched off by voltage=0, those S-parameter will be incomplete then
|
|
74
|
+
|
|
75
|
+
simulation_ports = simulation_setup.all_simulation_ports()
|
|
76
|
+
# instead of in-plane port specified with target_layername, we here use via port specified with from_layername and to_layername
|
|
77
|
+
simulation_ports.add_port(simulation_setup.simulation_port(portnumber=1, voltage=1, port_Z0=50, source_layernum=201, from_layername='Bottom', to_layername='Top', direction='z'))
|
|
78
|
+
simulation_ports.add_port(simulation_setup.simulation_port(portnumber=2, voltage=0, port_Z0=50, source_layernum=202, from_layername='Bottom', to_layername='Top', direction='z'))
|
|
79
|
+
|
|
80
|
+
|
|
81
|
+
# ======================== simulation ================================
|
|
82
|
+
|
|
83
|
+
# get technology stackup data
|
|
84
|
+
materials_list, dielectrics_list, metals_list = stackup_reader.read_substrate (XML_filename)
|
|
85
|
+
# get list of layers from technology
|
|
86
|
+
layernumbers = metals_list.getlayernumbers()
|
|
87
|
+
layernumbers.extend(simulation_ports.portlayers)
|
|
88
|
+
|
|
89
|
+
# read geometries from GDSII, only purpose 0
|
|
90
|
+
allpolygons = gds_reader.read_gds(gds_filename, layernumbers, purposelist=[0], metals_list=metals_list, preprocess=preprocess_gds, merge_polygon_size=merge_polygon_size)
|
|
91
|
+
|
|
92
|
+
|
|
93
|
+
########### create model ###########
|
|
94
|
+
|
|
95
|
+
settings['simulation_ports'] = simulation_ports
|
|
96
|
+
settings['materials_list'] = materials_list
|
|
97
|
+
settings['dielectrics_list'] = dielectrics_list
|
|
98
|
+
settings['metals_list'] = metals_list
|
|
99
|
+
settings['layernumbers'] = layernumbers
|
|
100
|
+
settings['allpolygons'] = allpolygons
|
|
101
|
+
settings['sim_path'] = sim_path
|
|
102
|
+
settings['model_basename'] = model_basename
|
|
103
|
+
|
|
104
|
+
|
|
105
|
+
# list of ports that are excited (set voltage to zero in port excitation to skip an excitation!)
|
|
106
|
+
excite_ports = simulation_ports.all_active_excitations()
|
|
107
|
+
config_name, data_dir = simulation_setup.create_palace (excite_ports, settings)
|
|
108
|
+
|
|
109
|
+
|
|
110
|
+
# for convenience, write run script to model directory
|
|
111
|
+
utilities.create_run_script(sim_path)
|
|
112
|
+
|
|
113
|
+
|
|
114
|
+
if start_simulation:
|
|
115
|
+
try:
|
|
116
|
+
os.chdir(sim_path)
|
|
117
|
+
subprocess.run(run_command, shell=True)
|
|
118
|
+
except:
|
|
119
|
+
print(f"Unable to run Palace using command ",run_command)
|
|
120
|
+
|
|
@@ -0,0 +1,120 @@
|
|
|
1
|
+
# MODEL FOR GMSH WITH PALACE
|
|
2
|
+
|
|
3
|
+
import os
|
|
4
|
+
import sys
|
|
5
|
+
import subprocess
|
|
6
|
+
|
|
7
|
+
# we expect gds2palace in the same directory as this model file
|
|
8
|
+
sys.path.insert(0, os.path.abspath(os.path.join(os.path.dirname(__file__), 'gds2palace')))
|
|
9
|
+
from gds2palace import *
|
|
10
|
+
|
|
11
|
+
|
|
12
|
+
# Model comments
|
|
13
|
+
#
|
|
14
|
+
# Balun from D-Band phase shifter design by Rupok Das, Neural Semi, in Tapeout July 2025
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15
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+
# Design frequency 140-170 GHz
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16
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+
# https://github.com/IHP-GmbH/TO_July2025/tree/main/FMD_QNC_D_Band_Phase_Shifter
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17
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+
# Ports: Model uses a via port that is defined between Metal3 and TopMetal2
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18
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+
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19
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+
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20
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+
# ======================== workflow settings ================================
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21
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+
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22
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+
# preview model/mesh only, without running solver?
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23
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+
start_simulation = False
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24
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+
run_command = ['start', 'wsl.exe']
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25
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+
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26
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+
# ===================== input files and path settings =======================
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27
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+
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28
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+
gds_filename = "Balun_140-170G_RupokDas_with_ports.gds" # geometries
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29
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+
XML_filename = "SG13G2_nosub.xml" # stackup
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30
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+
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31
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+
# preprocess GDSII for safe handling of cutouts/holes?
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32
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+
preprocess_gds = False
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|
33
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+
|
|
34
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+
# merge via polygons with distance less than .. microns, set to 0 to disable via merging.
|
|
35
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+
merge_polygon_size = 2.0
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|
36
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+
|
|
37
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+
# get path for this simulation file
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|
38
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+
script_path = utilities.get_script_path(__file__)
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|
39
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+
|
|
40
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+
# use script filename as model basename
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|
41
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+
model_basename = utilities.get_basename(__file__)
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|
42
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+
|
|
43
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+
# set and create directory for simulation output
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|
44
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+
sim_path = utilities.create_sim_path (script_path,model_basename)
|
|
45
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+
print('Simulation data directory: ', sim_path)
|
|
46
|
+
|
|
47
|
+
# change path to models script path
|
|
48
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+
modelDir = os.path.dirname(os.path.abspath(__file__))
|
|
49
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+
os.chdir(modelDir)
|
|
50
|
+
|
|
51
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+
# ======================== simulation settings ================================
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|
52
|
+
|
|
53
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+
settings = {}
|
|
54
|
+
|
|
55
|
+
settings['unit'] = 1e-6 # geometry is in microns
|
|
56
|
+
settings['margin'] = 50 # distance in microns from GDSII geometry boundary to simulation boundary
|
|
57
|
+
|
|
58
|
+
settings['fstart'] = 100e9
|
|
59
|
+
settings['fstop'] = 200e9
|
|
60
|
+
settings['fstep'] = 1e9
|
|
61
|
+
|
|
62
|
+
settings['refined_cellsize'] = 2 # mesh cell size in conductor region
|
|
63
|
+
settings['cells_per_wavelength'] = 10 # how many mesh cells per wavelength, must be 10 or more
|
|
64
|
+
|
|
65
|
+
settings['meshsize_max'] = 70 # microns, override cells_per_wavelength
|
|
66
|
+
settings['adaptive_mesh_iterations'] = 0
|
|
67
|
+
settings['z_thickness_factor'] = 0.33
|
|
68
|
+
|
|
69
|
+
|
|
70
|
+
# ports from GDSII Data, polygon geometry from specified special layer
|
|
71
|
+
# note that for multiport simulation, excitations are switched on/off in simulation_setup.createSimulation below
|
|
72
|
+
|
|
73
|
+
simulation_ports = simulation_setup.all_simulation_ports()
|
|
74
|
+
# instead of in-plane port specified with target_layername, we here use via port specified with from_layername and to_layername
|
|
75
|
+
simulation_ports.add_port(simulation_setup.simulation_port(portnumber=1, voltage=1, port_Z0=50, source_layernum=201, from_layername='Metal3', to_layername='TopMetal2', direction='z'))
|
|
76
|
+
simulation_ports.add_port(simulation_setup.simulation_port(portnumber=2, voltage=1, port_Z0=50, source_layernum=202, from_layername='Metal3', to_layername='TopMetal2', direction='z'))
|
|
77
|
+
simulation_ports.add_port(simulation_setup.simulation_port(portnumber=3, voltage=1, port_Z0=50, source_layernum=203, from_layername='Metal3', to_layername='TopMetal2', direction='z'))
|
|
78
|
+
|
|
79
|
+
|
|
80
|
+
# ======================== simulation ================================
|
|
81
|
+
|
|
82
|
+
# get technology stackup data
|
|
83
|
+
materials_list, dielectrics_list, metals_list = stackup_reader.read_substrate (XML_filename)
|
|
84
|
+
# get list of layers from technology
|
|
85
|
+
layernumbers = metals_list.getlayernumbers()
|
|
86
|
+
layernumbers.extend(simulation_ports.portlayers)
|
|
87
|
+
|
|
88
|
+
# read geometries from GDSII, only purpose 0
|
|
89
|
+
allpolygons = gds_reader.read_gds(gds_filename, layernumbers, purposelist=[0], metals_list=metals_list, preprocess=preprocess_gds, merge_polygon_size=merge_polygon_size)
|
|
90
|
+
|
|
91
|
+
|
|
92
|
+
########### create model ###########
|
|
93
|
+
|
|
94
|
+
settings['simulation_ports'] = simulation_ports
|
|
95
|
+
settings['materials_list'] = materials_list
|
|
96
|
+
settings['dielectrics_list'] = dielectrics_list
|
|
97
|
+
settings['metals_list'] = metals_list
|
|
98
|
+
settings['layernumbers'] = layernumbers
|
|
99
|
+
settings['allpolygons'] = allpolygons
|
|
100
|
+
settings['sim_path'] = sim_path
|
|
101
|
+
settings['model_basename'] = model_basename
|
|
102
|
+
|
|
103
|
+
|
|
104
|
+
# list of ports that are excited (set voltage to zero in port excitation to skip an excitation!)
|
|
105
|
+
excite_ports = simulation_ports.all_active_excitations()
|
|
106
|
+
config_name, data_dir = simulation_setup.create_palace (excite_ports, settings)
|
|
107
|
+
|
|
108
|
+
|
|
109
|
+
# for convenience, write run script to model directory
|
|
110
|
+
utilities.create_run_script(sim_path)
|
|
111
|
+
|
|
112
|
+
|
|
113
|
+
if start_simulation:
|
|
114
|
+
try:
|
|
115
|
+
os.chdir(sim_path)
|
|
116
|
+
subprocess.run(run_command, shell=True)
|
|
117
|
+
except:
|
|
118
|
+
print(f"Unable to run Palace using command ",run_command)
|
|
119
|
+
|
|
120
|
+
|