pyVHDLModelTreesitter 0.9.0__tar.gz → 0.10.0__tar.gz

{pyvhdlmodeltreesitter-0.9.0 → pyvhdlmodeltreesitter-0.10.0}/PKG-INFO

@@ -1,14 +1,15 @@
-Metadata-Version: 2.4
+Metadata-Version: 2.5
 Name: pyVHDLModelTreesitter
-Version: 0.9.0
+Version: 0.10.0
 Summary: An implementation of pyVHDLModel using treesitter
 Project-URL: Repository, https://gitlab.com/dawalters/pyVHDLModelTreesitter
 Author: Dominic Adam Walters
+License-Expression: Apache-2.0
 License-File: LICENSE
 Keywords: language,model,treesitter,vhdl
 Classifier: Development Status :: 3 - Alpha
 Classifier: Intended Audience :: Developers
-Classifier: License :: OSI Approved :: MIT License
+Classifier: License :: OSI Approved :: Apache Software License
 Classifier: Programming Language :: Python :: 3 :: Only
 Classifier: Programming Language :: Python :: 3.11
 Classifier: Programming Language :: Python :: 3.12
@@ -18,24 +19,27 @@ Requires-Python: >=3.11
 Requires-Dist: pygments>=2.20.0
 Requires-Dist: pyvhdlmodel>=0.38.0
 Requires-Dist: rich>=11.0.0
-Requires-Dist: tree-sitter-vhdl>=1.2.5
+Requires-Dist: tree-sitter-vhdl>=2.0.0
 Requires-Dist: tree-sitter>=0.23.0
 Provides-Extra: dev
-Requires-Dist: coverage>=7.15.2; extra == 'dev'
+Requires-Dist: codespell>=2.4.3; extra == 'dev'
+Requires-Dist: coverage>=7.15.4; extra == 'dev'
 Requires-Dist: cryptography>=49.0.0; extra == 'dev'
-Requires-Dist: hatch>=1.17.1; extra == 'dev'
+Requires-Dist: git-cliff>=2.13.1; extra == 'dev'
+Requires-Dist: hatch>=1.18.0; extra == 'dev'
 Requires-Dist: idna>=3.18; extra == 'dev'
 Requires-Dist: jaraco-context>=6.1.2; extra == 'dev'
-Requires-Dist: mypy>=2.3.0; extra == 'dev'
-Requires-Dist: pre-commit>=4.6.1; extra == 'dev'
+Requires-Dist: mypy>=2.3.1; extra == 'dev'
+Requires-Dist: pre-commit>=4.6.2; extra == 'dev'
 Requires-Dist: pytest-cov>=7.1.0; extra == 'dev'
 Requires-Dist: pytest-order>=1.5.0; extra == 'dev'
 Requires-Dist: pytest-sugar>=1.1.1; extra == 'dev'
 Requires-Dist: pytest-xdist>=3.8.0; extra == 'dev'
 Requires-Dist: pytest>=9.1.1; extra == 'dev'
-Requires-Dist: ruff>=0.16.1; extra == 'dev'
-Requires-Dist: ty>=0.0.65; extra == 'dev'
-Requires-Dist: uv>=0.12.0; extra == 'dev'
+Requires-Dist: ruff>=0.16.4; extra == 'dev'
+Requires-Dist: ty>=0.0.74; extra == 'dev'
+Requires-Dist: uv>=0.12.5; extra == 'dev'
+Requires-Dist: vsg>=3.35.0; extra == 'dev'
 Description-Content-Type: text/markdown
 
 # pyVHDLModelTreesitter
@@ -50,8 +54,13 @@ Description-Content-Type: text/markdown
 [`pyVHDLModel`][pyVHDLModel-github] API using
 [`tree-sitter-vhdl`][tree-sitter-vhdl].
 
-> Disclaimer: This project is in early development and only implements a
-              fraction of the features of [`pyVHDLModel`][pyVHDLModel-github].
+## Implementation Status Disclaimer
+
+This project is in early development and only implements a fraction of the
+features of [`pyVHDLModel`][pyVHDLModel-github].
+
+A complete breakdown of the current implementation status is available in
+[`docs/IMPLEMENTATION_STATUS.md`](/docs/IMPLEMENTATION_STATUS.md).
 
 ## Installation
 
@@ -83,10 +92,12 @@ document = pyVHDLModelTreesitter.Document.from_file("path/to/file.vhd")
 
 Detailed documentation is available for [`pyVHDLModel`][pyVHDLModel-documentation].
 
-A complete list of public API endpoints is in [DOCS.md](DOCS.md).
+A complete list of public API endpoints is in [`docs/API.md`](docs/API.md).
 
 ## Setup for Development
 
+See [`CONTRIBUTING.md`](CONTRIBUTING.md) for the full contribution guide.
+
 ### Dependencies
 
 Developers aiming to contribute to this repository need the following tools:

{pyvhdlmodeltreesitter-0.9.0 → pyvhdlmodeltreesitter-0.10.0}/README.md

@@ -10,8 +10,13 @@
 [`pyVHDLModel`][pyVHDLModel-github] API using
 [`tree-sitter-vhdl`][tree-sitter-vhdl].
 
-> Disclaimer: This project is in early development and only implements a
-              fraction of the features of [`pyVHDLModel`][pyVHDLModel-github].
+## Implementation Status Disclaimer
+
+This project is in early development and only implements a fraction of the
+features of [`pyVHDLModel`][pyVHDLModel-github].
+
+A complete breakdown of the current implementation status is available in
+[`docs/IMPLEMENTATION_STATUS.md`](/docs/IMPLEMENTATION_STATUS.md).
 
 ## Installation
 
@@ -43,10 +48,12 @@ document = pyVHDLModelTreesitter.Document.from_file("path/to/file.vhd")
 
 Detailed documentation is available for [`pyVHDLModel`][pyVHDLModel-documentation].
 
-A complete list of public API endpoints is in [DOCS.md](DOCS.md).
+A complete list of public API endpoints is in [`docs/API.md`](docs/API.md).
 
 ## Setup for Development
 
+See [`CONTRIBUTING.md`](CONTRIBUTING.md) for the full contribution guide.
+
 ### Dependencies
 
 Developers aiming to contribute to this repository need the following tools:

{pyvhdlmodeltreesitter-0.9.0 → pyvhdlmodeltreesitter-0.10.0}/pyproject.toml

@@ -4,16 +4,18 @@ build-backend = "hatchling.build"
 
 [project]
 name = "pyVHDLModelTreesitter"
-version = "0.9.0"
+version = "0.10.0"
 description = "An implementation of pyVHDLModel using treesitter"
 readme = "README.md"
+license = "Apache-2.0"
+license-files = ["LICENSE"]
 requires-python = ">=3.11"
 dependencies = [
     "pyVHDLModel >= 0.38.0",
     "rich >= 11.0.0",
         "pygments >= 2.20.0",  # forced to avoid CVE
     "tree-sitter >= 0.23.0",
-    "tree-sitter-vhdl >= 1.2.5",  # TODO: move to 1.6.0 once released
+    "tree-sitter-vhdl >= 2.0.0",
 ]
 authors = [
     { name = "Dominic Adam Walters" },
@@ -21,7 +23,7 @@ authors = [
 keywords = ["language", "model", "treesitter", "vhdl"]
 classifiers = [
     "Development Status :: 3 - Alpha",
-    "License :: OSI Approved :: MIT License",
+    "License :: OSI Approved :: Apache Software License",
     "Programming Language :: Python :: 3 :: Only",
     "Programming Language :: Python :: 3.11",
     "Programming Language :: Python :: 3.12",
@@ -32,21 +34,24 @@ classifiers = [
 
 [project.optional-dependencies]
 dev = [
-    "coverage >= 7.15.2",
-    "hatch >= 1.17.1",
+    "codespell >= 2.4.3",
+    "coverage >= 7.15.4",
+    "git-cliff >= 2.13.1",
+    "hatch >= 1.18.0",
         "cryptography >= 49.0.0",  # forced to avoid CVE
         "idna >= 3.18",  # forced to avoid CVE
         "jaraco-context >= 6.1.2",  # forced to avoid CVE
-    "mypy >= 2.3.0",
-    "pre-commit >= 4.6.1",
+    "mypy >= 2.3.1",
+    "pre-commit >= 4.6.2",
     "pytest >= 9.1.1",
     "pytest-cov >= 7.1.0",
     "pytest-order >= 1.5.0",
     "pytest-sugar >= 1.1.1",
     "pytest-xdist >= 3.8.0",
-    "ruff >= 0.16.1",
-    "ty >= 0.0.65",
-    "uv >= 0.12.0",
+    "ruff >= 0.16.4",
+    "ty >= 0.0.74",
+    "uv >= 0.12.5",
+    "vsg >= 3.35.0",
 ]
 
 [project.urls]
@@ -54,6 +59,8 @@ Repository = "https://gitlab.com/dawalters/pyVHDLModelTreesitter"
 
 [tool.codespell]
 ignore-words-list = "inout"
+# CHANGELOG.md quotes historical commit messages verbatim
+exclude-file = "CHANGELOG.md"
 
 [tool.coverage.html]
 directory = ".htmlcov"
@@ -63,9 +70,15 @@ exclude_also = [
     "@overload",
     "if TYPE_CHECKING:",
 ]
+omit = [
+    "src/pyVHDLModelTreesitter/queries/_generated_queries.py",
+]
 
 [tool.coverage.run]
 branch = true
+omit = [
+    "src/pyVHDLModelTreesitter/queries/_generated_queries.py",
+]
 
 [tool.coverage.xml]
 output = ".coverage.xml"
@@ -96,11 +109,15 @@ strict = true
 warn_unreachable = true
 
 [tool.pytest.ini_options]
-addopts = "--capture=fd -n auto --dist loadgroup --cov=pyVHDLModelTreesitter --cov-report html --cov-report xml --verbose --junitxml=.junit.xml -o junit_family=legacy"
+addopts = "--capture=fd -n auto --dist loadgroup --strict-markers --cov=pyVHDLModelTreesitter --cov-report html --cov-report xml --verbose --junitxml=.junit.xml -o junit_family=legacy"
 norecursedirs = "oss/*"
 testpaths = [
     "tests",
 ]
+markers = [
+    "order: control test execution order relative to other tests (pytest-order)",
+    "xdist_group: run tests in the same group on the same xdist worker",
+]
 
 [tool.ruff]
 unsafe-fixes = true
@@ -141,6 +158,11 @@ required-imports = ["from __future__ import annotations"]
 "tests/**/*.py" = ["S101"]
 "tests/examples/local/**/*.py" = ["D100", "D103", "INP001", "TID252"]
 
+[tool.ty.src]
+exclude = [
+    "tests/examples/oss/**",
+]
+
 [tool.ty.rules]
 all = "error"
 missing-override-decorator = "ignore"  # this is emitted for every dunder override

pyvhdlmodeltreesitter-0.10.0/src/pyVHDLModelTreesitter/Declaration.py

@@ -0,0 +1,96 @@
+"""
+Submodule mirroring modified aspects of pyVHDLModel.Declaration.
+
+The :class:`Alias` class is overridden to add support for the signature that
+:class:`pyVHDLModel.Declaration.Alias` does not model.
+"""
+
+# ruff: file-ignore[invalid-argument-name, mixed-case-variable-in-class-scope, undocumented-public-init]
+
+from __future__ import annotations
+
+__all__ = [
+    "Alias",
+    "AliasSignature",
+]
+
+from typing import TYPE_CHECKING
+
+import pyVHDLModel
+from pyVHDLModel.Declaration import Alias as Alias_VHDLModel
+
+if TYPE_CHECKING:
+    from pyVHDLModel.Base import ModelEntity
+    from pyVHDLModel.Symbol import SimpleSubtypeSymbol
+
+
+class AliasSignature(pyVHDLModel.Base.ModelEntity):
+    """
+    Represents a signature in an alias declaration.
+
+    A signature is used to disambiguate overloaded subprograms and enumeration
+    literals, and has the form ``[ type_mark { , type_mark } [ return type_mark ] ]``.
+    """
+
+    _parameters: list[SimpleSubtypeSymbol]
+    _returnType: SimpleSubtypeSymbol | None
+
+    def __init__(
+        self,
+        parameters: list[SimpleSubtypeSymbol],
+        returnType: SimpleSubtypeSymbol | None = None,
+        parent: ModelEntity | None = None,
+    ) -> None:
+        super().__init__(parent)
+        self._parameters = parameters
+        self._returnType = returnType
+
+    @property
+    # ruff: ignore[invalid-function-name, undocumented-public-method]
+    def Parameters(self) -> list[SimpleSubtypeSymbol]:
+        return self._parameters
+
+    @property
+    # ruff: ignore[invalid-function-name, undocumented-public-method]
+    def ReturnType(self) -> SimpleSubtypeSymbol | None:
+        return self._returnType
+
+    def __str__(self) -> str:  # ruff: ignore[undocumented-magic-method]
+        parameters = ", ".join(str(parameter) for parameter in self._parameters)
+        result = "["
+        if parameters:
+            result += f" {parameters}"
+        if self._returnType is not None:
+            result += f" return {self._returnType}"
+        return f"{result} ]"
+
+
+class Alias(Alias_VHDLModel):
+    """An alias declaration with optional signature support."""
+
+    _signature: AliasSignature | None
+
+    # ruff: ignore[too-many-arguments, too-many-positional-arguments]
+    def __init__(
+        self,
+        identifier: str,
+        name: pyVHDLModel.Symbol.Symbol,
+        subtype: pyVHDLModel.Symbol.SubtypeSymbol | None = None,
+        signature: AliasSignature | None = None,
+        documentation: str = "",
+        parent: ModelEntity | None = None,
+    ) -> None:
+        super().__init__(identifier, name, subtype, documentation, parent)
+        self._signature = signature
+        if signature is not None:
+            signature.Parent = self
+
+    @property
+    # ruff: ignore[invalid-function-name, undocumented-public-method]
+    def Signature(self) -> AliasSignature | None:
+        return self._signature
+
+    def __str__(self) -> str:  # ruff: ignore[undocumented-magic-method]
+        subtype = f" : {self._subtype}" if self._subtype is not None else ""
+        signature = f" {self._signature}" if self._signature is not None else ""
+        return f"alias {self._identifier}{subtype} is {self._name}{signature}"

pyvhdlmodeltreesitter-0.10.0/src/pyVHDLModelTreesitter/Object.py

@@ -0,0 +1,52 @@
+"""
+Submodule mirroring modified aspects of pyVHDLModel.Object.
+
+The :class:`File` class is overridden to add support for the file open
+information that :class:`pyVHDLModel.Object.File` does not model.
+"""
+
+from __future__ import annotations
+
+__all__ = [
+    "File",
+]
+
+from typing import TYPE_CHECKING
+
+import pyVHDLModel
+
+if TYPE_CHECKING:
+    from pyVHDLModel.Base import ModelEntity
+    from pyVHDLModel.Expression import EnumerationLiteral, StringLiteral
+    from pyVHDLModel.Symbol import Symbol
+
+
+class File(pyVHDLModel.Object.File):
+    """A file declaration with optional file open information."""
+
+    _fileOpenKind: EnumerationLiteral | None  # ruff: ignore[mixed-case-variable-in-class-scope]
+    _fileLogicalName: StringLiteral | None  # ruff: ignore[mixed-case-variable-in-class-scope]
+
+    # ruff: ignore[too-many-arguments, too-many-positional-arguments, undocumented-public-init]
+    def __init__(
+        self,
+        identifiers: list[str],
+        subtype: Symbol,
+        fileOpenKind: EnumerationLiteral | None = None,  # ruff: ignore[invalid-argument-name]
+        fileLogicalName: StringLiteral | None = None,  # ruff: ignore[invalid-argument-name]
+        documentation: str = "",
+        parent: ModelEntity | None = None,
+    ) -> None:
+        super().__init__(identifiers, subtype, documentation, parent)
+        self._fileOpenKind = fileOpenKind
+        self._fileLogicalName = fileLogicalName
+
+    @property
+    # ruff: ignore[invalid-function-name, undocumented-public-method]
+    def fileOpenKind(self) -> EnumerationLiteral | None:
+        return self._fileOpenKind
+
+    @property
+    # ruff: ignore[invalid-function-name, undocumented-public-method]
+    def fileLogicalName(self) -> StringLiteral | None:
+        return self._fileLogicalName

{pyvhdlmodeltreesitter-0.9.0 → pyvhdlmodeltreesitter-0.10.0}/src/pyVHDLModelTreesitter/_Association.py

@@ -10,15 +10,10 @@ from typing import TYPE_CHECKING, TypeVar
 
 from pyVHDLModel.Association import AssociationItem
 from pyVHDLModel.Name import OpenName
-from pyVHDLModel.Symbol import SignalSymbol
 
 from pyVHDLModelTreesitter._Name import parse_name
-from pyVHDLModelTreesitter.queries import AssociationElement
-from pyVHDLModelTreesitter.queries._protocol import inject_node
-from pyVHDLModelTreesitter.queries._utils import (
-    get_node,
-    get_node_text,
-)
+from pyVHDLModelTreesitter.queries import AssociationElementQuery
+from pyVHDLModelTreesitter.treesitter import get_node_text, inject_node
 
 if TYPE_CHECKING:
     import pyVHDLModel
@@ -30,23 +25,22 @@ T = TypeVar("T", bound=AssociationItem)
 
 def parse_association_item(cls: type[T], node: tree_sitter.Node) -> T | None:
     """Create an AssociationItem from a tree-sitter node."""
-    captures = AssociationElement.capture_first_root(node)
-    formal_node = get_node(node, captures, "formal", optional=True)
+    captures = AssociationElementQuery.capture_first_root(node)
+    formal_node = captures.get_node(node, "formal", optional=True)
     formal = None
     if formal_node is not None:
-        formal = SignalSymbol(parse_name(get_node_text(formal_node)))
-    actual_node = get_node(node, captures, "actual")
+        formal = parse_name(get_node_text(formal_node))
+    actual_node = captures.get_node(node, "actual")
     actual: pyVHDLModel.Base.ExpressionUnion
     if actual_node.type == "OPEN":
         actual = OpenName()
     else:
         # ruff: ignore[import-outside-top-level]
-        from pyVHDLModelTreesitter._parse import parse_conditional_expression
+        from pyVHDLModelTreesitter._Expression import parse_conditional_expression
 
         actual = parse_conditional_expression(actual_node)
         if actual is None:
             return None
-    # TODO: `formal` is a `SignalSymbol`, is this correct?
     # TODO: `OpenName` might need wrapping in a `Symbol`
     # ty: ignore[invalid-argument-type]
     ret = cls(formal, actual)  # type: ignore[arg-type]

{pyvhdlmodeltreesitter-0.9.0 → pyvhdlmodeltreesitter-0.10.0}/src/pyVHDLModelTreesitter/_Base.py

@@ -5,19 +5,27 @@ from __future__ import annotations
 __all__ = [
     "parse_direction",
     "parse_mode",
+    "parse_range_attribute",
     "parse_simple_range",
     "parse_waveform_element",
+    "parse_waveform_elements",
 ]
 
 from typing import TYPE_CHECKING
 
 import pyVHDLModel
-from pyVHDLModel.Base import SimpleRange, WaveformElement
+from pyVHDLModel.Base import RangeFromName, SimpleRange, WaveformElement
+from pyVHDLModel.Name import AttributeName
+from pyVHDLModel.Symbol import RangeAttributeSymbol
 
 if TYPE_CHECKING:
     from tree_sitter import Node
 
-from pyVHDLModelTreesitter._parse import parse_simple_expression
+from pyVHDLModelTreesitter._Expression import parse_simple_expression
+from pyVHDLModelTreesitter._Name import parse_name
+from pyVHDLModelTreesitter._parse import (
+    _parse_enum_string,
+)
 from pyVHDLModelTreesitter.error import (
     NodeExtraChildError,
     NodeMissingChildError,
@@ -25,12 +33,17 @@ from pyVHDLModelTreesitter.error import (
     NodeTextIsNoneError,
     NotImplementedWarning,
 )
-from pyVHDLModelTreesitter.queries._protocol import inject_node
+from pyVHDLModelTreesitter.treesitter._access import get_node_text
+from pyVHDLModelTreesitter.treesitter._map import inject_node
 
 
-def parse_direction(string: str) -> pyVHDLModel.Base.Direction | None:
+def parse_direction(node: Node | None) -> pyVHDLModel.Base.Direction | None:
     """
-    Parse a string as a direction.
+    Parse a tree-sitter direction node.
+
+    Extracts the text from a direction node and resolves it to a
+    :class:`pyVHDLModel.Base.Direction` enum value.  Returns ``None`` if the text
+    does not match any known direction.
 
     This will accept any mix of the following:
         - Incorrect capitalisation
@@ -39,19 +52,23 @@ def parse_direction(string: str) -> pyVHDLModel.Base.Direction | None:
         - Split words with whitespace
             - "down to"
     """
-    # TODO: make a PR on pyVHDLModel to add this
-    string = "".join(string.split()).lower().capitalize()
-    if string == "Downto":
-        string = "DownTo"
-    try:
-        return pyVHDLModel.Base.Direction[string]
-    except IndexError:
+    if node is None:
         return None
+    string = get_node_text(node)
+    return _parse_enum_string(
+        string,
+        pyVHDLModel.Base.Direction,
+        renames={"Downto": "DownTo"},
+    )
 
 
-def parse_mode(string: str) -> pyVHDLModel.Base.Mode | None:
+def parse_mode(node: Node | None) -> pyVHDLModel.Base.Mode | None:
     """
-    Parse a string as a mode.
+    Parse a tree-sitter mode node.
+
+    Extracts the text from a mode node and resolves it to a
+    :class:`pyVHDLModel.Base.Mode` enum value.  Returns ``None`` if the text does
+    not match any known mode.
 
     This will accept any mix of the following:
         - Incorrect capitalisation
@@ -61,14 +78,60 @@ def parse_mode(string: str) -> pyVHDLModel.Base.Mode | None:
         - Split words with whitespace
             - "in out"
     """
-    # TODO: make a PR on pyVHDLModel to add this
-    string = "".join(string.split()).lower().capitalize()
-    if string == "Inout":
-        string = "InOut"
-    try:
-        return pyVHDLModel.Base.Mode[string]
-    except IndexError:
+    if node is None:
+        return pyVHDLModel.Base.Mode.In
+    string = get_node_text(node)
+    parsed = _parse_enum_string(
+        string,
+        pyVHDLModel.Base.Mode,
+        renames={"Inout": "InOut"},
+    )
+    if parsed is None:
+        normalized = "".join(string.split()).lower().capitalize()
+        NotImplementedWarning.warn(
+            f"'{normalized}' is not a supported interface mode",
+            node,
+        )
+    return parsed
+
+
+def parse_range_attribute(  # ruff: ignore[complex-structure, too-many-return-statements]
+    node: Node,
+) -> RangeFromName | None:
+    """
+    Check if a conditional_expression node represents a range attribute.
+
+    For example, parses ``s'range`` into a `RangeFromName`.
+    Returns `None` if the node is not a range attribute.
+    """
+    if node.type != "conditional_expression":
+        return None
+    if node.child_count != 1:
+        return None
+    simple_expr = node.children[0]
+    if simple_expr.type != "simple_expression":
         return None
+    if simple_expr.child_count != 1:
+        return None
+    name_node = simple_expr.children[0]
+    if name_node.type != "name":
+        return None
+    prefix_identifier = None
+    has_range_attr = False
+    for nc in name_node.children:
+        if nc.type == "identifier":
+            prefix_identifier = nc
+        elif nc.type == "attribute":
+            for ac in nc.children:
+                if ac.type == "attribute_range":
+                    has_range_attr = True
+                    break
+    if has_range_attr and prefix_identifier is not None:
+        prefix_text = get_node_text(prefix_identifier)
+        prefix_name = parse_name(prefix_text)
+        attr_name = AttributeName("range", prefix_name)
+        return RangeFromName(RangeAttributeSymbol(attr_name))
+    return None
 
 
 def parse_simple_range(node: Node) -> SimpleRange | None:  # ruff: ignore[complex-structure, too-many-branches]
@@ -109,7 +172,6 @@ def parse_simple_range(node: Node) -> SimpleRange | None:  # ruff: ignore[comple
         return None
     if direction_node.text is None or len(direction_node.text) == 0:
         raise NodeTextIsNoneError(direction_node)
-    direction_str = direction_node.text.decode("utf-8")
     right = node.child(2)
     if right is None:
         raise NodeMissingChildError(node, "third-child")
@@ -124,8 +186,9 @@ def parse_simple_range(node: Node) -> SimpleRange | None:  # ruff: ignore[comple
     right_expr = parse_simple_expression(right)
     if right_expr is None:
         return None
-    direction = parse_direction(direction_str)
+    direction = parse_direction(direction_node)
     if direction is None:
+        direction_str = direction_node.text.decode("utf-8")
         raise NodeTextIsInvalidError(
             node,
             f"'{direction_str}' is not a valid VHDL direction",
@@ -152,3 +215,12 @@ def parse_waveform_element(node: Node) -> WaveformElement | None:
     if expression is None:
         return None
     return inject_node(WaveformElement(expression), node)
+
+
+def parse_waveform_elements(node: Node) -> list[WaveformElement]:
+    return [
+        we
+        for child in node.children
+        if child.type == "waveform_element"
+        if (we := parse_waveform_element(child)) is not None
+    ]

pyvhdlmodeltreesitter-0.10.0/src/pyVHDLModelTreesitter/_Common.py

@@ -0,0 +1,60 @@
+"""Submodule defining parsers for classes from pyVHDLModel.Common."""
+
+from __future__ import annotations
+
+__all__ = [
+    "parse_conditional_waveforms",
+]
+
+from typing import TYPE_CHECKING
+
+from pyVHDLModel.Common import ConditionalWaveform
+
+if TYPE_CHECKING:
+    import tree_sitter
+
+from pyVHDLModelTreesitter._Base import parse_waveform_elements
+from pyVHDLModelTreesitter._Expression import parse_simple_expression
+from pyVHDLModelTreesitter.queries import ConditionalWaveformsQuery
+from pyVHDLModelTreesitter.treesitter import sort_into_text_order
+
+
+def parse_conditional_waveforms(
+    node: tree_sitter.Node,
+) -> list[ConditionalWaveform] | None:
+    """Parse a ``conditional_waveforms`` node into a list of ``ConditionalWaveform``."""
+    captures = ConditionalWaveformsQuery.capture_first_root(node)
+    waveform_node = captures.get_node(node, "waveform")
+    condition_nodes = sort_into_text_order(
+        captures.get_nodes(node, "when_expression"),
+    )
+    other_waveform_nodes = sort_into_text_order(
+        captures.get_nodes(node, "else_waveform"),
+    )
+
+    result: list[ConditionalWaveform] = []
+
+    next_waveform_node = waveform_node
+    for condition_node, other_waveform_node in zip(
+        condition_nodes,
+        other_waveform_nodes,
+        strict=True,
+    ):
+        waveform = parse_waveform_elements(next_waveform_node)
+        if len(waveform) == 0:
+            # TODO: message
+            return None
+        condition = parse_simple_expression(condition_node)
+        if condition is None:
+            # TODO: message
+            return None
+        result.append(
+            ConditionalWaveform(waveform=waveform, condition=condition),
+        )
+        next_waveform_node = other_waveform_node
+    else_waveform = parse_waveform_elements(next_waveform_node)
+    if len(else_waveform) == 0:
+        # TODO: message
+        return None
+    result.append(ConditionalWaveform(waveform=else_waveform, condition=None))
+    return result