pyVHDLModelTreesitter 0.7.0__tar.gz → 0.7.1__tar.gz

{pyvhdlmodeltreesitter-0.7.0 → pyvhdlmodeltreesitter-0.7.1}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: pyVHDLModelTreesitter
-Version: 0.7.0
+Version: 0.7.1
 Summary: An implementation of pyVHDLModel using treesitter
 Project-URL: Repository, https://gitlab.com/dawalters/pyVHDLModelTreesitter
 Author: Dominic Adam Walters

{pyvhdlmodeltreesitter-0.7.0 → pyvhdlmodeltreesitter-0.7.1}/pyproject.toml

@@ -4,7 +4,7 @@ build-backend = "hatchling.build"
 
 [project]
 name = "pyVHDLModelTreesitter"
-version = "0.7.0"
+version = "0.7.1"
 description = "An implementation of pyVHDLModel using treesitter"
 readme = "README.md"
 requires-python = ">=3.11"

{pyvhdlmodeltreesitter-0.7.0 → pyvhdlmodeltreesitter-0.7.1}/src/pyVHDLModelTreesitter/Association.py

@@ -22,7 +22,7 @@ from pyVHDLModel.Association import (
     PortAssociationItem as pyVHDLModel_PortAssociationItem,
 )
 
-from pyVHDLModelTreesitter.Name import parse_name
+from pyVHDLModelTreesitter.Name import OpenName, parse_name
 from pyVHDLModelTreesitter.Symbol import SimpleObjectOrFunctionCallSymbol
 from pyVHDLModelTreesitter.treesitter import (
     TreesitterNodeMixin,
@@ -32,6 +32,7 @@ from pyVHDLModelTreesitter.treesitter import (
 from pyVHDLModelTreesitter.treesitter.query import AssociationElement
 
 if TYPE_CHECKING:
+    import pyVHDLModel
     import tree_sitter
 
 
@@ -50,12 +51,16 @@ class AssociationItemMixin(TreesitterNodeMixin, pyVHDLModel_AssociationItem):
                 parse_name(get_node_text(formal_node)),
             )
         actual_node = get_node(node, captures, "actual")
-        # ruff: ignore[import-outside-top-level]
-        from pyVHDLModelTreesitter._parse import parse_conditional_expression
-
-        actual = parse_conditional_expression(actual_node)
-        if actual is None:
-            return []
+        actual: pyVHDLModel.Base.ExpressionUnion
+        if actual_node.type == "OPEN":
+            actual = SimpleObjectOrFunctionCallSymbol(OpenName())
+        else:
+            # ruff: ignore[import-outside-top-level]
+            from pyVHDLModelTreesitter._parse import parse_conditional_expression
+
+            actual = parse_conditional_expression(actual_node)
+            if actual is None:
+                return []
         return [cls(actual, formal, _treesitter_node=node)]
 
     def __eq__(self, other: object) -> bool:

{pyvhdlmodeltreesitter-0.7.0 → pyvhdlmodeltreesitter-0.7.1}/src/pyVHDLModelTreesitter/Concurrent.py

@@ -36,6 +36,7 @@ from pyVHDLModelTreesitter.treesitter import (
     get_node,
     get_node_text,
     get_nodes,
+    sort_into_text_order,
 )
 from pyVHDLModelTreesitter.treesitter.query import (
     ComponentInstantiationStatement,
@@ -54,16 +55,16 @@ def _parse_instantiation_common(
 ) -> tuple[str, list[Any], list[Any]]:
     label_node = get_node(node, captures, "label")
     label = get_node_text(label_node)
-    generic_associations = []
-    for association_node in get_nodes(node, captures, "generics", optional=True):
-        generic_associations.extend(
-            GenericAssociationItem.from_treesitter_node(association_node),
-        )
-    port_associations = []
-    for association_node in get_nodes(node, captures, "ports", optional=True):
-        port_associations.extend(
-            PortAssociationItem.from_treesitter_node(association_node),
-        )
+    generic_associations = sort_into_text_order(
+        association
+        for association_node in get_nodes(node, captures, "generics", optional=True)
+        for association in GenericAssociationItem.from_treesitter_node(association_node)
+    )
+    port_associations = sort_into_text_order(
+        association
+        for association_node in get_nodes(node, captures, "ports", optional=True)
+        for association in PortAssociationItem.from_treesitter_node(association_node)
+    )
     return label, generic_associations, port_associations
 
 

{pyvhdlmodeltreesitter-0.7.0 → pyvhdlmodeltreesitter-0.7.1}/src/pyVHDLModelTreesitter/Name.py

@@ -6,6 +6,7 @@ __all__ = [
     "AttributeName",
     "IndexedName",
     "Name",
+    "OpenName",
     "SelectedName",
     "SimpleName",
     "SlicedName",
@@ -23,6 +24,9 @@ from pyVHDLModel.Name import (
 from pyVHDLModel.Name import (
     Name as VHDLModel_Name,
 )
+from pyVHDLModel.Name import (
+    OpenName as VHDLModel_OpenName,
+)
 from pyVHDLModel.Name import (
     SelectedName as VHDLModel_SelectedName,
 )
@@ -86,6 +90,10 @@ class SelectedName(VHDLModel_SelectedName, Name):  # ruff: ignore[undocumented-p
     pass
 
 
+class OpenName(VHDLModel_OpenName, Name):  # ruff: ignore[undocumented-public-class]
+    pass
+
+
 class SimpleName(VHDLModel_SimpleName, Name):  # ruff: ignore[undocumented-public-class]
     pass
 

pyvhdlmodeltreesitter-0.7.1/src/pyVHDLModelTreesitter/treesitter/queries/association_element.scm

@@ -0,0 +1,7 @@
+(association_element
+  (name)? @formal
+  [
+    (conditional_expression) @actual
+    (OPEN) @actual
+  ]
+) @root

pyvhdlmodeltreesitter-0.7.0/src/pyVHDLModelTreesitter/treesitter/queries/association_element.scm

@@ -1,4 +0,0 @@
-(association_element
-  (name)? @formal
-  (conditional_expression) @actual
-) @root