pyVHDLModelTreesitter 0.5.0__tar.gz → 0.5.2__tar.gz

{pyvhdlmodeltreesitter-0.5.0 → pyvhdlmodeltreesitter-0.5.2}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: pyVHDLModelTreesitter
-Version: 0.5.0
+Version: 0.5.2
 Summary: An implementation of pyVHDLModel using treesitter
 Project-URL: Repository, https://gitlab.com/dawalters/pyVHDLModelTreesitter
 Author: Dominic Adam Walters
@@ -15,7 +15,9 @@ Classifier: Programming Language :: Python :: 3.12
 Classifier: Programming Language :: Python :: 3.13
 Classifier: Programming Language :: Python :: 3.14
 Requires-Python: >=3.11
-Requires-Dist: pyvhdlmodel>=0.32.0
+Requires-Dist: pygments>=2.20.0
+Requires-Dist: pyvhdlmodel>=0.34.0
+Requires-Dist: rich>=11.0.0
 Requires-Dist: tree-sitter-vhdl>=1.2.5
 Requires-Dist: tree-sitter>=0.23.0
 Provides-Extra: dev
@@ -26,13 +28,11 @@ Requires-Dist: idna==3.16; extra == 'dev'
 Requires-Dist: jaraco-context==6.1.2; extra == 'dev'
 Requires-Dist: mypy==2.1.0; extra == 'dev'
 Requires-Dist: pre-commit==4.6.0; extra == 'dev'
-Requires-Dist: pygments==2.20.0; extra == 'dev'
 Requires-Dist: pytest-cov==7.1.0; extra == 'dev'
 Requires-Dist: pytest-order==1.4.0; extra == 'dev'
 Requires-Dist: pytest-sugar==1.1.1; extra == 'dev'
 Requires-Dist: pytest-xdist==3.8.0; extra == 'dev'
 Requires-Dist: pytest==9.0.3; extra == 'dev'
-Requires-Dist: rich==15.0.0; extra == 'dev'
 Requires-Dist: ruff==0.15.14; extra == 'dev'
 Requires-Dist: ty==0.0.39; extra == 'dev'
 Requires-Dist: uv==0.11.16; extra == 'dev'

{pyvhdlmodeltreesitter-0.5.0 → pyvhdlmodeltreesitter-0.5.2}/pyproject.toml

@@ -4,12 +4,14 @@ build-backend = "hatchling.build"
 
 [project]
 name = "pyVHDLModelTreesitter"
-version = "0.5.0"
+version = "0.5.2"
 description = "An implementation of pyVHDLModel using treesitter"
 readme = "README.md"
 requires-python = ">=3.11"
 dependencies = [
-    "pyVHDLModel >= 0.32.0",
+    "pyVHDLModel >= 0.34.0",
+    "rich >= 11.0.0",
+        "pygments >= 2.20.0",  # forced to avoid CVE
     "tree-sitter >= 0.23.0",
     "tree-sitter-vhdl >= 1.2.5",
 ]
@@ -42,8 +44,6 @@ dev = [
     "pytest-order == 1.4.0",
     "pytest-sugar == 1.1.1",
     "pytest-xdist == 3.8.0",
-    "rich == 15.0.0",
-        "pygments == 2.20.0",  # forced to avoid CVE
     "ruff == 0.15.14",
     "ty == 0.0.39",
     "uv == 0.11.16",

{pyvhdlmodeltreesitter-0.5.0 → pyvhdlmodeltreesitter-0.5.2}/src/pyVHDLModelTreesitter/DesignUnit.py

@@ -120,7 +120,7 @@ class UseClause(TreesitterNodeMixin, VHDLModel_UseClause):  # noqa: D101
                 symbols.append(
                     PackageReferenceSymbol(selected_or_simple_name(selected_name)),
                 )
-            ret.append(cls(symbols, _treesitter_node=selected_name_node))
+            ret.append(cls(symbols, _treesitter_node=use_clause_node))
         return ret
 
     def __eq__(self, other: object) -> bool:  # noqa: D105

{pyvhdlmodeltreesitter-0.5.0 → pyvhdlmodeltreesitter-0.5.2}/src/pyVHDLModelTreesitter/_Document.py

@@ -21,7 +21,23 @@ from pyVHDLModelTreesitter.treesitter.query import PARSER, DesignUnits
 
 class Document(VHDLModel_Document):
     @classmethod
-    def from_file(cls, path: str | Path) -> Self:  # noqa: C901, PLR0912  # TODO: refactor
+    def from_file(cls, path: str | Path) -> Self:
+        """
+        Create a Document, and all ModelEntities it contains.
+
+        Nodes that are not recognised issue a `NotImplementedWarning`.
+        """
+        if isinstance(path, str):
+            path = Path(path)
+        path = path.resolve()
+        return cls.from_text(path.read_bytes(), path)
+
+    @classmethod
+    def from_text(  # noqa: C901, PLR0912  # TODO: refactor
+        cls,
+        text: str | bytes,
+        path: str | Path,
+    ) -> Self:
         """
         Create a Document, and all ModelEntities it contains.
 
@@ -34,13 +50,16 @@ class Document(VHDLModel_Document):
             - Any `design_unit` node has no children.
 
         """
+        if isinstance(text, str):
+            text = text.encode()
         if isinstance(path, str):
             path = Path(path)
         path = path.resolve()
         document = cls(path)
 
-        tree = PARSER.parse(path.read_bytes())
+        tree = PARSER.parse(text)
         node = tree.root_node
+
         captures = DesignUnits.capture(node)
         design_unit_captures = captures.get("design_unit")
         if design_unit_captures is None:
@@ -52,9 +71,6 @@ class Document(VHDLModel_Document):
             context_children = design_unit_capture.children[:-1]
             context_items: list[LibraryClause | UseClause] = []
             for context_child in context_children:
-                if context_child is None:
-                    # TODO: error type is wrong: should be "discovered child is empty"
-                    raise NodeMissingChildError(node, "design_unit")
                 if context_child.type == "library_clause":
                     context_items.extend(
                         LibraryClause.from_treesitter_node(context_child),
@@ -65,8 +81,6 @@ class Document(VHDLModel_Document):
                     )
                 else:
                     NotImplementedWarning.warn_child_type(context_child)
-            if design_unit_child is None:
-                raise NodeMissingChildError(node, "design_unit")
             if design_unit_child.type == "architecture_definition":
                 architecture = Architecture.from_treesitter_node(
                     node,

pyvhdlmodeltreesitter-0.5.2/src/pyVHDLModelTreesitter/format.py

@@ -0,0 +1,68 @@
+"""
+Submodule that provides useful utilities for performing nice looking outputs.
+
+WARNING: This submodule is a filthy hack. When called, `patch_module`
+monkeypatches a generic `__rich_repr__` method onto every class in a given
+module within `pyVHDLModel`.
+
+This avoids having to write a `__rich_repr__` for every class. This is not a
+good solution, but it was quick and works for what I care about.
+"""
+
+from __future__ import annotations
+
+import importlib
+import inspect
+import pkgutil
+from typing import TYPE_CHECKING
+
+if TYPE_CHECKING:
+    from types import ModuleType
+
+if TYPE_CHECKING:
+    from rich.repr import Result as RichReprResult
+
+import pyVHDLModelTreesitter
+
+
+def __rich_repr__(obj: object) -> RichReprResult:  # noqa: N807
+    """
+    Return a rich compatible repr for an arbitrary object.
+
+    WARNING: `obj` must define `__allSlots__` or `__dict__`.
+    """  # noqa: DOC402
+    for attr in (
+        getattr(obj, "__allSlots__", [])
+        if hasattr(obj, "__allSlots__")
+        else obj.__dict__
+    ):
+        if attr in {
+            "_documents",  # this duplicates data in the `_libraries` field
+            "_namespace",  # this isn't printed
+            "_parent",  # this duplicates the parent
+            "_treesitter_node",  # this doesn't provide useful info
+        } or attr.endswith(("Graph", "Vertex")):  # these are from the dependency graph
+            continue
+        yield attr, getattr(obj, attr)
+
+
+def patch_module(
+    *,
+    module: ModuleType = pyVHDLModelTreesitter,
+    top: bool = True,
+) -> None:
+    """Inject a `__rich_repr__` into every class defined in a given module."""
+    # Inject into all classes defined in this module
+    for _, obj in inspect.getmembers(module):
+        if (
+            inspect.isclass(obj)
+            and obj.__module__ == module.__name__
+            and not hasattr(obj, "__rich_repr__")
+        ):
+            obj.__rich_repr__ = __rich_repr__
+    # Inject into all submodules of this module
+    if top and hasattr(module, "__path__"):
+        for _, name, _ in pkgutil.walk_packages(pyVHDLModelTreesitter.__path__):
+            full_name = f"{pyVHDLModelTreesitter.__name__}.{name}"
+            submodule = importlib.import_module(full_name)
+            patch_module(module=submodule, top=False)

pyvhdlmodeltreesitter-0.5.2/src/pyVHDLModelTreesitter/treesitter/queries/concurrent_simple_signal_assignment.scm

@@ -0,0 +1,5 @@
+(concurrent_simple_signal_assignment
+  (name) @lhs
+  (signal_assignment)
+  (waveform) @rhs
+) @signal