pyVHDLModel 0.31.2__tar.gz → 0.32.0__tar.gz
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/PKG-INFO +35 -36
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/Expression.py +72 -1
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/__init__.py +1 -1
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel.egg-info/PKG-INFO +35 -36
- pyvhdlmodel-0.32.0/pyVHDLModel.egg-info/requires.txt +42 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyproject.toml +19 -4
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/setup.py +20 -16
- pyvhdlmodel-0.31.2/pyVHDLModel.egg-info/requires.txt +0 -42
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/LICENSE.md +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/README.md +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/Association.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/Base.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/Common.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/Concurrent.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/Declaration.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/DesignUnit.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/Exception.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/IEEE.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/Instantiation.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/Interface.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/Name.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/Namespace.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/Object.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/PSLModel.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/Predefined.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/Regions.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/STD.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/Sequential.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/Subprogram.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/Symbol.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/Type.py +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel/py.typed +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel.egg-info/SOURCES.txt +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel.egg-info/dependency_links.txt +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/pyVHDLModel.egg-info/top_level.txt +0 -0
- {pyvhdlmodel-0.31.2 → pyvhdlmodel-0.32.0}/setup.cfg +0 -0
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Metadata-Version: 2.4
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Name: pyVHDLModel
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Version: 0.
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Version: 0.32.0
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Summary: An abstract VHDL language model.
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Home-page: https://GitHub.com/VHDL/pyVHDLModel
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Author: Patrick Lehmann
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All declarations for literals, aggregates, operators forming an expressions.
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"""
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from
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from typing import Tuple, List, Iterable, Union, ClassVar
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from pyTooling.Decorators import export, readonly
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@export
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class BitStringBase(Flag):
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NoBase = 0
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Binary = 2
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Octal = 8
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Decimal = 10
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Hexadecimal = 16
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Unsigned = 32
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@readonly
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def Bits(self) -> int:
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@readonly
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@export
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Summary: An abstract VHDL language model.
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**DescribePythonPackageHostedOnGitHub(
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packageName=packageName,
|
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description="An abstract VHDL language model.",
|
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gitHubNamespace=gitHubNamespace,
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keywords="Python3 VHDL Language Model Abstract",
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sourceFileWithVersion=packageInformationFile,
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classifiers=list(DEFAULT_CLASSIFIERS) + [
|
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"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
|
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"Topic :: Software Development :: Code Generators",
|
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|
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],
|
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developmentStatus="beta",
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pythonVersions=("3.11", "3.12", "3.13", "3.14"),
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packageName: ["py.typed"]
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