pyEDAA.ProjectModel 0.6.4__tar.gz → 0.7.0__tar.gz
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/PKG-INFO +42 -40
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/Altera/Quartus.py +2 -1
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/Altera/__init__.py +2 -1
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/Attributes.py +2 -1
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/GHDL.py +2 -1
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/Intel/QuartusPrime.py +2 -1
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/Intel/__init__.py +2 -1
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/MentorGraphics/ModelSim.py +2 -1
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/MentorGraphics/QuestaSim.py +2 -1
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/MentorGraphics/__init__.py +2 -1
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/OSVVM.py +2 -1
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/Verilog.py +2 -1
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/Xilinx/ISE.py +2 -1
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/Xilinx/Vivado.py +8 -9
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/Xilinx/__init__.py +2 -1
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/__init__.py +16 -19
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA.ProjectModel.egg-info/PKG-INFO +42 -40
- pyedaa_projectmodel-0.7.0/pyEDAA.ProjectModel.egg-info/requires.txt +58 -0
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyproject.toml +4 -3
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/setup.py +4 -3
- pyedaa_projectmodel-0.6.4/pyEDAA.ProjectModel.egg-info/requires.txt +0 -56
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/LICENSE.md +0 -0
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/README.md +0 -0
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/VHDL.py +0 -0
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/py.typed +0 -0
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA.ProjectModel.egg-info/SOURCES.txt +0 -0
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA.ProjectModel.egg-info/dependency_links.txt +0 -0
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA.ProjectModel.egg-info/top_level.txt +0 -0
- {pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/setup.cfg +0 -0
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Metadata-Version: 2.4
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Name: pyEDAA.ProjectModel
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Version: 0.
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Version: 0.7.0
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Summary: An abstract model of EDA tool projects.
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Home-page: https://GitHub.com/edaa-org/pyEDAA.ProjectModel
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Author: Patrick Lehmann
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Classifier: Intended Audience :: Developers
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Classifier: Topic :: Utilities
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Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
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Classifier: License :: OSI Approved :: Apache Software License
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Classifier: Programming Language :: Python :: 3 :: Only
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Classifier: Development Status :: 4 - Beta
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Description-Content-Type: text/markdown
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License-File: LICENSE.md
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{pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/Altera/Quartus.py
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# #
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# License: #
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# ==================================================================================================================== #
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# Copyright 2017-2020 Patrick Lehmann - Boetzingen, Germany #
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# you may not use this file except in compliance with the License. #
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# License: #
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# ==================================================================================================================== #
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# Copyright
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# Copyright 2021-2026 Electronic Design Automation Abstraction (EDA²) #
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# Copyright 2017-2020 Patrick Lehmann - Boetzingen, Germany #
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# #
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# Licensed under the Apache License, Version 2.0 (the "License"); #
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# you may not use this file except in compliance with the License. #
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{pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/Xilinx/Vivado.py
RENAMED
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@@ -11,7 +11,8 @@
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# #
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# License: #
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# ==================================================================================================================== #
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# Copyright
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# Copyright 2021-2026 Electronic Design Automation Abstraction (EDA²) #
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# #
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# you may not use this file except in compliance with the License. #
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# ==================================================================================================================== #
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#
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"""Specific file types and attributes for Xilinx Vivado."""
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from pathlib
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from xml.dom
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from pathlib import Path
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from xml.dom import minidom, Node
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from pyTooling.Decorators import export
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from pyVHDLModel import VHDLVersion
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from pyEDAA.ProjectModel
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from pyEDAA.ProjectModel import VerilogSourceFile as Model_VerilogSourceFile
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from pyEDAA.ProjectModel import VHDLSourceFile as Model_VHDLSourceFile
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from pyEDAA.ProjectModel import ProjectFile, XMLFile, XMLContent, SDCContent, Project, FileSet, Attribute, Design, \
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File as Model_File, ConstraintFile as Model_ConstraintFile, \
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VerilogSourceFile as Model_VerilogSourceFile, VHDLSourceFile as Model_VHDLSourceFile
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@export
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{pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA/ProjectModel/Xilinx/__init__.py
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# #
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# ==================================================================================================================== #
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# Copyright
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# Copyright 2021-2026 Electronic Design Automation Abstraction (EDA²) #
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# Copyright 2017-2020 Patrick Lehmann - Boetzingen, Germany #
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@@ -11,8 +11,9 @@
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# #
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# License: #
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# ==================================================================================================================== #
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# Copyright
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# Copyright
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# Copyright 2021-2026 Electronic Design Automation Abstraction (EDA²) #
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# Copyright 2017-2020 Patrick Lehmann - Boetzingen, Germany #
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# Copyright 2014-2016 Technische Universitaet Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture #
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# Licensed under the Apache License, Version 2.0 (the "License"); #
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# you may not use this file except in compliance with the License. #
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@@ -32,18 +33,18 @@
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"""An abstract model of EDA tool projects."""
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__author__ = "Patrick Lehmann"
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__email__ = "Paebbels@gmail.com"
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__copyright__ = "
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__copyright__ = "2021-2026, Electronic Design Automation Abstraction (EDA²)"
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__license__ = "Apache License, Version 2.0"
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__version__ = "0.
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__version__ = "0.7.0"
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__keywords__ = ["eda project", "model", "abstract", "xilinx", "vivado", "osvvm", "file set", "file group", "test bench", "test harness"]
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__project_url__ = "https://github.com/edaa-org/pyEDAA.ProjectModel"
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__documentation_url__ = "https://edaa-org.github.io/pyEDAA.ProjectModel"
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__issue_tracker_url__ = "https://GitHub.com/edaa-org/pyEDAA.ProjectModel/issues"
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from os.path
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from pathlib
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from
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from pathlib import Path as pathlib_Path
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from typing import Dict, Union, Optional as Nullable, List, Iterable, Generator, Tuple, \
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Any as typing_Any, Type, Set, Self
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from pyTooling.Common import getFullyQualifiedName
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@@ -434,16 +435,15 @@ class VHDLSourceFile(HDLSourceFile, HumanReadableContent):
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except KeyError as ex:
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raise Exception(f"VHDL library '{vhdlLibrary}' not found in default design '{project.DefaultDesign.Name}'.") from ex
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else:
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-
raise Exception(
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+
raise Exception("Can't lookup VHDL library because neither 'project' nor 'design' is given as a parameter.")
|
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|
elif isinstance(vhdlLibrary, VHDLLibrary):
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self._vhdlLibrary = vhdlLibrary
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vhdlLibrary.AddFile(self)
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elif vhdlLibrary is None:
|
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else:
|
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-
ex = TypeError(
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-
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|
-
ex.add_note(f"Got type '{getFullyQualifiedName(vhdlLibrary)}'.")
|
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|
+
ex = TypeError("Parameter 'vhdlLibrary' is neither a 'str' nor 'VHDLibrary'.")
|
|
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+
ex.add_note(f"Got type '{getFullyQualifiedName(vhdlLibrary)}'.")
|
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raise ex
|
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self._vhdlVersion = vhdlVersion
|
|
@@ -919,13 +919,11 @@ class FileSet(metaclass=ExtendedType, slots=True):
|
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919
919
|
raise TypeError("Parameter 'file' is not of type ProjectModel.File.")
|
|
920
920
|
elif file._fileSet is not None:
|
|
921
921
|
ex = ValueError(f"File '{file.Path!s}' is already part of fileset '{file.FileSet.Name}'.")
|
|
922
|
-
|
|
923
|
-
ex.add_note(f"A file can't be assigned to another fileset.")
|
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922
|
+
ex.add_note("A file can't be assigned to another fileset.")
|
|
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|
raise ex
|
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elif file in self._set:
|
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926
925
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ex = ValueError(f"File '{file.Path!s}' is already part of this fileset.")
|
|
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|
-
|
|
928
|
-
ex.add_note(f"A file can't be added twice to a fileset.")
|
|
926
|
+
ex.add_note("A file can't be added twice to a fileset.")
|
|
929
927
|
raise ex
|
|
930
928
|
|
|
931
929
|
self._files.append(file)
|
|
@@ -1258,9 +1256,8 @@ class VHDLLibrary(metaclass=ExtendedType, slots=True):
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|
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|
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|
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|
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|
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|
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|
-
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|
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+
ex = TypeError("Parameter 'vhdlFile' is not a 'VHDLSourceFile'.")
|
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|
+
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|
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|
|
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|
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self._files.append(vhdlFile)
|
{pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA.ProjectModel.egg-info/PKG-INFO
RENAMED
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1
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Metadata-Version: 2.4
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Name: pyEDAA.ProjectModel
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Version: 0.
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+
Version: 0.7.0
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Summary: An abstract model of EDA tool projects.
|
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Home-page: https://GitHub.com/edaa-org/pyEDAA.ProjectModel
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Author: Patrick Lehmann
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@@ -14,68 +14,70 @@ Classifier: Operating System :: OS Independent
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Classifier: Intended Audience :: Developers
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Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
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Classifier: License :: OSI Approved :: Apache Software License
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Requires-Dist: pytest-xdist~=3.8; extra == "test"
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Dynamic: author
|
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80
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|
Dynamic: author-email
|
|
81
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|
Dynamic: classifier
|
|
@@ -0,0 +1,58 @@
|
|
|
1
|
+
pySystemRDLModel~=0.4.0
|
|
2
|
+
pyVHDLModel~=0.40.0
|
|
3
|
+
pyTooling<11.0,>=10.1.1
|
|
4
|
+
pySVModel~=0.6.0
|
|
5
|
+
|
|
6
|
+
[all]
|
|
7
|
+
docutils_stubs~=0.0.22
|
|
8
|
+
pyVHDLModel~=0.40.0
|
|
9
|
+
typing_extensions~=4.16
|
|
10
|
+
sphinx_rtd_theme~=3.1
|
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11
|
+
Coverage~=7.17
|
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12
|
+
pyTooling.Sphinx[reports]~=1.0
|
|
13
|
+
sphinx~=9.2
|
|
14
|
+
pySVModel~=0.6.0
|
|
15
|
+
pySystemRDLModel~=0.4.0
|
|
16
|
+
pytest~=9.1
|
|
17
|
+
mypy[reports]~=2.4
|
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18
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+
sphinxcontrib-mermaid~=2.1
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19
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+
autoapi>=2.0.1
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20
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+
pytest-xdist~=3.8
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21
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pyEDAA.OSVVM~=0.6
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22
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+
sphinx_autodoc_typehints~=3.17
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23
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pyTooling<11.0,>=10.1.1
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sphinx_design~=0.7.0
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sphinx-copybutton>=0.5.2
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pytest-cov~=7.1
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lxml<7.0,>=6.1.3
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[doc]
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pyTooling.Sphinx[reports]~=1.0
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31
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docutils_stubs~=0.0.22
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32
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pyVHDLModel~=0.40.0
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33
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sphinx~=9.2
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34
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sphinx_design~=0.7.0
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35
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pySVModel~=0.6.0
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36
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pySystemRDLModel~=0.4.0
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sphinx-copybutton>=0.5.2
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sphinx_rtd_theme~=3.1
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sphinxcontrib-mermaid~=2.1
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40
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autoapi>=2.0.1
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sphinx_autodoc_typehints~=3.17
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pyTooling<11.0,>=10.1.1
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43
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+
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44
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+
[osvvm]
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45
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+
pyEDAA.OSVVM~=0.6
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46
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+
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47
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+
[test]
|
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48
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+
pyVHDLModel~=0.40.0
|
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49
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+
typing_extensions~=4.16
|
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50
|
+
pySVModel~=0.6.0
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51
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+
pySystemRDLModel~=0.4.0
|
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52
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+
pytest~=9.1
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53
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+
mypy[reports]~=2.4
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54
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+
pytest-cov~=7.1
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55
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+
lxml<7.0,>=6.1.3
|
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56
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+
Coverage~=7.17
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57
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+
pytest-xdist~=3.8
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58
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+
pyTooling<11.0,>=10.1.1
|
|
@@ -1,7 +1,7 @@
|
|
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1
1
|
[build-system]
|
|
2
2
|
requires = [
|
|
3
|
-
"setuptools >=
|
|
4
|
-
"pyTooling
|
|
3
|
+
"setuptools >= 84.2.1",
|
|
4
|
+
"pyTooling >= 10.1.1, < 11.0"
|
|
5
5
|
]
|
|
6
6
|
build-backend = "setuptools.build_meta"
|
|
7
7
|
|
|
@@ -25,7 +25,7 @@ variable-naming-style = "camelCase"
|
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25
25
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|
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26
26
|
[tool.mypy]
|
|
27
27
|
packages = ["pyEDAA.ProjectModel"]
|
|
28
|
-
python_version = "3.
|
|
28
|
+
python_version = "3.15"
|
|
29
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|
#ignore_missing_imports = true
|
|
30
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strict = true
|
|
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pretty = true
|
|
@@ -66,6 +66,7 @@ ignore-setters = true
|
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66
66
|
[tool.coverage.run]
|
|
67
67
|
branch = true
|
|
68
68
|
relative_files = true
|
|
69
|
+
patch = ["subprocess"]
|
|
69
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|
omit = [
|
|
70
71
|
"*site-packages*",
|
|
71
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|
"setup.py",
|
|
@@ -11,8 +11,9 @@
|
|
|
11
11
|
# #
|
|
12
12
|
# License: #
|
|
13
13
|
# ==================================================================================================================== #
|
|
14
|
-
# Copyright
|
|
15
|
-
# Copyright
|
|
14
|
+
# Copyright 2021-2026 Electronic Design Automation Abstraction (EDA²) #
|
|
15
|
+
# Copyright 2017-2020 Patrick Lehmann - Boetzingen, Germany #
|
|
16
|
+
# Copyright 2014-2016 Technische Universitaet Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture #
|
|
16
17
|
# #
|
|
17
18
|
# Licensed under the Apache License, Version 2.0 (the "License"); #
|
|
18
19
|
# you may not use this file except in compliance with the License. #
|
|
@@ -53,7 +54,7 @@ setup(
|
|
|
53
54
|
"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)"
|
|
54
55
|
],
|
|
55
56
|
developmentStatus="beta",
|
|
56
|
-
pythonVersions=("3.11", "3.12", "3.13", "3.14"),
|
|
57
|
+
pythonVersions=("3.11", "3.12", "3.13", "3.14", "3.15"),
|
|
57
58
|
dataFiles={
|
|
58
59
|
packageName: ["py.typed"]
|
|
59
60
|
}
|
|
@@ -1,56 +0,0 @@
|
|
|
1
|
-
pySVModel~=0.5.11
|
|
2
|
-
pyVHDLModel~=0.37.0
|
|
3
|
-
pySystemRDLModel~=0.3.10
|
|
4
|
-
pyTooling~=8.15
|
|
5
|
-
|
|
6
|
-
[all]
|
|
7
|
-
pyEDAA.OSVVM~=0.6
|
|
8
|
-
pyVHDLModel~=0.37.0
|
|
9
|
-
pytest-cov~=7.1
|
|
10
|
-
sphinx_rtd_theme~=3.1
|
|
11
|
-
sphinx_autodoc_typehints~=3.12
|
|
12
|
-
pySVModel~=0.5.11
|
|
13
|
-
docutils_stubs~=0.0.22
|
|
14
|
-
sphinx_reports~=0.11.0
|
|
15
|
-
lxml<7.0,>=6.1
|
|
16
|
-
mypy[reports]~=2.1
|
|
17
|
-
typing_extensions~=4.16
|
|
18
|
-
Coverage~=7.15
|
|
19
|
-
sphinx~=9.1
|
|
20
|
-
sphinx_design~=0.7.0
|
|
21
|
-
sphinxcontrib-mermaid~=2.0
|
|
22
|
-
pyTooling~=8.15
|
|
23
|
-
autoapi>=2.0.1
|
|
24
|
-
pytest~=9.1
|
|
25
|
-
pySystemRDLModel~=0.3.10
|
|
26
|
-
sphinx-copybutton>=0.5.2
|
|
27
|
-
|
|
28
|
-
[doc]
|
|
29
|
-
pyVHDLModel~=0.37.0
|
|
30
|
-
autoapi>=2.0.1
|
|
31
|
-
sphinx_autodoc_typehints~=3.12
|
|
32
|
-
pySVModel~=0.5.11
|
|
33
|
-
docutils_stubs~=0.0.22
|
|
34
|
-
sphinx_reports~=0.11.0
|
|
35
|
-
sphinxcontrib-mermaid~=2.0
|
|
36
|
-
pySystemRDLModel~=0.3.10
|
|
37
|
-
sphinx~=9.1
|
|
38
|
-
sphinx_design~=0.7.0
|
|
39
|
-
sphinx_rtd_theme~=3.1
|
|
40
|
-
sphinx-copybutton>=0.5.2
|
|
41
|
-
pyTooling~=8.15
|
|
42
|
-
|
|
43
|
-
[osvvm]
|
|
44
|
-
pyEDAA.OSVVM~=0.6
|
|
45
|
-
|
|
46
|
-
[test]
|
|
47
|
-
mypy[reports]~=2.1
|
|
48
|
-
pyVHDLModel~=0.37.0
|
|
49
|
-
typing_extensions~=4.16
|
|
50
|
-
pytest-cov~=7.1
|
|
51
|
-
pySVModel~=0.5.11
|
|
52
|
-
Coverage~=7.15
|
|
53
|
-
pytest~=9.1
|
|
54
|
-
pySystemRDLModel~=0.3.10
|
|
55
|
-
lxml<7.0,>=6.1
|
|
56
|
-
pyTooling~=8.15
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
{pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA.ProjectModel.egg-info/SOURCES.txt
RENAMED
|
File without changes
|
|
File without changes
|
{pyedaa_projectmodel-0.6.4 → pyedaa_projectmodel-0.7.0}/pyEDAA.ProjectModel.egg-info/top_level.txt
RENAMED
|
File without changes
|
|
File without changes
|