pyEDAA.ProjectModel 0.6.0__tar.gz → 0.6.2__tar.gz

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (29) hide show
  1. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/PKG-INFO +43 -43
  2. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/Altera/Quartus.py +1 -1
  3. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/Altera/__init__.py +1 -1
  4. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/Attributes.py +1 -1
  5. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/GHDL.py +1 -1
  6. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/Intel/QuartusPrime.py +1 -1
  7. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/Intel/__init__.py +1 -1
  8. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/MentorGraphics/ModelSim.py +1 -1
  9. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/MentorGraphics/QuestaSim.py +1 -1
  10. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/MentorGraphics/__init__.py +1 -1
  11. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/OSVVM.py +2 -2
  12. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/Verilog.py +1 -1
  13. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/Xilinx/ISE.py +1 -1
  14. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/Xilinx/Vivado.py +1 -1
  15. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/Xilinx/__init__.py +1 -1
  16. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/__init__.py +24 -21
  17. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA.ProjectModel.egg-info/PKG-INFO +43 -43
  18. pyedaa_projectmodel-0.6.2/pyEDAA.ProjectModel.egg-info/requires.txt +58 -0
  19. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyproject.toml +9 -11
  20. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/setup.py +1 -1
  21. pyedaa_projectmodel-0.6.0/pyEDAA.ProjectModel.egg-info/requires.txt +0 -58
  22. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/LICENSE.md +0 -0
  23. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/README.md +0 -0
  24. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/VHDL.py +0 -0
  25. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/py.typed +0 -0
  26. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA.ProjectModel.egg-info/SOURCES.txt +0 -0
  27. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA.ProjectModel.egg-info/dependency_links.txt +0 -0
  28. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA.ProjectModel.egg-info/top_level.txt +0 -0
  29. {pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/setup.cfg +0 -0
{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/PKG-INFO RENAMED
@@ -1,6 +1,6 @@
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  Metadata-Version: 2.4
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  Name: pyEDAA.ProjectModel
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- Version: 0.6.0
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+ Version: 0.6.2
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  Summary: An abstract model of EDA tool projects.
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  Home-page: https://GitHub.com/edaa-org/pyEDAA.ProjectModel
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  Author: Patrick Lehmann
@@ -24,60 +24,60 @@ Classifier: Development Status :: 4 - Beta
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  Requires-Python: >=3.11
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  Description-Content-Type: text/markdown
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  License-File: LICENSE.md
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- Requires-Dist: pyVHDLModel~=0.31
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- Requires-Dist: pySVModel~=0.5
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- Requires-Dist: pySystemRDLModel~=0.3
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- Requires-Dist: pyTooling~=8.7
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+ Requires-Dist: pySystemRDLModel~=0.3.0
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+ Requires-Dist: pyTooling~=8.11
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+ Requires-Dist: pySVModel~=0.5.0
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+ Requires-Dist: pyVHDLModel~=0.33.0
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  Provides-Extra: doc
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- Requires-Dist: pySVModel~=0.5; extra == "doc"
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- Requires-Dist: pySystemRDLModel~=0.3; extra == "doc"
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- Requires-Dist: docutils~=0.21; extra == "doc"
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- Requires-Dist: sphinx_design~=0.6; extra == "doc"
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- Requires-Dist: pyVHDLModel~=0.31; extra == "doc"
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- Requires-Dist: sphinx-copybutton>=0.5; extra == "doc"
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- Requires-Dist: sphinxcontrib-mermaid~=1.0; extra == "doc"
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+ Requires-Dist: docutils~=0.22.0; extra == "doc"
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+ Requires-Dist: pyTooling~=8.11; extra == "doc"
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+ Requires-Dist: pySystemRDLModel~=0.3.0; extra == "doc"
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+ Requires-Dist: sphinx-copybutton>=0.5.0; extra == "doc"
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  Requires-Dist: docutils_stubs~=0.0.22; extra == "doc"
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- Requires-Dist: sphinx~=8.2; extra == "doc"
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- Requires-Dist: sphinx_autodoc_typehints~=3.5; extra == "doc"
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- Requires-Dist: sphinx_reports~=0.9; extra == "doc"
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- Requires-Dist: pyTooling~=8.7; extra == "doc"
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- Requires-Dist: sphinx_rtd_theme~=3.0; extra == "doc"
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+ Requires-Dist: sphinx_autodoc_typehints~=3.6; extra == "doc"
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+ Requires-Dist: sphinxcontrib-mermaid~=2.0; extra == "doc"
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+ Requires-Dist: pySVModel~=0.5.0; extra == "doc"
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  Requires-Dist: autoapi>=2.0.1; extra == "doc"
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+ Requires-Dist: pyVHDLModel~=0.33.0; extra == "doc"
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+ Requires-Dist: sphinx_reports~=0.10.0; extra == "doc"
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+ Requires-Dist: sphinx~=9.1; extra == "doc"
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+ Requires-Dist: sphinx_rtd_theme~=3.1; extra == "doc"
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+ Requires-Dist: sphinx_design~=0.7.0; extra == "doc"
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  Provides-Extra: test
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- Requires-Dist: mypy[reports]~=1.18; extra == "test"
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- Requires-Dist: pySVModel~=0.5; extra == "test"
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- Requires-Dist: pySystemRDLModel~=0.3; extra == "test"
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+ Requires-Dist: mypy[reports]~=1.19; extra == "test"
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+ Requires-Dist: pyTooling~=8.11; extra == "test"
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+ Requires-Dist: Coverage~=7.13; extra == "test"
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+ Requires-Dist: pySystemRDLModel~=0.3.0; extra == "test"
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+ Requires-Dist: pytest-cov~=7.0; extra == "test"
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+ Requires-Dist: pySVModel~=0.5.0; extra == "test"
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  Requires-Dist: lxml<7.0,>=5.4; extra == "test"
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- Requires-Dist: Coverage~=7.11; extra == "test"
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- Requires-Dist: pyVHDLModel~=0.31; extra == "test"
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- Requires-Dist: pyTooling~=8.7; extra == "test"
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- Requires-Dist: pytest~=8.4; extra == "test"
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+ Requires-Dist: pyVHDLModel~=0.33.0; extra == "test"
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+ Requires-Dist: pytest~=9.0; extra == "test"
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  Requires-Dist: typing_extensions~=4.15; extra == "test"
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- Requires-Dist: pytest-cov~=7.0; extra == "test"
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  Provides-Extra: osvvm
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  Requires-Dist: pyEDAA.OSVVM~=0.6; extra == "osvvm"
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  Provides-Extra: all
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- Requires-Dist: pySystemRDLModel~=0.3; extra == "all"
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- Requires-Dist: sphinx_design~=0.6; extra == "all"
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- Requires-Dist: sphinx-copybutton>=0.5; extra == "all"
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  Requires-Dist: docutils_stubs~=0.0.22; extra == "all"
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- Requires-Dist: lxml<7.0,>=5.4; extra == "all"
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- Requires-Dist: sphinx_autodoc_typehints~=3.5; extra == "all"
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- Requires-Dist: sphinxcontrib-mermaid~=1.0; extra == "all"
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- Requires-Dist: sphinx~=8.2; extra == "all"
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- Requires-Dist: pyEDAA.OSVVM~=0.6; extra == "all"
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- Requires-Dist: pyTooling~=8.7; extra == "all"
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- Requires-Dist: sphinx_rtd_theme~=3.0; extra == "all"
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- Requires-Dist: mypy[reports]~=1.18; extra == "all"
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- Requires-Dist: pySVModel~=0.5; extra == "all"
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- Requires-Dist: docutils~=0.21; extra == "all"
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- Requires-Dist: Coverage~=7.11; extra == "all"
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- Requires-Dist: pyVHDLModel~=0.31; extra == "all"
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+ Requires-Dist: sphinx_autodoc_typehints~=3.6; extra == "all"
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+ Requires-Dist: pySVModel~=0.5.0; extra == "all"
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+ Requires-Dist: sphinx_design~=0.7.0; extra == "all"
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+ Requires-Dist: pySystemRDLModel~=0.3.0; extra == "all"
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+ Requires-Dist: pyVHDLModel~=0.33.0; extra == "all"
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+ Requires-Dist: docutils~=0.22.0; extra == "all"
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+ Requires-Dist: sphinx-copybutton>=0.5.0; extra == "all"
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  Requires-Dist: pytest-cov~=7.0; extra == "all"
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- Requires-Dist: typing_extensions~=4.15; extra == "all"
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- Requires-Dist: sphinx_reports~=0.9; extra == "all"
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- Requires-Dist: pytest~=8.4; extra == "all"
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+ Requires-Dist: sphinxcontrib-mermaid~=2.0; extra == "all"
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  Requires-Dist: autoapi>=2.0.1; extra == "all"
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+ Requires-Dist: mypy[reports]~=1.19; extra == "all"
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+ Requires-Dist: sphinx~=9.1; extra == "all"
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+ Requires-Dist: sphinx_rtd_theme~=3.1; extra == "all"
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+ Requires-Dist: typing_extensions~=4.15; extra == "all"
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+ Requires-Dist: pyTooling~=8.11; extra == "all"
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+ Requires-Dist: pyEDAA.OSVVM~=0.6; extra == "all"
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+ Requires-Dist: Coverage~=7.13; extra == "all"
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+ Requires-Dist: lxml<7.0,>=5.4; extra == "all"
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+ Requires-Dist: sphinx_reports~=0.10.0; extra == "all"
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+ Requires-Dist: pytest~=9.0; extra == "all"
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  Dynamic: author
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  Dynamic: author-email
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  Dynamic: classifier
{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/Altera/Quartus.py RENAMED
@@ -11,7 +11,7 @@
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  # #
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  # License: #
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  # ==================================================================================================================== #
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- # Copyright 2017-2025 Patrick Lehmann - Boetzingen, Germany #
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+ # Copyright 2017-2026 Patrick Lehmann - Boetzingen, Germany #
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  # #
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  # Licensed under the Apache License, Version 2.0 (the "License"); #
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  # you may not use this file except in compliance with the License. #
{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/Altera/__init__.py RENAMED
@@ -11,7 +11,7 @@
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  # #
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  # License: #
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  # ==================================================================================================================== #
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- # Copyright 2017-2025 Patrick Lehmann - Boetzingen, Germany #
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+ # Copyright 2017-2026 Patrick Lehmann - Boetzingen, Germany #
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  # #
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  # Licensed under the Apache License, Version 2.0 (the "License"); #
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  # you may not use this file except in compliance with the License. #
{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/Attributes.py RENAMED
@@ -11,7 +11,7 @@
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  # #
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  # License: #
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  # ==================================================================================================================== #
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- # Copyright 2017-2025 Patrick Lehmann - Boetzingen, Germany #
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+ # Copyright 2017-2026 Patrick Lehmann - Boetzingen, Germany #
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  # #
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  # Licensed under the Apache License, Version 2.0 (the "License"); #
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  # you may not use this file except in compliance with the License. #
{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/GHDL.py RENAMED
@@ -11,7 +11,7 @@
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  # #
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  # License: #
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  # ==================================================================================================================== #
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- # Copyright 2017-2025 Patrick Lehmann - Boetzingen, Germany #
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+ # Copyright 2017-2026 Patrick Lehmann - Boetzingen, Germany #
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  # #
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  # Licensed under the Apache License, Version 2.0 (the "License"); #
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  # you may not use this file except in compliance with the License. #
{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/Intel/QuartusPrime.py RENAMED
@@ -11,7 +11,7 @@
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  # #
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  # License: #
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  # ==================================================================================================================== #
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- # Copyright 2017-2025 Patrick Lehmann - Boetzingen, Germany #
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+ # Copyright 2017-2026 Patrick Lehmann - Boetzingen, Germany #
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  # #
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  # Licensed under the Apache License, Version 2.0 (the "License"); #
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  # you may not use this file except in compliance with the License. #
{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/Intel/__init__.py RENAMED
@@ -11,7 +11,7 @@
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  # #
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  # License: #
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  # ==================================================================================================================== #
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- # Copyright 2017-2025 Patrick Lehmann - Boetzingen, Germany #
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+ # Copyright 2017-2026 Patrick Lehmann - Boetzingen, Germany #
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  # #
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  # Licensed under the Apache License, Version 2.0 (the "License"); #
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  # you may not use this file except in compliance with the License. #
{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/MentorGraphics/ModelSim.py RENAMED
@@ -11,7 +11,7 @@
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  # #
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  # License: #
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  # ==================================================================================================================== #
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- # Copyright 2017-2025 Patrick Lehmann - Boetzingen, Germany #
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+ # Copyright 2017-2026 Patrick Lehmann - Boetzingen, Germany #
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  # #
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  # Licensed under the Apache License, Version 2.0 (the "License"); #
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  # you may not use this file except in compliance with the License. #
{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/MentorGraphics/QuestaSim.py RENAMED
@@ -11,7 +11,7 @@
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  # #
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  # License: #
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  # ==================================================================================================================== #
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- # Copyright 2017-2025 Patrick Lehmann - Boetzingen, Germany #
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+ # Copyright 2017-2026 Patrick Lehmann - Boetzingen, Germany #
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  # #
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  # Licensed under the Apache License, Version 2.0 (the "License"); #
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  # you may not use this file except in compliance with the License. #
{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/MentorGraphics/__init__.py RENAMED
@@ -11,7 +11,7 @@
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  # #
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  # License: #
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  # ==================================================================================================================== #
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- # Copyright 2017-2025 Patrick Lehmann - Boetzingen, Germany #
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+ # Copyright 2017-2026 Patrick Lehmann - Boetzingen, Germany #
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  # #
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  # Licensed under the Apache License, Version 2.0 (the "License"); #
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  # you may not use this file except in compliance with the License. #
{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/OSVVM.py RENAMED
@@ -11,7 +11,7 @@
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  # #
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  # License: #
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  # ==================================================================================================================== #
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- # Copyright 2017-2025 Patrick Lehmann - Boetzingen, Germany #
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+ # Copyright 2017-2026 Patrick Lehmann - Boetzingen, Germany #
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  # #
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  # Licensed under the Apache License, Version 2.0 (the "License"); #
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  # you may not use this file except in compliance with the License. #
@@ -49,7 +49,7 @@ class OSVVMProjectFile(ProjectFile, TCLContent):
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  project: Nullable[Project] = None,
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  design: Nullable[Design] = None,
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  fileSet: Nullable[FileSet] = None
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- ):
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+ ) -> None:
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  super().__init__(path, project, design, fileSet)
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  self._osvvmProject = None
{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/Verilog.py RENAMED
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  # #
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  # ==================================================================================================================== #
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- # Copyright 2017-2025 Patrick Lehmann - Boetzingen, Germany #
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+ # Copyright 2017-2026 Patrick Lehmann - Boetzingen, Germany #
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  # #
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  # you may not use this file except in compliance with the License. #
{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/Xilinx/ISE.py RENAMED
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  # #
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  # ==================================================================================================================== #
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- # Copyright 2017-2025 Patrick Lehmann - Boetzingen, Germany #
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+ # Copyright 2017-2026 Patrick Lehmann - Boetzingen, Germany #
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  # #
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  # you may not use this file except in compliance with the License. #
{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/Xilinx/Vivado.py RENAMED
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  # ==================================================================================================================== #
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+ # Copyright 2017-2026 Patrick Lehmann - Boetzingen, Germany #
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{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/Xilinx/__init__.py RENAMED
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  # #
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  # ==================================================================================================================== #
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+ # Copyright 2017-2026 Patrick Lehmann - Boetzingen, Germany #
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{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA/ProjectModel/__init__.py RENAMED
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  # #
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  # ==================================================================================================================== #
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- # Copyright 2017-2025 Patrick Lehmann - Boetzingen, Germany #
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+ # Copyright 2017-2026 Patrick Lehmann - Boetzingen, Germany #
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  # Copyright 2014-2016 Technische Universität Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture #
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  # #
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  # Licensed under the Apache License, Version 2.0 (the "License"); #
@@ -32,15 +32,15 @@
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  """An abstract model of EDA tool projects."""
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  __author__ = "Patrick Lehmann"
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  __email__ = "Paebbels@gmail.com"
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- __copyright__ = "2014-2025, Patrick Lehmann, Unai Martinez-Corral"
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+ __copyright__ = "2014-2026, Patrick Lehmann, Unai Martinez-Corral"
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  __license__ = "Apache License, Version 2.0"
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- __version__ = "0.6.0"
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+ __version__ = "0.6.2"
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  __keywords__ = ["eda project", "model", "abstract", "xilinx", "vivado", "osvvm", "file set", "file group", "test bench", "test harness"]
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  from os.path import relpath as path_relpath
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  from pathlib import Path as pathlib_Path
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  from sys import version_info
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- from typing import Dict, Union, Optional as Nullable, List, Iterable, Generator, Tuple, Any as typing_Any, Type, Set, Any
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+ from typing import Dict, Union, Optional as Nullable, List, Iterable, Generator, Tuple, Any as typing_Any, Type, Set, Self
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  from pyTooling.Common import getFullyQualifiedName
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  from pyTooling.Decorators import export
@@ -80,11 +80,11 @@ class FileType(ExtendedType):
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  FileTypes: Dict[str, 'FileType'] = {} #: Dictionary of all classes of type :class:`FileType` or derived variants
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+ def __init__(cls, name: str, bases: Tuple[type, ...], dictionary: Dict[str, typing_Any], **kwargs) -> None:
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  cls.Any = cls
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  cls.FileTypes[className] = fileType
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@@ -128,7 +128,7 @@ class File(metaclass=FileType, slots=True):
128
128
  project: Nullable["Project"] = None,
129
129
  design: Nullable["Design"] = None,
130
130
  fileSet: Nullable["FileSet"] = None
131
- ):
131
+ ) -> None:
132
132
  self._fileType = getattr(FileTypes, self.__class__.__name__)
133
133
  self._path = path
134
134
  if project is not None:
@@ -259,7 +259,7 @@ class File(metaclass=FileType, slots=True):
259
259
  """
260
260
  return len(self._attributes)
261
261
 
262
- def __getitem__(self, key: Type[Attribute]) -> Any:
262
+ def __getitem__(self, key: Type[Attribute]) -> typing_Any:
263
263
  """Index access for returning attributes on this file.
264
264
 
265
265
  :param key: The attribute type.
@@ -416,7 +416,7 @@ class VHDLSourceFile(HDLSourceFile, HumanReadableContent):
416
416
  _vhdlLibrary: Nullable['VHDLLibrary']
417
417
  _vhdlVersion: VHDLVersion
418
418
 
419
- def __init__(self, path: pathlib_Path, vhdlLibrary: Union[str, 'VHDLLibrary'] = None, vhdlVersion: Nullable[VHDLVersion] = None, project: Nullable["Project"] = None, design: Nullable["Design"] = None, fileSet: Nullable["FileSet"] = None):
419
+ def __init__(self, path: pathlib_Path, vhdlLibrary: Union[str, 'VHDLLibrary'] = None, vhdlVersion: Nullable[VHDLVersion] = None, project: Nullable["Project"] = None, design: Nullable["Design"] = None, fileSet: Nullable["FileSet"] = None) -> None:
420
420
  super().__init__(path, project, design, fileSet)
421
421
 
422
422
  if isinstance(vhdlLibrary, str):
@@ -527,7 +527,7 @@ class SystemVerilogMixIn(metaclass=ExtendedType, mixin=True):
527
527
  class VerilogBaseFile(HDLSourceFile, HumanReadableContent):
528
528
  _version: SystemVerilogVersion
529
529
 
530
- def __init__(self, path: pathlib_Path, version: Nullable[SystemVerilogVersion] = None, project: Nullable["Project"] = None, design: Nullable["Design"] = None, fileSet: Nullable["FileSet"] = None):
530
+ def __init__(self, path: pathlib_Path, version: Nullable[SystemVerilogVersion] = None, project: Nullable["Project"] = None, design: Nullable["Design"] = None, fileSet: Nullable["FileSet"] = None) -> None:
531
531
  super().__init__(path, project, design, fileSet)
532
532
 
533
533
  self._version = version
@@ -564,7 +564,7 @@ class SystemRDLSourceFile(RDLSourceFile, HumanReadableContent):
564
564
 
565
565
  _srdlVersion: SystemRDLVersion
566
566
 
567
- def __init__(self, path: pathlib_Path, srdlVersion: Nullable[SystemRDLVersion] = None, project: Nullable["Project"] = None, design: Nullable["Design"] = None, fileSet: Nullable["FileSet"] = None):
567
+ def __init__(self, path: pathlib_Path, srdlVersion: Nullable[SystemRDLVersion] = None, project: Nullable["Project"] = None, design: Nullable["Design"] = None, fileSet: Nullable["FileSet"] = None) -> None:
568
568
  super().__init__(path, project, design, fileSet)
569
569
 
570
570
  self._srdlVersion = srdlVersion
@@ -708,7 +708,7 @@ class FileSet(metaclass=ExtendedType, slots=True):
708
708
  verilogVersion: Nullable[SystemVerilogVersion] = None,
709
709
  svVersion: Nullable[SystemVerilogVersion] = None,
710
710
  srdlVersion: Nullable[SystemRDLVersion] = None
711
- ):
711
+ ) -> None:
712
712
  self._name = name
713
713
  self._topLevel = topLevel
714
714
  if project is not None:
@@ -998,7 +998,7 @@ class FileSet(metaclass=ExtendedType, slots=True):
998
998
  elif self._parent is not None:
999
999
  return self._parent.VHDLLibrary
1000
1000
  elif self._design is not None:
1001
- return self._design.VHDLLibrary
1001
+ return self._design.VHDLLibrary # FIXME: no library property. add a DefaultVHDLLibrary property
1002
1002
  else:
1003
1003
  raise Exception("VHDLLibrary was neither set locally nor globally.")
1004
1004
 
@@ -1077,7 +1077,7 @@ class FileSet(metaclass=ExtendedType, slots=True):
1077
1077
  """
1078
1078
  return len(self._attributes)
1079
1079
 
1080
- def __getitem__(self, key: Type[Attribute]) -> Any:
1080
+ def __getitem__(self, key: Type[Attribute]) -> typing_Any:
1081
1081
  """Index access for returning attributes on this fileset.
1082
1082
 
1083
1083
  :param key: The attribute type.
@@ -1138,6 +1138,7 @@ class VHDLLibrary(metaclass=ExtendedType, slots=True):
1138
1138
  _files: List[File]
1139
1139
  _vhdlVersion: VHDLVersion
1140
1140
 
1141
+ _attributes: Dict[Attribute, typing_Any]
1141
1142
  _dependencyNode: Vertex
1142
1143
 
1143
1144
  def __init__(
@@ -1146,8 +1147,10 @@ class VHDLLibrary(metaclass=ExtendedType, slots=True):
1146
1147
  project: Nullable["Project"] = None,
1147
1148
  design: Nullable["Design"] = None,
1148
1149
  vhdlVersion: Nullable[VHDLVersion] = None
1149
- ):
1150
- self._name = name
1150
+ ) -> None:
1151
+ self._name = name
1152
+ self._attributes = {}
1153
+
1151
1154
  if project is not None:
1152
1155
  self._project = project
1153
1156
  self._design = project._defaultDesign if design is None else design
@@ -1279,7 +1282,7 @@ class VHDLLibrary(metaclass=ExtendedType, slots=True):
1279
1282
  """
1280
1283
  return len(self._attributes)
1281
1284
 
1282
- def __getitem__(self, key: Type[Attribute]) -> Any:
1285
+ def __getitem__(self, key: Type[Attribute]) -> typing_Any:
1283
1286
  """Index access for returning attributes on this VHDL library.
1284
1287
 
1285
1288
  :param key: The attribute type.
@@ -1370,7 +1373,7 @@ class Design(metaclass=ExtendedType, slots=True):
1370
1373
  verilogVersion: Nullable[SystemVerilogVersion] = None,
1371
1374
  svVersion: Nullable[SystemVerilogVersion] = None,
1372
1375
  srdlVersion: Nullable[SystemRDLVersion] = None
1373
- ):
1376
+ ) -> None:
1374
1377
  self._name = name
1375
1378
  self._topLevel = topLevel
1376
1379
  self._project = project
@@ -1637,7 +1640,7 @@ class Design(metaclass=ExtendedType, slots=True):
1637
1640
  """
1638
1641
  return len(self._attributes)
1639
1642
 
1640
- def __getitem__(self, key: Type[Attribute]) -> Any:
1643
+ def __getitem__(self, key: Type[Attribute]) -> typing_Any:
1641
1644
  """Index access for returning attributes on this design.
1642
1645
 
1643
1646
  :param key: The attribute type.
@@ -1710,7 +1713,7 @@ class Project(metaclass=ExtendedType, slots=True):
1710
1713
  vhdlVersion: Nullable[VHDLVersion] = None,
1711
1714
  verilogVersion: Nullable[SystemVerilogVersion] = None,
1712
1715
  svVersion: Nullable[SystemVerilogVersion] = None
1713
- ):
1716
+ ) -> None:
1714
1717
  self._name = name
1715
1718
  self._rootDirectory = rootDirectory
1716
1719
  self._designs = {}
@@ -1829,7 +1832,7 @@ class Project(metaclass=ExtendedType, slots=True):
1829
1832
  """
1830
1833
  return len(self._attributes)
1831
1834
 
1832
- def __getitem__(self, key: Type[Attribute]) -> Any:
1835
+ def __getitem__(self, key: Type[Attribute]) -> typing_Any:
1833
1836
  """Index access for returning attributes on this project.
1834
1837
 
1835
1838
  :param key: The attribute type.
{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyEDAA.ProjectModel.egg-info/PKG-INFO RENAMED
@@ -1,6 +1,6 @@
1
1
  Metadata-Version: 2.4
2
2
  Name: pyEDAA.ProjectModel
3
- Version: 0.6.0
3
+ Version: 0.6.2
4
4
  Summary: An abstract model of EDA tool projects.
5
5
  Home-page: https://GitHub.com/edaa-org/pyEDAA.ProjectModel
6
6
  Author: Patrick Lehmann
@@ -24,60 +24,60 @@ Classifier: Development Status :: 4 - Beta
24
24
  Requires-Python: >=3.11
25
25
  Description-Content-Type: text/markdown
26
26
  License-File: LICENSE.md
27
- Requires-Dist: pyVHDLModel~=0.31
28
- Requires-Dist: pySVModel~=0.5
29
- Requires-Dist: pySystemRDLModel~=0.3
30
- Requires-Dist: pyTooling~=8.7
27
+ Requires-Dist: pySystemRDLModel~=0.3.0
28
+ Requires-Dist: pyTooling~=8.11
29
+ Requires-Dist: pySVModel~=0.5.0
30
+ Requires-Dist: pyVHDLModel~=0.33.0
31
31
  Provides-Extra: doc
32
- Requires-Dist: pySVModel~=0.5; extra == "doc"
33
- Requires-Dist: pySystemRDLModel~=0.3; extra == "doc"
34
- Requires-Dist: docutils~=0.21; extra == "doc"
35
- Requires-Dist: sphinx_design~=0.6; extra == "doc"
36
- Requires-Dist: pyVHDLModel~=0.31; extra == "doc"
37
- Requires-Dist: sphinx-copybutton>=0.5; extra == "doc"
38
- Requires-Dist: sphinxcontrib-mermaid~=1.0; extra == "doc"
32
+ Requires-Dist: docutils~=0.22.0; extra == "doc"
33
+ Requires-Dist: pyTooling~=8.11; extra == "doc"
34
+ Requires-Dist: pySystemRDLModel~=0.3.0; extra == "doc"
35
+ Requires-Dist: sphinx-copybutton>=0.5.0; extra == "doc"
39
36
  Requires-Dist: docutils_stubs~=0.0.22; extra == "doc"
40
- Requires-Dist: sphinx~=8.2; extra == "doc"
41
- Requires-Dist: sphinx_autodoc_typehints~=3.5; extra == "doc"
42
- Requires-Dist: sphinx_reports~=0.9; extra == "doc"
43
- Requires-Dist: pyTooling~=8.7; extra == "doc"
44
- Requires-Dist: sphinx_rtd_theme~=3.0; extra == "doc"
37
+ Requires-Dist: sphinx_autodoc_typehints~=3.6; extra == "doc"
38
+ Requires-Dist: sphinxcontrib-mermaid~=2.0; extra == "doc"
39
+ Requires-Dist: pySVModel~=0.5.0; extra == "doc"
45
40
  Requires-Dist: autoapi>=2.0.1; extra == "doc"
41
+ Requires-Dist: pyVHDLModel~=0.33.0; extra == "doc"
42
+ Requires-Dist: sphinx_reports~=0.10.0; extra == "doc"
43
+ Requires-Dist: sphinx~=9.1; extra == "doc"
44
+ Requires-Dist: sphinx_rtd_theme~=3.1; extra == "doc"
45
+ Requires-Dist: sphinx_design~=0.7.0; extra == "doc"
46
46
  Provides-Extra: test
47
- Requires-Dist: mypy[reports]~=1.18; extra == "test"
48
- Requires-Dist: pySVModel~=0.5; extra == "test"
49
- Requires-Dist: pySystemRDLModel~=0.3; extra == "test"
47
+ Requires-Dist: mypy[reports]~=1.19; extra == "test"
48
+ Requires-Dist: pyTooling~=8.11; extra == "test"
49
+ Requires-Dist: Coverage~=7.13; extra == "test"
50
+ Requires-Dist: pySystemRDLModel~=0.3.0; extra == "test"
51
+ Requires-Dist: pytest-cov~=7.0; extra == "test"
52
+ Requires-Dist: pySVModel~=0.5.0; extra == "test"
50
53
  Requires-Dist: lxml<7.0,>=5.4; extra == "test"
51
- Requires-Dist: Coverage~=7.11; extra == "test"
52
- Requires-Dist: pyVHDLModel~=0.31; extra == "test"
53
- Requires-Dist: pyTooling~=8.7; extra == "test"
54
- Requires-Dist: pytest~=8.4; extra == "test"
54
+ Requires-Dist: pyVHDLModel~=0.33.0; extra == "test"
55
+ Requires-Dist: pytest~=9.0; extra == "test"
55
56
  Requires-Dist: typing_extensions~=4.15; extra == "test"
56
- Requires-Dist: pytest-cov~=7.0; extra == "test"
57
57
  Provides-Extra: osvvm
58
58
  Requires-Dist: pyEDAA.OSVVM~=0.6; extra == "osvvm"
59
59
  Provides-Extra: all
60
- Requires-Dist: pySystemRDLModel~=0.3; extra == "all"
61
- Requires-Dist: sphinx_design~=0.6; extra == "all"
62
- Requires-Dist: sphinx-copybutton>=0.5; extra == "all"
63
60
  Requires-Dist: docutils_stubs~=0.0.22; extra == "all"
64
- Requires-Dist: lxml<7.0,>=5.4; extra == "all"
65
- Requires-Dist: sphinx_autodoc_typehints~=3.5; extra == "all"
66
- Requires-Dist: sphinxcontrib-mermaid~=1.0; extra == "all"
67
- Requires-Dist: sphinx~=8.2; extra == "all"
68
- Requires-Dist: pyEDAA.OSVVM~=0.6; extra == "all"
69
- Requires-Dist: pyTooling~=8.7; extra == "all"
70
- Requires-Dist: sphinx_rtd_theme~=3.0; extra == "all"
71
- Requires-Dist: mypy[reports]~=1.18; extra == "all"
72
- Requires-Dist: pySVModel~=0.5; extra == "all"
73
- Requires-Dist: docutils~=0.21; extra == "all"
74
- Requires-Dist: Coverage~=7.11; extra == "all"
75
- Requires-Dist: pyVHDLModel~=0.31; extra == "all"
61
+ Requires-Dist: sphinx_autodoc_typehints~=3.6; extra == "all"
62
+ Requires-Dist: pySVModel~=0.5.0; extra == "all"
63
+ Requires-Dist: sphinx_design~=0.7.0; extra == "all"
64
+ Requires-Dist: pySystemRDLModel~=0.3.0; extra == "all"
65
+ Requires-Dist: pyVHDLModel~=0.33.0; extra == "all"
66
+ Requires-Dist: docutils~=0.22.0; extra == "all"
67
+ Requires-Dist: sphinx-copybutton>=0.5.0; extra == "all"
76
68
  Requires-Dist: pytest-cov~=7.0; extra == "all"
77
- Requires-Dist: typing_extensions~=4.15; extra == "all"
78
- Requires-Dist: sphinx_reports~=0.9; extra == "all"
79
- Requires-Dist: pytest~=8.4; extra == "all"
69
+ Requires-Dist: sphinxcontrib-mermaid~=2.0; extra == "all"
80
70
  Requires-Dist: autoapi>=2.0.1; extra == "all"
71
+ Requires-Dist: mypy[reports]~=1.19; extra == "all"
72
+ Requires-Dist: sphinx~=9.1; extra == "all"
73
+ Requires-Dist: sphinx_rtd_theme~=3.1; extra == "all"
74
+ Requires-Dist: typing_extensions~=4.15; extra == "all"
75
+ Requires-Dist: pyTooling~=8.11; extra == "all"
76
+ Requires-Dist: pyEDAA.OSVVM~=0.6; extra == "all"
77
+ Requires-Dist: Coverage~=7.13; extra == "all"
78
+ Requires-Dist: lxml<7.0,>=5.4; extra == "all"
79
+ Requires-Dist: sphinx_reports~=0.10.0; extra == "all"
80
+ Requires-Dist: pytest~=9.0; extra == "all"
81
81
  Dynamic: author
82
82
  Dynamic: author-email
83
83
  Dynamic: classifier
pyedaa_projectmodel-0.6.2/pyEDAA.ProjectModel.egg-info/requires.txt ADDED
@@ -0,0 +1,58 @@
1
+ pySystemRDLModel~=0.3.0
2
+ pyTooling~=8.11
3
+ pySVModel~=0.5.0
4
+ pyVHDLModel~=0.33.0
5
+
6
+ [all]
7
+ docutils_stubs~=0.0.22
8
+ sphinx_autodoc_typehints~=3.6
9
+ pySVModel~=0.5.0
10
+ sphinx_design~=0.7.0
11
+ pySystemRDLModel~=0.3.0
12
+ pyVHDLModel~=0.33.0
13
+ docutils~=0.22.0
14
+ sphinx-copybutton>=0.5.0
15
+ pytest-cov~=7.0
16
+ sphinxcontrib-mermaid~=2.0
17
+ autoapi>=2.0.1
18
+ mypy[reports]~=1.19
19
+ sphinx~=9.1
20
+ sphinx_rtd_theme~=3.1
21
+ typing_extensions~=4.15
22
+ pyTooling~=8.11
23
+ pyEDAA.OSVVM~=0.6
24
+ Coverage~=7.13
25
+ lxml<7.0,>=5.4
26
+ sphinx_reports~=0.10.0
27
+ pytest~=9.0
28
+
29
+ [doc]
30
+ docutils~=0.22.0
31
+ pyTooling~=8.11
32
+ pySystemRDLModel~=0.3.0
33
+ sphinx-copybutton>=0.5.0
34
+ docutils_stubs~=0.0.22
35
+ sphinx_autodoc_typehints~=3.6
36
+ sphinxcontrib-mermaid~=2.0
37
+ pySVModel~=0.5.0
38
+ autoapi>=2.0.1
39
+ pyVHDLModel~=0.33.0
40
+ sphinx_reports~=0.10.0
41
+ sphinx~=9.1
42
+ sphinx_rtd_theme~=3.1
43
+ sphinx_design~=0.7.0
44
+
45
+ [osvvm]
46
+ pyEDAA.OSVVM~=0.6
47
+
48
+ [test]
49
+ mypy[reports]~=1.19
50
+ pyTooling~=8.11
51
+ Coverage~=7.13
52
+ pySystemRDLModel~=0.3.0
53
+ pytest-cov~=7.0
54
+ pySVModel~=0.5.0
55
+ lxml<7.0,>=5.4
56
+ pyVHDLModel~=0.33.0
57
+ pytest~=9.0
58
+ typing_extensions~=4.15
{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/pyproject.toml RENAMED
@@ -1,8 +1,8 @@
1
1
  [build-system]
2
2
  requires = [
3
3
  "setuptools >= 80.0",
4
- "wheel ~= 0.45",
5
- "pyTooling ~= 8.7"
4
+ "wheel ~= 0.45.0",
5
+ "pyTooling ~= 8.11"
6
6
  ]
7
7
  build-backend = "setuptools.build_meta"
8
8
 
@@ -36,23 +36,21 @@ namespace_packages = true
36
36
  html_report = "report/typing"
37
37
 
38
38
  [tool.pytest]
39
- junit_xml = "report/unit/UnittestReportSummary.xml"
40
-
41
- [tool.pyedaa-reports]
42
- junit_xml = "report/unit/unittest.xml"
43
-
44
- [tool.pytest.ini_options]
45
- addopts = "--tb=native"
39
+ addopts = ["--tb=native"]
46
40
  # Don't set 'python_classes = *' otherwise, pytest doesn't search for classes
47
41
  # derived from unittest.Testcase
48
- python_files = "*"
49
- python_functions = "test_*"
42
+ python_files = ["*"]
43
+ python_functions = ["test_*"]
50
44
  filterwarnings = [
51
45
  "error::DeprecationWarning",
52
46
  "error::PendingDeprecationWarning"
53
47
  ]
48
+ junit_xml = "report/unit/UnittestReportSummary.xml"
54
49
  junit_logging = "all"
55
50
 
51
+ [tool.pyedaa-reports]
52
+ junit_xml = "report/unit/unittest.xml"
53
+
56
54
  [tool.interrogate]
57
55
  color = true
58
56
  verbose = 1 # possible values: 0 (minimal output), 1 (-v), 2 (-vv)
{pyedaa_projectmodel-0.6.0 → pyedaa_projectmodel-0.6.2}/setup.py RENAMED
@@ -11,7 +11,7 @@
11
11
  # #
12
12
  # License: #
13
13
  # ==================================================================================================================== #
14
- # Copyright 2017-2025 Patrick Lehmann - Boetzingen, Germany #
14
+ # Copyright 2017-2026 Patrick Lehmann - Boetzingen, Germany #
15
15
  # Copyright 2014-2016 Technische Universität Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture #
16
16
  # #
17
17
  # Licensed under the Apache License, Version 2.0 (the "License"); #
pyedaa_projectmodel-0.6.0/pyEDAA.ProjectModel.egg-info/requires.txt DELETED
@@ -1,58 +0,0 @@
1
- pyVHDLModel~=0.31
2
- pySVModel~=0.5
3
- pySystemRDLModel~=0.3
4
- pyTooling~=8.7
5
-
6
- [all]
7
- pySystemRDLModel~=0.3
8
- sphinx_design~=0.6
9
- sphinx-copybutton>=0.5
10
- docutils_stubs~=0.0.22
11
- lxml<7.0,>=5.4
12
- sphinx_autodoc_typehints~=3.5
13
- sphinxcontrib-mermaid~=1.0
14
- sphinx~=8.2
15
- pyEDAA.OSVVM~=0.6
16
- pyTooling~=8.7
17
- sphinx_rtd_theme~=3.0
18
- mypy[reports]~=1.18
19
- pySVModel~=0.5
20
- docutils~=0.21
21
- Coverage~=7.11
22
- pyVHDLModel~=0.31
23
- pytest-cov~=7.0
24
- typing_extensions~=4.15
25
- sphinx_reports~=0.9
26
- pytest~=8.4
27
- autoapi>=2.0.1
28
-
29
- [doc]
30
- pySVModel~=0.5
31
- pySystemRDLModel~=0.3
32
- docutils~=0.21
33
- sphinx_design~=0.6
34
- pyVHDLModel~=0.31
35
- sphinx-copybutton>=0.5
36
- sphinxcontrib-mermaid~=1.0
37
- docutils_stubs~=0.0.22
38
- sphinx~=8.2
39
- sphinx_autodoc_typehints~=3.5
40
- sphinx_reports~=0.9
41
- pyTooling~=8.7
42
- sphinx_rtd_theme~=3.0
43
- autoapi>=2.0.1
44
-
45
- [osvvm]
46
- pyEDAA.OSVVM~=0.6
47
-
48
- [test]
49
- mypy[reports]~=1.18
50
- pySVModel~=0.5
51
- pySystemRDLModel~=0.3
52
- lxml<7.0,>=5.4
53
- Coverage~=7.11
54
- pyVHDLModel~=0.31
55
- pyTooling~=8.7
56
- pytest~=8.4
57
- typing_extensions~=4.15
58
- pytest-cov~=7.0