pyEDAA.ProjectModel 0.4.2__tar.gz → 0.5.0__tar.gz
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/PKG-INFO +49 -9
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/Altera/Quartus.py +1 -1
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/Altera/__init__.py +1 -1
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/Attributes.py +2 -2
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/GHDL.py +1 -1
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/Intel/QuartusPrime.py +1 -1
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/Intel/__init__.py +1 -1
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/MentorGraphics/ModelSim.py +1 -1
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/MentorGraphics/QuestaSim.py +1 -1
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/MentorGraphics/__init__.py +1 -1
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/OSVVM.py +7 -7
- pyedaa_projectmodel-0.5.0/pyEDAA/ProjectModel/VHDL.py +0 -0
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/Verilog.py +1 -1
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/Xilinx/ISE.py +1 -1
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/Xilinx/Vivado.py +26 -25
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/Xilinx/__init__.py +1 -1
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/__init__.py +653 -193
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA.ProjectModel.egg-info/PKG-INFO +49 -9
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA.ProjectModel.egg-info/SOURCES.txt +1 -0
- pyedaa_projectmodel-0.5.0/pyEDAA.ProjectModel.egg-info/requires.txt +48 -0
- pyedaa_projectmodel-0.5.0/pyproject.toml +76 -0
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/setup.py +11 -4
- pyEDAA.ProjectModel-0.4.2/pyEDAA.ProjectModel.egg-info/requires.txt +0 -23
- pyEDAA.ProjectModel-0.4.2/pyproject.toml +0 -36
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/LICENSE.md +0 -0
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/README.md +0 -0
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA.ProjectModel.egg-info/dependency_links.txt +0 -0
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA.ProjectModel.egg-info/top_level.txt +0 -0
- {pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/setup.cfg +0 -0
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Metadata-Version: 2.1
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Name: pyEDAA.ProjectModel
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Version: 0.
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Version: 0.5.0
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Summary: An abstract model of EDA tool projects.
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Home-page: https://GitHub.com/edaa-org/pyEDAA.ProjectModel
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Author: Patrick Lehmann
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Project-URL: Source Code, https://GitHub.com/edaa-org/pyEDAA.ProjectModel
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Project-URL: Issue Tracker, https://GitHub.com/edaa-org/pyEDAA.ProjectModel/issues
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Keywords: eda project,model,abstract,xilinx,vivado,osvvm,file set,file group,test bench,test harness
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Platform: UNKNOWN
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Classifier: Operating System :: OS Independent
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Classifier: Intended Audience :: Developers
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Classifier: Topic :: Utilities
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Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
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Classifier: License :: OSI Approved :: Apache Software License
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Classifier: Programming Language :: Python :: 3 :: Only
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Classifier: Programming Language :: Python :: 3.6
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Classifier: Programming Language :: Python :: 3.7
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Classifier: Programming Language :: Python :: 3.9
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Classifier: Programming Language :: Python :: 3.10
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Classifier: Programming Language :: Python :: 3.11
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Classifier: Programming Language :: Python :: 3.12
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Classifier: Programming Language :: Python :: 3.13
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Classifier: Development Status :: 4 - Beta
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Requires-Python: >=3.
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Requires-Python: >=3.9
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Description-Content-Type: text/markdown
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License-File: LICENSE.md
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Requires-Dist: pySVModel~=0.5
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Requires-Dist: pySystemRDLModel~=0.3
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Requires-Dist: pyTooling~=7.0
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Requires-Dist: pyVHDLModel~=0.29.1
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Provides-Extra: doc
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Requires-Dist: pySystemRDLModel~=0.3; extra == "doc"
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Requires-Dist: sphinx_fontawesome>=0.0.6; extra == "doc"
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Requires-Dist: autoapi>=2.0.1; extra == "doc"
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Requires-Dist: sphinxcontrib-mermaid~=1.0; extra == "doc"
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Requires-Dist: docutils_stubs~=0.0.22; extra == "doc"
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Requires-Dist: pyVHDLModel~=0.29.1; extra == "doc"
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Requires-Dist: sphinx_autodoc_typehints~=2.5; extra == "doc"
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Provides-Extra: test
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Requires-Dist: pySystemRDLModel~=0.3; extra == "test"
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Requires-Dist: typing_extensions~=4.12; extra == "test"
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Requires-Dist: pytest~=8.3; extra == "test"
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Requires-Dist: Coverage~=7.6; extra == "test"
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Requires-Dist: lxml~=5.3; extra == "test"
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Requires-Dist: pyVHDLModel~=0.29.1; extra == "test"
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Requires-Dist: mypy~=1.13; extra == "test"
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Provides-Extra: all
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Requires-Dist: docutils_stubs~=0.0.22; extra == "all"
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Requires-Dist: pyVHDLModel~=0.29.1; extra == "all"
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<p align="center">
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<a title="edaa-org.github.io/pySVModel" href="https://edaa-org.github.io/pyEDAA.ProjectModel"><img height="80px" src="doc/_static/logo_on_dark.svg"/></a>
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-------------------------
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SPDX-License-Identifier: Apache-2.0
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{pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/Altera/Quartus.py
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# #
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# License: #
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# ==================================================================================================================== #
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# Copyright 2017-
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# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany #
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# #
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# Licensed under the Apache License, Version 2.0 (the "License"); #
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# you may not use this file except in compliance with the License. #
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{pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/Altera/__init__.py
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# #
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# License: #
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# ==================================================================================================================== #
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# Licensed under the Apache License, Version 2.0 (the "License"); #
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# #
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# License: #
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# Licensed under the Apache License, Version 2.0 (the "License"); #
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# you may not use this file except in compliance with the License. #
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_keyValuePairs: Dict[str, str]
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# License: #
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# you may not use this file except in compliance with the License. #
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{pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/Intel/QuartusPrime.py
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# Licensed under the Apache License, Version 2.0 (the "License"); #
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# you may not use this file except in compliance with the License. #
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{pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/Xilinx/Vivado.py
RENAMED
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@@ -11,7 +11,7 @@
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# #
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# License: #
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# ==================================================================================================================== #
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# Copyright 2017-
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# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany #
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# #
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# Licensed under the Apache License, Version 2.0 (the "License"); #
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# you may not use this file except in compliance with the License. #
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@@ -30,11 +30,12 @@
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#
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"""Specific file types and attributes for Xilinx Vivado."""
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from pathlib import Path
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from typing
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from typing import Iterable, Optional as Nullable
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from xml.dom import minidom, Node
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from pyTooling.Decorators
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from pyTooling.Decorators import export
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from pyTooling.MetaClasses import ExtendedType
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from pyVHDLModel import VHDLVersion
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from pyEDAA.ProjectModel import ProjectFile, XMLFile, XMLContent, SDCContent, Project, FileSet, Attribute, Design
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from pyEDAA.ProjectModel import File as Model_File
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pass
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class VivadoFileMixIn:
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def _registerAttributes(self):
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class VivadoFileMixIn(metaclass=ExtendedType, mixin=True):
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def _registerAttributes(self) -> None:
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self._attributes[UsedInAttribute] = []
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@export
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class ConstraintFile(Model_ConstraintFile, VivadoFileMixIn):
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def _registerAttributes(self):
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def _registerAttributes(self) -> None:
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super()._registerAttributes()
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VivadoFileMixIn._registerAttributes(self)
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@export
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class VerilogSourceFile(Model_VerilogSourceFile):
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def _registerAttributes(self):
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def _registerAttributes(self) -> None:
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super()._registerAttributes()
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VivadoFileMixIn._registerAttributes(self)
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@export
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class VHDLSourceFile(Model_VHDLSourceFile):
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def _registerAttributes(self):
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def _registerAttributes(self) -> None:
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super()._registerAttributes()
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VivadoFileMixIn._registerAttributes(self)
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def __init__(
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self,
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path: Path,
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project: Project = None,
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design:
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fileSet: FileSet = None
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):
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project: Nullable[Project] = None,
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design: Nullable[Design] = None,
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fileSet: Nullable[FileSet] = None
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) -> None:
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super().__init__(path, project, design, fileSet)
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self._xprProject = None
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def ProjectModel(self) -> Project:
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return self._xprProject
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def Parse(self):
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def Parse(self) -> None:
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if not self._path.exists():
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raise Exception(f"Vivado project file '{self._path!s}' not found.") from FileNotFoundError(f"File '{self._path!s}' not found.")
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self._xprProject = Project(self._path.stem, rootDirectory=self._path.parent)
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self._ParseRootElement(root)
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def _ParseRootElement(self, root):
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def _ParseRootElement(self, root) -> None:
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for rootNode in root.childNodes:
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if rootNode.nodeName == "FileSets":
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self._ParseFileSets(rootNode)
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break
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def _ParseFileSets(self, filesetsNode):
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def _ParseFileSets(self, filesetsNode) -> None:
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for fileSetsNode in filesetsNode.childNodes:
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if fileSetsNode.nodeType == Node.ELEMENT_NODE and fileSetsNode.tagName == "FileSet":
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self._ParseFileSet(fileSetsNode)
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def _ParseFileSet(self, filesetNode):
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def _ParseFileSet(self, filesetNode) -> None:
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filesetName = filesetNode.getAttribute("Name")
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fileset = FileSet(filesetName, design=self._xprProject.DefaultDesign)
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elif fileNode.nodeType == Node.ELEMENT_NODE and fileNode.tagName == "Config":
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self._ParseFileSetConfig(fileNode, fileset)
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def _ParseFile(self, fileNode, fileset):
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def _ParseFile(self, fileNode, fileset) -> None:
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croppedPath = fileNode.getAttribute("Path").replace("$PPRDIR/", "")
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filePath = Path(croppedPath)
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if filePath.suffix in (".vhd", ".vhdl"):
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else:
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self._ParseDefaultFile(fileNode, filePath, fileset)
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def _ParseVHDLFile(self, fileNode, path, fileset):
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def _ParseVHDLFile(self, fileNode, path, fileset) -> None:
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vhdlFile = VHDLSourceFile(path)
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fileset.AddFile(vhdlFile)
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usedInAttr = vhdlFile[UsedInAttribute]
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elif fileAttribute.getAttribute("Val") == "UsedIn":
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usedInAttr.append(fileAttribute.getAttribute("Val"))
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def _ParseDefaultFile(self, _, path, fileset):
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def _ParseDefaultFile(self, _, path, fileset) -> None:
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File(path, fileSet=fileset)
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def _ParseXDCFile(self, _, path, fileset):
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def _ParseXDCFile(self, _, path, fileset) -> None:
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XDCConstraintFile(path, fileSet=fileset)
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def _ParseVerilogFile(self, _, path, fileset):
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def _ParseVerilogFile(self, _, path, fileset) -> None:
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VerilogSourceFile(path, fileSet=fileset)
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def _ParseXCIFile(self, _, path, fileset):
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def _ParseXCIFile(self, _, path, fileset) -> None:
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IPCoreInstantiationFile(path, fileSet=fileset)
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def _ParseFileSetConfig(self, fileNode, fileset):
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def _ParseFileSetConfig(self, fileNode, fileset) -> None:
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for option in fileNode.childNodes:
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if option.nodeType == Node.ELEMENT_NODE and option.tagName == "Option":
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if option.getAttribute("Name") == "TopModule":
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{pyEDAA.ProjectModel-0.4.2 → pyedaa_projectmodel-0.5.0}/pyEDAA/ProjectModel/Xilinx/__init__.py
RENAMED
|
@@ -11,7 +11,7 @@
|
|
|
11
11
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# #
|
|
12
12
|
# License: #
|
|
13
13
|
# ==================================================================================================================== #
|
|
14
|
-
# Copyright 2017-
|
|
14
|
+
# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany #
|
|
15
15
|
# #
|
|
16
16
|
# Licensed under the Apache License, Version 2.0 (the "License"); #
|
|
17
17
|
# you may not use this file except in compliance with the License. #
|