pyEDAA.OutputFilter 0.2.0__tar.gz → 0.3.0__tar.gz

{pyedaa_outputfilter-0.2.0 → pyedaa_outputfilter-0.3.0}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: pyEDAA.OutputFilter
-Version: 0.2.0
+Version: 0.3.0
 Summary: Post-processing of EDA Tool outputs (log files).
 Home-page: https://GitHub.com/edaa-org/pyEDAA.OutputFilter
 Author: Patrick Lehmann
@@ -27,45 +27,45 @@ Description-Content-Type: text/markdown
 License-File: LICENSE.md
 Requires-Dist: pyTooling[terminal]~=8.5
 Provides-Extra: doc
-Requires-Dist: sphinx_design~=0.6.1; extra == "doc"
 Requires-Dist: pyTooling[terminal]~=8.5; extra == "doc"
 Requires-Dist: docutils_stubs~=0.0.22; extra == "doc"
-Requires-Dist: sphinx_rtd_theme~=3.0; extra == "doc"
-Requires-Dist: sphinxcontrib-mermaid~=1.0; extra == "doc"
 Requires-Dist: sphinx_autodoc_typehints~=3.2; extra == "doc"
-Requires-Dist: sphinx-copybutton>=0.5.2; extra == "doc"
+Requires-Dist: sphinxcontrib-autoprogram~=0.1; extra == "doc"
 Requires-Dist: sphinx~=8.2; extra == "doc"
-Requires-Dist: sphinx_reports~=0.9; extra == "doc"
+Requires-Dist: sphinx_design~=0.6.1; extra == "doc"
+Requires-Dist: sphinxcontrib-mermaid~=1.0; extra == "doc"
 Requires-Dist: autoapi>=2.0.1; extra == "doc"
+Requires-Dist: sphinx-copybutton>=0.5.2; extra == "doc"
+Requires-Dist: sphinx_reports~=0.9; extra == "doc"
+Requires-Dist: sphinx_rtd_theme~=3.0; extra == "doc"
 Requires-Dist: docutils~=0.21; extra == "doc"
-Requires-Dist: sphinxcontrib-autoprogram~=0.1; extra == "doc"
 Provides-Extra: test
 Requires-Dist: pyTooling[terminal]~=8.5; extra == "test"
+Requires-Dist: pytest~=8.4; extra == "test"
 Requires-Dist: typing_extensions~=4.14; extra == "test"
+Requires-Dist: mypy~=1.16; extra == "test"
 Requires-Dist: pytest-cov~=6.2; extra == "test"
-Requires-Dist: pytest~=8.4; extra == "test"
 Requires-Dist: Coverage~=7.9; extra == "test"
 Requires-Dist: lxml~=5.4; extra == "test"
-Requires-Dist: mypy~=1.16; extra == "test"
 Provides-Extra: all
-Requires-Dist: sphinx_design~=0.6.1; extra == "all"
 Requires-Dist: pyTooling[terminal]~=8.5; extra == "all"
+Requires-Dist: pytest~=8.4; extra == "all"
+Requires-Dist: Coverage~=7.9; extra == "all"
 Requires-Dist: docutils_stubs~=0.0.22; extra == "all"
-Requires-Dist: sphinxcontrib-mermaid~=1.0; extra == "all"
-Requires-Dist: sphinx_rtd_theme~=3.0; extra == "all"
 Requires-Dist: sphinx_autodoc_typehints~=3.2; extra == "all"
-Requires-Dist: sphinx-copybutton>=0.5.2; extra == "all"
+Requires-Dist: sphinxcontrib-autoprogram~=0.1; extra == "all"
 Requires-Dist: sphinx~=8.2; extra == "all"
-Requires-Dist: typing_extensions~=4.14; extra == "all"
-Requires-Dist: sphinx_reports~=0.9; extra == "all"
-Requires-Dist: pytest-cov~=6.2; extra == "all"
-Requires-Dist: pytest~=8.4; extra == "all"
-Requires-Dist: Coverage~=7.9; extra == "all"
 Requires-Dist: lxml~=5.4; extra == "all"
+Requires-Dist: typing_extensions~=4.14; extra == "all"
+Requires-Dist: sphinx_design~=0.6.1; extra == "all"
+Requires-Dist: sphinxcontrib-mermaid~=1.0; extra == "all"
 Requires-Dist: autoapi>=2.0.1; extra == "all"
-Requires-Dist: docutils~=0.21; extra == "all"
-Requires-Dist: sphinxcontrib-autoprogram~=0.1; extra == "all"
+Requires-Dist: sphinx-copybutton>=0.5.2; extra == "all"
+Requires-Dist: sphinx_reports~=0.9; extra == "all"
+Requires-Dist: sphinx_rtd_theme~=3.0; extra == "all"
 Requires-Dist: mypy~=1.16; extra == "all"
+Requires-Dist: docutils~=0.21; extra == "all"
+Requires-Dist: pytest-cov~=6.2; extra == "all"
 Dynamic: author
 Dynamic: author-email
 Dynamic: classifier
@@ -127,7 +127,7 @@ Dynamic: summary
 
 ```python
 from pathlib import Path
-from pyEDAA.OutputFilter.Xilinx.Synthesis import Processor
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import Processor
 
 logfile = Path("tests/data/Stopwatch/toplevel.vds")
 processor = Processor(logfile)

{pyedaa_outputfilter-0.2.0 → pyedaa_outputfilter-0.3.0}/README.md

@@ -44,7 +44,7 @@
 
 ```python
 from pathlib import Path
-from pyEDAA.OutputFilter.Xilinx.Synthesis import Processor
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import Processor
 
 logfile = Path("tests/data/Stopwatch/toplevel.vds")
 processor = Processor(logfile)

{pyedaa_outputfilter-0.2.0 → pyedaa_outputfilter-0.3.0}/pyEDAA/OutputFilter/CLI/Vivado.py

@@ -38,13 +38,16 @@ from pyTooling.Attributes.ArgParse             import CommandHandler
 from pyTooling.Attributes.ArgParse.Flag        import LongFlag
 from pyTooling.Attributes.ArgParse.ValuedFlag  import LongValuedFlag
 
-from pyEDAA.OutputFilter.Xilinx                import Preamble, LineKind, Line
-from pyEDAA.OutputFilter.Xilinx.Synthesis      import WritingSynthesisReport, Processor, LoadingPart
+from pyEDAA.OutputFilter.Xilinx                  import Document, ProcessorException, SynthesizeDesign
+from pyEDAA.OutputFilter.Xilinx.Common           import LineKind, Line
+from pyEDAA.OutputFilter.Xilinx.Common2          import Preamble
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import WritingSynthesisReport, LoadingPart
+
 
 
 class VivadoHandlers(metaclass=ExtendedType, mixin=True):
-	@CommandHandler("vivado-synth", help="Parse AMD/Xilinx Vivado Synthesis log files.", description="Parse AMD/Xilinx Vivado Synthesis log files.")
-	@LongValuedFlag("--file", dest="logfile", metaName='Synthesis Log', help="Synthesis log file (*.vds).")
+	@CommandHandler("vivado", help="Parse AMD/Xilinx Vivado log files.", description="Parse AMD/Xilinx Vivado log files.")
+	@LongValuedFlag("--file", dest="logfile", metaName='Log file', help="Log file (*.vds|*.vdi).")
 	@LongFlag("--colored", dest="colored", help="Render logfile with colored lines.")
 	@LongFlag("--summary", dest="summary", help="Print a summary.")
 	@LongFlag("--info", dest="info", help="Print info messages.")
@@ -53,8 +56,8 @@ class VivadoHandlers(metaclass=ExtendedType, mixin=True):
 	@LongFlag("--error", dest="error", help="Print error messages.")
 	@LongFlag("--influxdb", dest="influxdb", help="Write statistics as InfluxDB line protocol file (*.line).")
 	# @LongValuedFlag("--file", dest="logfile", metaName='Synthesis Log', help="Synthesis log file (*.vds).")
-	def HandleVivadoSynthesis(self, args: Namespace) -> None:
-		"""Handle program calls with command ``vivado-synth``."""
+	def HandleVivado(self, args: Namespace) -> None:
+		"""Handle program calls with command ``vivado``."""
 		self._PrintHeadline()
 
 		returnCode = 0
@@ -64,13 +67,13 @@ class VivadoHandlers(metaclass=ExtendedType, mixin=True):
 
 		logfile = Path(args.logfile)
 		if not logfile.exists():
-			self.WriteError(f"Vivado synthesis log file '{logfile}' doesn't exist.")
+			self.WriteError(f"Vivado log file '{logfile}' doesn't exist.")
 			returnCode = 4
 
 		if returnCode != 0:
 			self.Exit(returnCode)
 
-		processor = Processor(logfile)
+		processor = Document(logfile)
 		processor.Parse()
 
 		if args.colored:
@@ -94,98 +97,108 @@ class VivadoHandlers(metaclass=ExtendedType, mixin=True):
 				self.WriteNormal(f"  {message}")
 
 		if args.influxdb:
+			synthesizeDesign = processor[SynthesizeDesign]
 			influxString  =  "vivado_synthesis_overview"
-			influxString += f",version={processor[Preamble].ToolVersion}"
+			influxString += f",version={processor.Preamble.ToolVersion}"
 			influxString += f",branch=main"
 			influxString += f",design=Stopwatch"
 			influxString += " "
 			influxString += f"processing_duration={processor.Duration:.3f}"
-			influxString += f",synthesis_duration={processor[WritingSynthesisReport].Duration:.1f}"
+			influxString += f",synthesis_duration={synthesizeDesign[WritingSynthesisReport].Duration:.1f}"
 			influxString += f",info_count={len(processor.InfoMessages)}u"
 			influxString += f",warning_count={len(processor.WarningMessages)}u"
 			influxString += f",critical_count={len(processor.CriticalWarningMessages)}u"
 			influxString += f",error_count={len(processor.ErrorMessages)}u"
-			influxString += f",blackbox_count={len(processor[WritingSynthesisReport].Blackboxes)}u"
+			influxString += f",blackbox_count={len(synthesizeDesign[WritingSynthesisReport].Blackboxes)}u"
 			influxString +=  "\n"
 			influxString +=  "vivado_synthesis_cells"
-			influxString += f",version={processor[Preamble].ToolVersion}"
+			influxString += f",version={processor.Preamble.ToolVersion}"
 			influxString += f",branch=main"
 			influxString += f",design=Stopwatch"
 			influxString += " "
-			influxString += ",".join(f"{cellName}={cellCount}" for cellName, cellCount in processor[WritingSynthesisReport].Cells.items() if not cellName.endswith("_bbox"))
+			influxString += ",".join(f"{cellName}={cellCount}" for cellName, cellCount in synthesizeDesign[WritingSynthesisReport].Cells.items() if not cellName.endswith("_bbox"))
 
 			self.WriteNormal(influxString)
 
 		if args.summary:
+			synthesizeDesign : SynthesizeDesign = processor[SynthesizeDesign]
 			self.WriteNormal("Summary:")
-			self.WriteNormal(f"  Tool version:        {processor[Preamble].ToolVersion}")
-			self.WriteNormal(f"  Started at:          {processor[Preamble].StartDatetime}")
+			self.WriteNormal(f"  Tool version:        {processor.Preamble.ToolVersion}")
+			self.WriteNormal(f"  Started at:          {processor.Preamble.StartDatetime}")
 			self.WriteNormal(f"  Processing duration: {processor.Duration:.3f} s")
 			self.WriteNormal(f"  Info:                {len(processor.InfoMessages)}")
 			self.WriteNormal(f"  Warning:             {len(processor.WarningMessages)}")
 			self.WriteNormal(f"  Critical Warning:    {len(processor.CriticalWarningMessages)}")
 			self.WriteNormal(f"  Error:               {len(processor.ErrorMessages)}")
-			self.WriteNormal(f"  Part:                {processor[LoadingPart].Part}")
+			self.WriteNormal(f"  Part:                {synthesizeDesign[LoadingPart].Part}")
 
 			self.WriteNormal("Policies:")
-			self.WriteNormal(f"  Latches:             {'found' if processor.HasLatches else '----'}")
-			if processor.HasLatches:
+			self.WriteNormal(f"  Latches:             {'found' if synthesizeDesign.HasLatches else '----'}")
+			if synthesizeDesign.HasLatches:
 				for cellName in ("LD", ):
 					try:
-						self.WriteNormal(f"    {cellName}: {processor.Cells[cellName]}")
+						self.WriteNormal(f"    {cellName}: {synthesizeDesign.Cells[cellName]}")
 					except KeyError:
 						pass
-				for latch in processor.Latches:
+				for latch in synthesizeDesign.Latches:
 					self.WriteNormal(f"    {latch}")
-			self.WriteNormal(f"  Blackboxes:          {'found' if processor.HasBlackboxes else '----'}")
-			if processor.HasBlackboxes:
-				for bbox in processor[WritingSynthesisReport].Blackboxes:
+			self.WriteNormal(f"  Blackboxes:          {'found' if synthesizeDesign.HasBlackboxes else '----'}")
+			if synthesizeDesign.HasBlackboxes:
+				for bbox in synthesizeDesign.Blackboxes:
 					self.WriteNormal(f"    {bbox}")
 
-			self.WriteNormal(f"VHDL report statements ({len(processor.VHDLReportMessages)}):")
-			for message in processor.VHDLReportMessages:
+			self.WriteNormal(f"VHDL report statements ({len(synthesizeDesign.VHDLReportMessages)}):")
+			for message in synthesizeDesign.VHDLReportMessages:
 				self.WriteNormal(f"  {message}")
-			self.WriteNormal(f"VHDL assert statements ({len(processor.VHDLAssertMessages)}):")
-			for message in processor.VHDLAssertMessages:
+			self.WriteNormal(f"VHDL assert statements ({len(synthesizeDesign.VHDLAssertMessages)}):")
+			for message in synthesizeDesign.VHDLAssertMessages:
 				self.WriteNormal(f"  {message}")
 
-			self.WriteNormal(f"Cells: {len(processor.Cells)}")
-			for cell, count in processor.Cells.items():
+			self.WriteNormal(f"Cells: {len(synthesizeDesign.Cells)}")
+			for cell, count in synthesizeDesign.Cells.items():
 				self.WriteNormal(f"  {cell}: {count}")
 
 		self.ExitOnPreviousErrors()
 
 	def ColoredOutput(self, lines: Iterable[Line]) -> None:
 		for i, line in enumerate(lines, start=1):
-			if line.Kind is LineKind.Normal:
+			message = str(line).replace("{", "{{").replace("}", "}}")
+			if isinstance(line, ProcessorException):
+				print(f"{i:4}: {{RED}}EXCEPTION:{{NOCOLOR}} {message}".format(**self.Foreground))
+			elif line.Kind is LineKind.Normal:
 				print(f"{i:4}: {line.Message}")
 			elif LineKind.Message in line.Kind:
 				if line.Kind is LineKind.InfoMessage:
-					print(f"{i:4}: {{BLUE}}{line}{{NOCOLOR}}".format(**self.Foreground))
+					print(f"{i:4}: {{BLUE}}{message}{{NOCOLOR}}".format(**self.Foreground))
 				elif line.Kind is LineKind.WarningMessage:
-					print(f"{i:4}: {{YELLOW}}{line}{{NOCOLOR}}".format(**self.Foreground))
+					print(f"{i:4}: {{YELLOW}}{message}{{NOCOLOR}}".format(**self.Foreground))
 				elif line.Kind is LineKind.CriticalWarningMessage:
-					print(f"{i:4}: {{MAGENTA}}{line}{{NOCOLOR}}".format(**self.Foreground))
+					print(f"{i:4}: {{MAGENTA}}{message}{{NOCOLOR}}".format(**self.Foreground))
 				elif line.Kind is LineKind.ErrorMessage:
-					print(f"{i:4}: {{RED}}{line}{{NOCOLOR}}".format(**self.Foreground))
-			elif LineKind.Command in line.Kind:
-				print(f"{i:4}: {{CYAN}}{line}{{NOCOLOR}}".format(**self.Foreground))
+					print(f"{i:4}: {{RED}}{message}{{NOCOLOR}}".format(**self.Foreground))
+			elif LineKind.TclCommand in line.Kind:
+				print(f"{i:4}: {{CYAN}}{message}{{NOCOLOR}}".format(**self.Foreground))
 			elif (LineKind.Start in line.Kind) or (LineKind.End in line.Kind):
-				print(f"{i:4}: {{DARK_CYAN}}{line}{{NOCOLOR}}".format(**self.Foreground))
+				if LineKind.Phase in line.Kind:
+					print(f"{i:4}: {{YELLOW}}{message}{{NOCOLOR}}".format(**self.Foreground))
+				else:
+					print(f"{i:4}: {{DARK_CYAN}}{message}{{NOCOLOR}}".format(**self.Foreground))
 			elif line.Kind is LineKind.ParagraphHeadline:
-				print(f"{i:4}: {{DARK_YELLOW}}{line}{{NOCOLOR}}".format(**self.Foreground))
+				print(f"{i:4}: {{DARK_YELLOW}}{message}{{NOCOLOR}}".format(**self.Foreground))
 			elif LineKind.Table in line.Kind:
-				print(f"{i:4}: {{WHITE}}{line}{{NOCOLOR}}".format(**self.Foreground))
+				print(f"{i:4}: {{WHITE}}{message}{{NOCOLOR}}".format(**self.Foreground))
 			elif LineKind.Delimiter in line.Kind:
-				print(f"{i:4}: {{GRAY}}{line}{{NOCOLOR}}".format(**self.Foreground))
+				print(f"{i:4}: {{GRAY}}{message}{{NOCOLOR}}".format(**self.Foreground))
 			elif LineKind.Verbose in line.Kind:
-				print(f"{i:4}: {{DARK_GRAY}}{line}{{NOCOLOR}}".format(**self.Foreground))
+				print(f"{i:4}: {{DARK_GRAY}}{message}{{NOCOLOR}}".format(**self.Foreground))
+			elif LineKind.Success in line.Kind:
+				print(f"{i:4}: {{GREEN}}{message}{{NOCOLOR}}".format(**self.Foreground))
 			elif line.Kind is LineKind.Empty:
 				print(f"{i:4}:")
 			elif line.Kind is LineKind.ProcessorError:
-				print(f"{i:4}: {{RED}}{line}{{NOCOLOR}}".format(**self.Foreground))
+				print(f"{i:4}: {{RED}}{message}{{NOCOLOR}}".format(**self.Foreground))
 			elif line.Kind is LineKind.Unprocessed:
-				print(f"{i:4}: {{DARK_RED}}{line}{{NOCOLOR}}".format(**self.Foreground))
+				print(f"{i:4}: {{DARK_RED}}{message}{{NOCOLOR}}".format(**self.Foreground))
 			else:
 				print(f"{i:4}: Unknown LineKind '{line._kind}' for line {line._lineNumber}.")
 				print(line)

pyedaa_outputfilter-0.3.0/pyEDAA/OutputFilter/Xilinx/Commands.py

@@ -0,0 +1,285 @@
+# ==================================================================================================================== #
+#               _____ ____    _        _      ___        _               _   _____ _ _ _                               #
+#   _ __  _   _| ____|  _ \  / \      / \    / _ \ _   _| |_ _ __  _   _| |_|  ___(_) | |_ ___ _ __                    #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \  | | | | | | | __| '_ \| | | | __| |_  | | | __/ _ \ '__|                   #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ | |_| | |_| | |_| |_) | |_| | |_|  _| | | | ||  __/ |                      #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)___/ \__,_|\__| .__/ \__,_|\__|_|   |_|_|\__\___|_|                      #
+#  |_|    |___/                                             |_|                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2025-2025 Electronic Design Automation Abstraction (EDA²)                                                  #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""Basic classes for outputs from AMD/Xilinx Vivado."""
+from typing import ClassVar, Generator, Union, List, Type, Dict, Iterator, Any
+
+from pyTooling.Decorators import export, readonly
+
+from pyEDAA.OutputFilter.Xilinx           import VivadoTclCommand
+from pyEDAA.OutputFilter.Xilinx.Exception import ProcessorException
+from pyEDAA.OutputFilter.Xilinx.Common    import Line, LineKind, VivadoMessage, VHDLReportMessage
+from pyEDAA.OutputFilter.Xilinx.Common2   import Parser
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import Section, RTLElaboration, HandlingCustomAttributes
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import ConstraintValidation, LoadingPart, ApplySetProperty
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import RTLComponentStatistics, PartResourceSummary
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import CrossBoundaryAndAreaOptimization, ROM_RAM_DSP_SR_Retiming
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import ApplyingXDCTimingConstraints, TimingOptimization
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import TechnologyMapping, IOInsertion, FlatteningBeforeIOInsertion
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import FinalNetlistCleanup, RenamingGeneratedInstances
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import RebuildingUserHierarchy, RenamingGeneratedPorts
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import RenamingGeneratedNets, WritingSynthesisReport
+
+
+@export
+class NotPresentException(ProcessorException):
+	pass
+
+
+@export
+class SectionNotPresentException(NotPresentException):
+	pass
+
+
+@export
+class HandlingCustomAttributes1(HandlingCustomAttributes):
+	pass
+
+
+@export
+class HandlingCustomAttributes2(HandlingCustomAttributes):
+	pass
+
+
+@export
+class ROM_RAM_DSP_SR_Retiming1(ROM_RAM_DSP_SR_Retiming):
+	pass
+
+
+@export
+class ROM_RAM_DSP_SR_Retiming2(ROM_RAM_DSP_SR_Retiming):
+	pass
+
+
+@export
+class ROM_RAM_DSP_SR_Retiming3(ROM_RAM_DSP_SR_Retiming):
+	pass
+
+
+@export
+class Command(Parser):
+	# _TCL_COMMAND: ClassVar[str]
+	pass
+
+
+@export
+class SynthesizeDesign(Command):
+	_TCL_COMMAND: ClassVar[str] = "synth_design"
+	_PARSERS:     ClassVar[List[Type[Section]]] = (
+		RTLElaboration,
+		HandlingCustomAttributes1,
+		ConstraintValidation,
+		LoadingPart,
+		ApplySetProperty,
+		RTLComponentStatistics,
+		PartResourceSummary,
+		CrossBoundaryAndAreaOptimization,
+		ROM_RAM_DSP_SR_Retiming1,
+		ApplyingXDCTimingConstraints,
+		TimingOptimization,
+		ROM_RAM_DSP_SR_Retiming2,
+		TechnologyMapping,
+		IOInsertion,
+		FlatteningBeforeIOInsertion,
+		FinalNetlistCleanup,
+		RenamingGeneratedInstances,
+		RebuildingUserHierarchy,
+		RenamingGeneratedPorts,
+		HandlingCustomAttributes2,
+		RenamingGeneratedNets,
+		ROM_RAM_DSP_SR_Retiming3,
+		WritingSynthesisReport,
+	)
+
+	_sections:  Dict[Type[Section], Section]
+
+	def __init__(self, processor: "Processor") -> None:
+		super().__init__(processor)
+
+		self._sections =  {p: p(self) for p in self._PARSERS}
+
+	@readonly
+	def HasLatches(self) -> bool:
+		if (8 in self._messagesByID) and (327 in self._messagesByID[8]):
+			return True
+
+		return "LD" in self._sections[WritingSynthesisReport]._cells
+
+	@readonly
+	def Latches(self) -> Iterator[VivadoMessage]:
+		try:
+			yield from iter(self._messagesByID[8][327])
+		except KeyError:
+			yield from ()
+
+	@readonly
+	def HasBlackboxes(self) -> bool:
+		return len(self._sections[WritingSynthesisReport]._blackboxes) > 0
+
+	@readonly
+	def Blackboxes(self) -> Dict[str, int]:
+		return self._sections[WritingSynthesisReport]._blackboxes
+
+	@readonly
+	def Cells(self) -> Dict[str, int]:
+		return self._sections[WritingSynthesisReport]._cells
+
+	@readonly
+	def VHDLReportMessages(self) -> List[VHDLReportMessage]:
+		if 8 in self._messagesByID:
+			if 6031 in (synthMessages := self._messagesByID[8]):
+				return [message for message in synthMessages[6031]]
+
+		return []
+
+	@readonly
+	def VHDLAssertMessages(self) -> List[VHDLReportMessage]:
+		if 8 in self._messagesByID:
+			if 63 in (synthMessages := self._messagesByID[8]):
+				return [message for message in synthMessages[63]]
+
+		return []
+
+	def __getitem__(self, item: Type[Parser]) -> Union[_PARSERS]:
+		try:
+			return self._sections[item]
+		except KeyError as ex:
+			raise SectionNotPresentException(F"Section '{item._NAME}' not present in '{self._parent.logfile}'.") from ex
+
+	def SectionDetector(self, line: Line) -> Generator[Union[Line, ProcessorException], Line, None]:
+		# parser:        Section      = firstValue(self._sections)
+		activeParsers: List[Parser] = list(self._sections.values())
+
+		rtlElaboration = self._sections[RTLElaboration]
+		# constraintValidation = self._sections[ConstraintValidation]
+
+		if not (isinstance(line, VivadoTclCommand) and line._command == self._TCL_COMMAND):
+			raise ProcessorException()
+
+		line = yield line
+		if line == "Starting synth_design":
+			line._kind = LineKind.Verbose
+		else:
+			raise ProcessorException()
+
+		line = yield line
+
+		while True:
+			while True:
+				if line.StartsWith("Start "):
+					for parser in activeParsers:  # type: Section
+						if line.StartsWith(parser._START):
+							line = next(section := parser.Generator(line))
+							line._previousLine._kind = LineKind.SectionStart | LineKind.SectionDelimiter
+							break
+					else:
+						raise Exception(f"Unknown section: {line}")
+					break
+				elif line.StartsWith("Starting "):
+					if line.StartsWith(rtlElaboration._START):
+						parser = rtlElaboration
+						line = next(section := parser.Generator(line))
+						line._previousLine._kind = LineKind.SectionStart | LineKind.SectionDelimiter
+						break
+				elif line.StartsWith(self._TCL_COMMAND):
+					if line[len(self._TCL_COMMAND) + 1:].startswith("completed successfully"):
+						line._kind |= LineKind.Success
+
+						line = yield line
+						if line.StartsWith(self._TCL_COMMAND + ":"):
+							line._kind |= LineKind.Last
+						else:
+							pass
+
+						lastLine = yield line
+						return lastLine
+				elif line.StartsWith("Finished RTL Optimization Phase"):
+					line._kind = LineKind.PhaseEnd
+					line._previousLine._kind = LineKind.PhaseEnd | LineKind.PhaseDelimiter
+				elif line.StartsWith("----"):
+					if LineKind.Phase in line._previousLine._kind:
+						line._kind = LineKind.PhaseEnd | LineKind.PhaseDelimiter
+				elif not isinstance(line, VivadoMessage):
+					pass
+					# line._kind = LineKind.Unprocessed
+
+				line = yield line
+
+			line = yield line
+
+			while True:
+				if line.StartsWith("Finished"):
+					l = line[9:]
+					if not (l.startswith("Flattening") or l.startswith("Final")):
+						line = yield section.send(line)
+						break
+
+				if isinstance(line, VivadoMessage):
+					self._AddMessage(line)
+
+				line = yield section.send(line)
+
+			line = yield section.send(line)
+
+			activeParsers.remove(parser)
+
+
+@export
+class LinkDesign(Command):
+	_TCL_COMMAND: ClassVar[str] = "link_design"
+
+
+@export
+class OptimizeDesign(Command):
+	_TCL_COMMAND: ClassVar[str] = "opt_design"
+
+
+@export
+class PlaceDesign(Command):
+	_TCL_COMMAND: ClassVar[str] = "place_design"
+
+
+@export
+class PhysicalOptimizationDesign(Command):
+	_TCL_COMMAND: ClassVar[str] = "phys_opt_design"
+
+
+@export
+class PhysicalOptimizationDesign(Command):
+	_TCL_COMMAND: ClassVar[str] = "route_design"
+
+
+@export
+class WriteBitstream(Command):
+	_TCL_COMMAND: ClassVar[str] = "write_bitstream"
+
+# report_drc
+# report_methodology
+# report_power