powertrain-build 1.4.3.dev1__tar.gz → 1.4.3.dev3__tar.gz

{powertrain_build-1.4.3.dev1 → powertrain_build-1.4.3.dev3}/ChangeLog

@@ -1,21 +1,12 @@
 CHANGES
 =======
 
-* Wikerstaal calibration hacks
-
-1.4.2
------
+1.4.3.dev3
+----------
 
+* New scope on nvm block generated code: type 2 write calls should be written manually, no init calls needed
 * Bug fix for ZC dids
-
-1.4.1
------
-
 * Bug fix in composition\_yaml.py
-
-1.4.0
------
-
 * Added RTE interface enum doc
 * Adding lsb, offset to curves and maps
 * Fix issue with mapping to Rte enums when enum does not have a key for integer 0

{powertrain_build-1.4.3.dev1 → powertrain_build-1.4.3.dev3}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.2
 Name: powertrain-build
-Version: 1.4.3.dev1
+Version: 1.4.3.dev3
 Summary: A Continuous Integration (CI) build system testing all configurations where a Simulink model is used.
 Home-page: https://opendev.org/volvocars/powertrain-build
 Download-URL: https://pypi.org/project/powertrain-build/
@@ -21,6 +21,7 @@ Classifier: Topic :: Software Development :: Embedded Systems
 Description-Content-Type: text/x-rst; charset=UTF-8
 License-File: LICENSE
 License-File: NOTICE
+License-File: AUTHORS
 Requires-Dist: gitpython>=3.1.8
 Requires-Dist: pbr>=6.0.0
 Requires-Dist: requests==2.32.3

{powertrain_build-1.4.3.dev1 → powertrain_build-1.4.3.dev3}/powertrain_build/build.py

@@ -884,7 +884,7 @@ def build(
         copy_unit_cfgs_to_output(build_cfg)
         copy_files_to_include(build_cfg)
         if code_generation_config["generateInterfaceHeaders"]:
-            memory_section = MemorySection(build_cfg, unit_cfg)
+            memory_section = MemorySection(build_cfg)
             memory_section.generate_required_header_files()
 
         # Propagate tag name for release builds, TAG_NAME must be set in environment

{powertrain_build-1.4.3.dev1 → powertrain_build-1.4.3.dev3}/powertrain_build/memory_section.py

@@ -32,10 +32,9 @@ class MemorySection(ProblemLogger):
         'CVC_DISP_ASIL_D'
     ]
 
-    def __init__(self, build_cfg, unit_cfg):
+    def __init__(self, build_cfg):
         super().__init__()
         self.build_cfg = build_cfg
-        self.unit_cfg = unit_cfg
         self.mem_map_config = self.build_cfg.get_memory_map_config()
         self.include_header_guards = self.mem_map_config['includeHeaderGuards']
         self.mem_map_include = f'#include "{self.mem_map_config["memMapPrefix"]}_MemMap.h"\n'
@@ -87,35 +86,13 @@ class MemorySection(ProblemLogger):
         ]
         return cvc_undefines, cvc_defines, memory_section_handling
 
-    def _get_wikerstaal_hack(self, section_file):
-        hacks = self._get_header(section_file)
-        swc_name = self.build_cfg.get_composition_config("softwareComponentName")
-        hacks.append(f'#include "Rte_{swc_name}.h"\n')
-
-        config = self.unit_cfg.get_per_cfg_unit_cfg()
-        valid_configs = ["outports", "local_vars", "calib_consts"]
-        for valid_config in valid_configs:
-            for signal_name, unit_info in config.get(valid_config, {}).items():
-                define_str = f'#define {signal_name} Rte_CData_{signal_name}()'
-                for info in unit_info.values():  # Should be length 1 for cal
-                    if "CVC_CAL" in info["class"]:
-                        if signal_name.startswith("m") and not signal_name.endswith("_r") and not signal_name.endswith("_c"):
-                            define_str += f"->dt_{signal_name}"
-                        define_str += "\n"
-                        hacks.append(define_str)
-
-        hacks.extend(self._get_footer(section_file))
-
-        return hacks
-
-    def _get_code(self, section, section_file):
+    def _get_code(self, section):
         cvc_undefines = []
         cvc_defines = []
         memory_section_handling = [
             self.mem_map_config['projectDefines'][self._get_mem_map_section(section)]['code'] + '\n',
             self.mem_map_include
         ]
-        memory_section_handling.extend(self._get_wikerstaal_hack(section_file))
         return cvc_undefines, cvc_defines, memory_section_handling
 
     def _get_const(self, section):
@@ -171,7 +148,7 @@ class MemorySection(ProblemLogger):
             if section_file.startswith('CVC_CAL') or section_file.startswith('CVC_DISP'):
                 self.critical('Should not find CVC_CAL/DISP here. Check logic. File: %s.', section_file)
             elif section_file.startswith('CVC_CODE'):
-                cvc_undefines, cvc_defines, memory_section_handling = self._get_code(section, section_file)
+                cvc_undefines, cvc_defines, memory_section_handling = self._get_code(section)
             elif section_file.startswith('CVC_CONST'):
                 cvc_undefines, cvc_defines, memory_section_handling = self._get_const(section)
             else:

{powertrain_build-1.4.3.dev1 → powertrain_build-1.4.3.dev3}/powertrain_build/nvm_def.py

@@ -664,29 +664,47 @@ class ZCNVMDef(NVMDef):
             f'#include "{bd.CVC_CODE_ASIL_D_START}"\n'
             f"{self.main_function} {{\n",
             "  //Call this function in the SWC main runnable\n",
-            "  UInt8 errorStatus = 0;\n",
         ]
         footer = [
             "}\n",
             f'#include "{bd.CVC_CODE_ASIL_D_END}"\n',
         ]
 
-        for nvm_name, nvm_data in self.valid_nvm_definitions.items():
-            pim_call = f"Rte_Pim_{nvm_name}()"
-            function_prefix = f"Rte_Call_{nvm_port_pattern.format(NvName=nvm_name)}"
-            main_function_lines.append(f"  *{pim_call} = {nvm_name.lower()};\n")
-            if nvm_data["type"] == "type1":
-                init_function_lines.append(f"  {function_prefix}_SetRamBlockStatus(TRUE);\n")
-            elif nvm_data["type"] == "type2":
-                main_function_lines.extend([
-                    f"  {function_prefix}_GetErrorStatus(&errorStatus);\n",
-                    "  if (errorStatus == 0) {\n",
-                    f"    {function_prefix}_WriteBlock({pim_call});\n",
-                    "  }\n",
-                ])
-            else:
-                self.critical(f"Unknown NVM type: {nvm_data['type']} for NVM: {nvm_name}")
+        error_status = ""
+        rte_write_instructions = ""
+        nvsw_init_instructions = ""
+        manual_signals = []
 
+        for nvm_name, nvm_data in self.valid_nvm_definitions.items():
+            if nvm_data["method"] == "DIRECT-CALL":
+                pim_call = f"Rte_Pim_{nvm_name}()"
+                function_prefix = f"Rte_Call_{nvm_port_pattern.format(NvName=nvm_name)}"
+                main_function_lines.append(f"  *{pim_call} = {nvm_name.lower()};\n")
+                if nvm_data["type"] == "type1":
+                    init_function_lines.append(f"  {function_prefix}_SetRamBlockStatus(TRUE);\n")
+                elif nvm_data["type"] == "type2":
+                    error_status = "  UInt8 errorStatus = 0;\n",
+                    main_function_lines.extend([
+                        f"  {function_prefix}_GetErrorStatus(&errorStatus);\n",
+                        "  if (errorStatus == 0) {\n",
+                        f"    {function_prefix}_WriteBlock({pim_call});\n",
+                        "  }\n",
+                    ])
+                else:
+                    self.critical(f"Unknown NVM type: {nvm_data['type']} for NVM: {nvm_name}")
+            elif nvm_data["method"] == "NVSWCOMPONENT":
+                nvsw_init_instructions = "  // NVSWCOMPONENTS init calls are scheduled by the arxml.\n"
+                if nvm_data["type"] == "type1":
+                    main_function_lines.append(f"  (void)Rte_Write_{nvm_name.upper()}_{nvm_name.upper()}({nvm_name.lower()});\n")
+                elif nvm_data["type"] == "type2":
+                    rte_write_instructions = "  // Nvm write calls are not generated for type2, they need to be added manually to src.\n  // Nvm signals:\n"
+                    manual_signals.append(f"  // Nvm {nvm_name.lower()} is type 2 and needs a manually written write call in source code.\n")
+        init_function_lines.append(nvsw_init_instructions)
+        main_function_lines.append(error_status)
+        main_function_lines.extend(manual_signals)
+
+        if len(manual_signals) > 0:
+            self.warning('NVSWCOMPONENT write calls are not generated automatically for type 2, they have to be written manually and added to source code.')
         with open(self._file_name + ".c", mode="a", encoding="utf-8") as cptr:
             cptr.writelines(init_function_lines + footer + ["\n"] + main_function_lines + footer)
 

{powertrain_build-1.4.3.dev1 → powertrain_build-1.4.3.dev3}/powertrain_build.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.2
 Name: powertrain-build
-Version: 1.4.3.dev1
+Version: 1.4.3.dev3
 Summary: A Continuous Integration (CI) build system testing all configurations where a Simulink model is used.
 Home-page: https://opendev.org/volvocars/powertrain-build
 Download-URL: https://pypi.org/project/powertrain-build/
@@ -21,6 +21,7 @@ Classifier: Topic :: Software Development :: Embedded Systems
 Description-Content-Type: text/x-rst; charset=UTF-8
 License-File: LICENSE
 License-File: NOTICE
+License-File: AUTHORS
 Requires-Dist: gitpython>=3.1.8
 Requires-Dist: pbr>=6.0.0
 Requires-Dist: requests==2.32.3

powertrain_build-1.4.3.dev3/powertrain_build.egg-info/pbr.json

@@ -0,0 +1 @@
+{"git_version": "f1a8331", "is_release": true}

powertrain_build-1.4.3.dev1/powertrain_build.egg-info/pbr.json

@@ -1 +0,0 @@
-{"git_version": "1843626", "is_release": false}