peakrdl-python 2.2.0__tar.gz → 2.3.0__tar.gz

{peakrdl_python-2.2.0 → peakrdl_python-2.3.0}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: peakrdl-python
-Version: 2.2.0
+Version: 2.3.0
 Summary: Generate Python Register Access Layer (RAL) from SystemRDL
 Author: Keith Brady
 License:              GNU LESSER GENERAL PUBLIC LICENSE
@@ -191,7 +191,7 @@ Classifier: Typing :: Typed
 Requires-Python: >=3.9.2
 Description-Content-Type: text/markdown
 License-File: LICENSE
-Requires-Dist: systemrdl-compiler>=1.29.3
+Requires-Dist: systemrdl-compiler>=1.31.0
 Requires-Dist: jinja2
 Requires-Dist: typing-extensions; python_version < "3.11"
 Requires-Dist: more_itertools; python_version < "3.13"

{peakrdl_python-2.2.0 → peakrdl_python-2.3.0}/pyproject.toml

@@ -8,7 +8,7 @@ dynamic = ["version"]
 # Callable is broken in python 3.9.0 and 3.9.1 so these need to be excluded
 requires-python = ">=3.9.2"
 dependencies = [
-    "systemrdl-compiler>=1.29.3", # this is needed to make sure all the latest type checking
+    "systemrdl-compiler>=1.31.0", # this is needed for the latest overlappign register features
     "jinja2",
     "typing-extensions;python_version<'3.11'",
     # the batched fucntion was adopted into the standard python library at 3.13

{peakrdl_python-2.2.0 → peakrdl_python-2.3.0}/src/peakrdl_python/__about__.py

@@ -17,4 +17,4 @@ along with this program.  If not, see <https://www.gnu.org/licenses/>.
 
 Variables that describes the peakrdl-python Package
 """
-__version__ = "2.2.0"
+__version__ = "2.3.0"

{peakrdl_python-2.2.0 → peakrdl_python-2.3.0}/src/peakrdl_python/exporter.py

@@ -46,7 +46,7 @@ from .systemrdl_node_utility_functions import get_reg_writable_fields, \
     get_memory_max_entry_value_hex_string, get_memory_width_bytes, \
     get_field_default_value, get_enum_values, get_properties_to_include, \
     HideNodeCallback, hide_based_on_property, \
-    full_slice_accessor, ShowUDPCallback
+    full_slice_accessor, ShowUDPCallback, simulator_field_definition
 from .unique_component_iterator import UniqueComponents
 from .unique_component_iterator import PeakRDLPythonUniqueRegisterComponents
 from .unique_component_iterator import PeakRDLPythonUniqueMemoryComponents
@@ -675,16 +675,17 @@ class PythonExporter:
                 raise TypeError(f'node should be a register, got {type(node)}')
             reg_addr = node.absolute_address
             if reg_addr in reg_dict:
+                if not node.has_overlaps:
+                    raise RuntimeError('A non-overlaping node should not have a duplicate address')
                 existing_entry = reg_dict[reg_addr]
-                # if the entry is already list simply append to it
-                if isinstance(existing_entry, list):
-                    existing_entry.append(node)
-                elif isinstance(existing_entry, RegNode):
-                    reg_dict[reg_addr] = [existing_entry, node]
-                else:
-                    raise TypeError(f'exiting entry of unexpected type: {type(existing_entry)}')
+                if not isinstance(existing_entry, list):
+                    raise RuntimeError('A overlapping entry should have been made as list')
+                existing_entry.append(node)
             else:
-                reg_dict[reg_addr] = node
+                if node.has_overlaps:
+                    reg_dict[reg_addr] = [node,]
+                else:
+                    reg_dict[reg_addr] = node
 
 
         context = {
@@ -696,7 +697,8 @@ class PythonExporter:
             'asyncoutput': asyncoutput,
             'skip_lib_copy': skip_lib_copy,
             'legacy_block_access': legacy_block_access,
-            'list': list
+            'list': list,
+            'simulator_field_definition': simulator_field_definition,
         }
 
         module_name = top_block.inst_name

{peakrdl_python-2.2.0 → peakrdl_python-2.3.0}/src/peakrdl_python/sim_lib/field.py

@@ -20,7 +20,8 @@ peakrdl-python tool. It provides a set of base classes used by the autogenerated
 """
 from dataclasses import dataclass
 from typing import TYPE_CHECKING
-from typing import Optional
+from typing import Optional, Union
+from enum import Enum, auto
 
 from ..lib.utility_functions import swap_msb_lsb_ordering
 
@@ -33,19 +34,8 @@ if TYPE_CHECKING:
 
 # pylint: disable=too-many-instance-attributes,too-many-arguments
 
-
-@dataclass
-class FieldDefinition:
-    """
-    Class for an entry in the list of memories in the simulator
-    """
-    high: int
-    low: int
-    msb: int
-    lsb: int
-    inst_name: str
-
-class Field(Base):
+#pylint:disable-next=too-few-public-methods
+class _FieldBase(Base):
     """
     class for all fields
 
@@ -58,7 +48,7 @@ class Field(Base):
                  '__bitmask', '__inverse_bitmask',
                  '__msb0', '__lsb0',
                  '__parent_register','__parent_width',
-                 '__read_callback', '__write_callback']
+                 '_read_callback', '_write_callback']
 
     def __init__(self, *, low: int, high: int, msb: int, lsb: int,
                  parent_register: 'BaseRegister', parent_width: int, inst_name: str):
@@ -94,30 +84,8 @@ class Field(Base):
         parent_max_value = (2 ** parent_width) - 1
         self.__inverse_bitmask = parent_max_value ^ self.__bitmask
 
-        self.__read_callback: Optional[FieldReadCallback] = None
-        self.__write_callback: Optional[FieldWriteCallback] = None
-
-    @property
-    def read_callback(self) -> Optional[FieldReadCallback]:
-        """
-        Callback made during each read operation
-        """
-        return self.__read_callback
-
-    @read_callback.setter
-    def read_callback(self, callback: Optional[FieldReadCallback]) -> None:
-        self.__read_callback = callback
-
-    @property
-    def write_callback(self) -> Optional[FieldWriteCallback]:
-        """
-        Callback made during each write operation
-        """
-        return self.__write_callback
-
-    @write_callback.setter
-    def write_callback(self, callback: Optional[FieldWriteCallback]) -> None:
-        self.__write_callback = callback
+        self._write_callback: Optional[FieldWriteCallback] = None
+        self._read_callback: Optional[FieldReadCallback] = None
 
     @property
     def __width(self) -> int:
@@ -149,6 +117,89 @@ class Field(Base):
             self.__parent_register.value = value
         else:
             # do a read, modify write
-            reg_value = self.__parent_register.read()
+            reg_value = self.__parent_register.value
             self.__parent_register.value = (reg_value & self.__inverse_bitmask) | \
                                            (value << self.__low)
+
+class ReadOnlyField(_FieldBase):
+    """
+    Simulation of a read-only field
+    """
+    __slots__: list[str] = []
+
+    @property
+    def read_callback(self) -> Optional[FieldReadCallback]:
+        """
+        Callback made during each read operation
+        """
+        return self._read_callback
+
+    @read_callback.setter
+    def read_callback(self, callback: Optional[FieldReadCallback]) -> None:
+        self._read_callback = callback
+
+
+class WriteOnlyField(_FieldBase):
+    """
+    Simulation of a write-only field
+    """
+    __slots__:list[str] = []
+
+
+
+
+    @property
+    def write_callback(self) -> Optional[FieldWriteCallback]:
+        """
+        Callback made during each write operation
+        """
+        return self._write_callback
+
+    @write_callback.setter
+    def write_callback(self, callback: Optional[FieldWriteCallback]) -> None:
+        self._write_callback = callback
+
+class ReadWriteField(ReadOnlyField, WriteOnlyField):
+    """
+    Simulation of a read/write field
+    """
+    __slots__:list[str] = []
+
+
+Field = Union[ReadOnlyField, WriteOnlyField, ReadWriteField]
+
+
+class FieldType(Enum):
+    """
+    types of register field to be simulated based on the software access
+    """
+    READONLY = auto()
+    WRITEONLY = auto()
+    READWRITE = auto()
+
+
+_class_type_map: dict[FieldType, Union[type[ReadOnlyField],
+                                       type[WriteOnlyField],
+                                       type[ReadWriteField]]] = {
+    FieldType.READONLY: ReadOnlyField,
+    FieldType.WRITEONLY: WriteOnlyField,
+    FieldType.READWRITE: ReadWriteField}
+
+@dataclass
+class FieldDefinition:
+    """
+    Class for an entry in the list of memories in the simulator
+    """
+    high: int
+    low: int
+    msb: int
+    lsb: int
+    inst_name: str
+    field_type: FieldType
+
+    @property
+    def class_type(self) -> Union[type[ReadOnlyField], type[WriteOnlyField], type[ReadWriteField]]:
+        """
+        Classtype to be used base on the fieldtype
+        """
+        return _class_type_map[self.field_type]

{peakrdl_python-2.2.0 → peakrdl_python-2.3.0}/src/peakrdl_python/sim_lib/register.py

@@ -19,13 +19,23 @@ This module is intended to distributed as part of automatically generated code b
 peakrdl-python tool. It provides a set of base classes used by the autogenerated code
 """
 from abc import ABC, abstractmethod
-from typing import Optional
+from typing import Optional, Union
+import sys
+from collections.abc import Iterator
 
 from .memory import Memory
 from .base import Base
-from .field import FieldDefinition, Field
+from .field import FieldDefinition, ReadOnlyField, WriteOnlyField, ReadWriteField
 from ._callbacks import RegisterReadCallback,RegisterWriteCallback
 
+# pylint: disable=duplicate-code
+if sys.version_info >= (3, 10):
+    # type guarding was introduced in python 3.10
+    from typing import TypeGuard
+else:
+    from typing_extensions import TypeGuard
+# pylint: enable=duplicate-code
+
 # pylint: disable=too-many-arguments
 
 class BaseRegister(Base, ABC):
@@ -46,13 +56,13 @@ class BaseRegister(Base, ABC):
         self._width = width
         self._readable = readable
         self._writable = writable
-        self.fields = [Field(low=field_def.low,
-                             high=field_def.high,
-                             msb=field_def.msb,
-                             lsb=field_def.lsb,
-                             inst_name=field_def.inst_name,
-                             parent_register=self,
-                             parent_width=width) for field_def in fields]
+        self.fields = tuple(field_def.class_type(low=field_def.low,
+                                                 high=field_def.high,
+                                                 msb=field_def.msb,
+                                                 lsb=field_def.lsb,
+                                                 inst_name=field_def.inst_name,
+                                                 parent_register=self,
+                                                 parent_width=width) for field_def in fields)
         self.__read_callback: Optional[RegisterReadCallback] = None
         self.__write_callback: Optional[RegisterWriteCallback] = None
 
@@ -85,7 +95,7 @@ class BaseRegister(Base, ABC):
             # pylint: disable-next=not-callable
             self.read_callback(value=self.value)
 
-        for field in self.fields:
+        for field in self.readable_fields:
             if field.read_callback is not None:
                 field.read_callback(value=field.value)
 
@@ -96,7 +106,7 @@ class BaseRegister(Base, ABC):
             # pylint: disable-next=not-callable
             self.write_callback(value=self.value)
 
-        for field in self.fields:
+        for field in self.writable_fields:
             if field.write_callback is not None:
                 field.write_callback(value=field.value)
 
@@ -135,6 +145,28 @@ class BaseRegister(Base, ABC):
     def value(self, value:int) -> None:
         ...
 
+    @property
+    def writable_fields(self) -> Iterator[Union[WriteOnlyField, ReadWriteField]]:
+        """
+        Iterator of the Writable fields
+        """
+        def is_writable(field: Union[WriteOnlyField, ReadWriteField, ReadOnlyField]) -> \
+                TypeGuard[Union[WriteOnlyField, ReadWriteField]]:
+            return isinstance(field, (WriteOnlyField, ReadWriteField))
+
+        return filter(is_writable, self.fields)
+
+    @property
+    def readable_fields(self) -> Iterator[Union[ReadOnlyField, ReadWriteField]]:
+        """
+        Iterator of the Readable fields
+        """
+        def is_readable(field: Union[WriteOnlyField, ReadWriteField, ReadOnlyField]) -> \
+                TypeGuard[Union[ReadOnlyField, ReadWriteField]]:
+            return isinstance(field, (ReadOnlyField, ReadWriteField))
+
+        return filter(is_readable, self.fields)
+
 
 class Register(BaseRegister):
     """

{peakrdl_python-2.2.0 → peakrdl_python-2.3.0}/src/peakrdl_python/sim_lib/simulator.py

@@ -137,8 +137,8 @@ class BaseSimulator(ABC):
         return memory_entry
 
     def _read(self, addr: int,
-             width: int, # pylint: disable=unused-argument
-             accesswidth: int) -> int: # pylint: disable=unused-argument
+              width: int,  # pylint: disable=unused-argument
+              accesswidth: int) -> int:  # pylint: disable=unused-argument
         """
         function to simulate a device read, this needs to match the protocol for the callbacks
         """

{peakrdl_python-2.2.0 → peakrdl_python-2.3.0}/src/peakrdl_python/systemrdl_node_utility_functions.py

@@ -35,6 +35,7 @@ from systemrdl.node import SignalNode
 from systemrdl.rdltypes.user_enum import UserEnumMeta
 
 from .lib.utility_functions import calculate_bitmask
+from .sim_lib.field import FieldType
 
 class HideNodeCallback(Protocol):
     """
@@ -480,3 +481,22 @@ def full_slice_accessor(node: AddressableNode) -> str:
     if dimensions is None:
         raise RuntimeError('array node should have dimensions')
     return '[' + ','.join([':' for _ in range(len(dimensions))]) + ']'
+
+def simulator_field_definition(node: FieldNode) -> str:
+    """
+    Based on whether the field is readable and/or writeable, returns the value of the FieldType
+    to use
+    """
+    if not isinstance(node, FieldNode):
+        raise TypeError(f'This should only be called on an FieldNode, got {type(node)}')
+
+    if node.is_sw_readable and node.is_sw_writable:
+        return FieldType.READWRITE.name
+
+    if node.is_sw_readable and not node.is_sw_writable:
+        return FieldType.READONLY.name
+
+    if not node.is_sw_readable and node.is_sw_writable:
+        return FieldType.WRITEONLY.name
+
+    raise RuntimeError('Encountered a field node that was neither readable or writable')

{peakrdl_python-2.2.0 → peakrdl_python-2.3.0}/src/peakrdl_python/templates/addrmap_simulation.py.jinja

@@ -27,7 +27,7 @@ from typing import Union
 from {{ peakrdl_python_sim_lib(depth=lib_depth) }}.register import Register, MemoryRegister
 from {{ peakrdl_python_sim_lib(depth=lib_depth) }}.memory import Memory
 from {{ peakrdl_python_sim_lib(depth=lib_depth) }}.simulator import MemoryEntry
-from {{ peakrdl_python_sim_lib(depth=lib_depth) }}.field import FieldDefinition
+from {{ peakrdl_python_sim_lib(depth=lib_depth) }}.field import FieldDefinition, FieldType
 {% if asyncoutput -%}
 from {{ peakrdl_python_sim_lib(depth=lib_depth) }}.simulator import AsyncSimulator{% if legacy_block_access %}Legacy{% endif %} as Simulator{% if legacy_block_access %}Legacy{% endif %}
 {% else %}
@@ -39,7 +39,7 @@ from {{ peakrdl_python_sim_lib(depth=lib_depth) }}.simulator import Simulator{%
                                          fields=[
 
                                                 {%- for field in node.fields() -%}
-                                                FieldDefinition(high={{field.high}}, low={{field.low}}, msb={{field.msb}}, lsb={{field.lsb}}, inst_name='{{field.inst_name}}'),
+                                                FieldDefinition(high={{field.high}}, low={{field.low}}, msb={{field.msb}}, lsb={{field.lsb}}, inst_name='{{field.inst_name}}', field_type=FieldType.{{simulator_field_definition(field)}}),
                                                 {%- endfor %}
                                                 ])
 {%- endmacro %}

{peakrdl_python-2.2.0 → peakrdl_python-2.3.0}/src/peakrdl_python/templates/addrmap_simulation_tb.py.jinja

@@ -40,7 +40,7 @@ from enum import IntEnum
 {% endif %}
 
 from {{ peakrdl_python_sim_lib(depth=lib_depth) }}.register import Register,MemoryRegister
-from {{ peakrdl_python_sim_lib(depth=lib_depth) }}.field import Field
+from {{ peakrdl_python_sim_lib(depth=lib_depth) }}.field import ReadOnlyField, WriteOnlyField, ReadWriteField
 
 from ._{{top_node.inst_name}}_sim_test_base import {{top_node.inst_name}}_SimTestCase, {{top_node.inst_name}}_SimTestCase_BlockAccess
 from ._{{top_node.inst_name}}_sim_test_base import __name__ as base_name
@@ -129,7 +129,16 @@ class {{fq_block_name}}_single_access({{top_node.inst_name}}_SimTestCase): # typ
             sim_register = self.sim.register_by_full_name('{{'.'.join(node.parent.get_path_segments())}}')
             self.assertIsInstance(sim_register, (Register,MemoryRegister))
             sim_field = self.sim.field_by_full_name('{{'.'.join(node.get_path_segments())}}')
-            self.assertIsInstance(sim_field, Field)
+            {% if node.is_sw_readable and node.is_sw_writable -%}
+            if not isinstance(sim_field, ReadWriteField):
+                raise TypeError(f'should be a simulated read/write field got {type(sim_field)}')
+            {% elif node.is_sw_readable and not node.is_sw_writable -%}
+            if not isinstance(sim_field, ReadOnlyField):
+                raise TypeError(f'should be a simulated read/write field got {type(sim_field)}')
+            {% elif not node.is_sw_readable and node.is_sw_writable -%}
+            if not isinstance(sim_field, WriteOnlyField):
+                raise TypeError(f'should be a simulated read/write field got {type(sim_field)}')
+            {% endif %}
             register_read_callback = Mock()
             register_write_callback = Mock()
             field_read_callback = Mock()
@@ -178,7 +187,9 @@ class {{fq_block_name}}_single_access({{top_node.inst_name}}_SimTestCase): # typ
             sim_register.read_callback = register_read_callback
             sim_register.write_callback = register_write_callback
             sim_field.read_callback = field_read_callback
+            {% if node.is_sw_writable -%}
             sim_field.write_callback = field_write_callback
+            {% endif %}
             self.assertEqual({% if asyncoutput %}await {%endif %}self.dut.{{'.'.join(get_python_path_segments(node))}}.read(), random_field_value)
             register_write_callback.assert_not_called()
             register_read_callback.assert_called_once_with(value=random_value)
@@ -196,7 +207,9 @@ class {{fq_block_name}}_single_access({{top_node.inst_name}}_SimTestCase): # typ
             sim_register.read_callback = None
             sim_register.write_callback = None
             sim_field.read_callback = None
+            {% if node.is_sw_writable -%}
             sim_field.write_callback = None
+            {% endif %}
             {%- if 'encode' in node.list_properties() %}
             random_field_value = random_enum_reg_value(self.dut.{{'.'.join(get_python_path_segments(node))}}.enum_cls)
             random_value = (random.randrange(0, {{get_reg_max_value_hex_string(node.parent)}}+1) & {{get_field_inv_bitmask_hex_string(node)}}) | ({% if node.msb == node.high %}random_field_value.value{% else %}self._reverse_bits(value=random_field_value.value, number_bits={{node.width}}){% endif %} << {{node.low}})
@@ -245,7 +258,9 @@ class {{fq_block_name}}_single_access({{top_node.inst_name}}_SimTestCase): # typ
             # hook up the call backs
             sim_register.read_callback = None
             sim_register.write_callback = register_write_callback
+            {% if node.is_sw_readable -%}
             sim_field.read_callback = None
+            {% endif %}
             sim_field.write_callback = field_write_callback
             {%- if 'encode' in node.list_properties() %}
             random_field_value = random_enum_reg_value(self.dut.{{'.'.join(get_python_path_segments(node))}}.enum_cls)

{peakrdl_python-2.2.0 → peakrdl_python-2.3.0}/src/peakrdl_python.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: peakrdl-python
-Version: 2.2.0
+Version: 2.3.0
 Summary: Generate Python Register Access Layer (RAL) from SystemRDL
 Author: Keith Brady
 License:              GNU LESSER GENERAL PUBLIC LICENSE
@@ -191,7 +191,7 @@ Classifier: Typing :: Typed
 Requires-Python: >=3.9.2
 Description-Content-Type: text/markdown
 License-File: LICENSE
-Requires-Dist: systemrdl-compiler>=1.29.3
+Requires-Dist: systemrdl-compiler>=1.31.0
 Requires-Dist: jinja2
 Requires-Dist: typing-extensions; python_version < "3.11"
 Requires-Dist: more_itertools; python_version < "3.13"

{peakrdl_python-2.2.0 → peakrdl_python-2.3.0}/src/peakrdl_python.egg-info/SOURCES.txt

@@ -144,6 +144,7 @@ tests/testcases/name_clash.rdl
 tests/testcases/name_desc_all_levels.rdl
 tests/testcases/name_desc_option_deduplicate.rdl
 tests/testcases/name_desc_stress_test.rdl
+tests/testcases/overlapping_registers_and_fields.rdl
 tests/testcases/overridden_python_name.rdl
 tests/testcases/parametrised_readonly_and_readwrite.rdl
 tests/testcases/parametrised_top.rdl
@@ -151,7 +152,6 @@ tests/testcases/reg_name_stress.rdl
 tests/testcases/regfile_and_arrays.rdl
 tests/testcases/reserved_elements.rdl
 tests/testcases/same_but_different_enum.rdl
-tests/testcases/shared_register_issue_202
 tests/testcases/signals_definitions_at_various_levels.rdl
 tests/testcases/simple.rdl
 tests/testcases/simple.xml
@@ -170,4 +170,5 @@ tests/unit_tests/test_field.py
 tests/unit_tests/test_name_desc_export.py
 tests/unit_tests/test_optimised_reg_array.py
 tests/unit_tests/test_reg.py
+tests/unit_tests/test_sim.py
 tests/unit_tests/test_system_rdl_enum.py

{peakrdl_python-2.2.0 → peakrdl_python-2.3.0}/src/peakrdl_python.egg-info/requires.txt

@@ -1,4 +1,4 @@
-systemrdl-compiler>=1.29.3
+systemrdl-compiler>=1.31.0
 jinja2
 
 [:python_version < "3.11"]

peakrdl_python-2.3.0/tests/testcases/overlapping_registers_and_fields.rdl

@@ -0,0 +1,39 @@
+/*
+This test was introduced as part of #202 to resolve issues with overlapping registers at the
+same address. It was extended in #255
+*/
+addrmap overlapping_registers_and_fields {
+
+     reg {
+        field { fieldwidth=1; sw=rw; } enable;
+     } control ;
+
+     reg {
+        field { fieldwidth=16; sw=w; hw=r; } data;
+     } tx @ 4;
+
+     reg {
+        field { fieldwidth=16; sw=r; hw=w; } data;
+     } rx @ 4;
+
+     reg {
+        field { fieldwidth=8; sw=r; hw=w; } count;
+     } rx_fifo_fill;
+
+     reg {
+        field { fieldwidth=8; sw=r; hw=w; } count;
+     } tx_fifo_fill;
+
+     reg {
+        field {sw = r;} ro_field[15:0];
+        field {sw = w;} wo_field[15:0];
+     } overlapping_single_reg;
+
+     reg {
+        field {sw = r;} ro_field[15:0];
+        field {sw = w;} wo_field[15:0];
+        field {sw = rw;} rw_field[31:16];
+     } mixed_overlapping_and_noneoverlapping;
+
+};
+