peakrdl-python 2.0.0rc3__tar.gz → 2.0.0rc4__tar.gz

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: peakrdl-python
-Version: 2.0.0rc3
+Version: 2.0.0rc4
 Summary: Generate Python Register Access Layer (RAL) from SystemRDL
 Author: Keith Brady
 License:                     GNU GENERAL PUBLIC LICENSE
@@ -756,20 +756,20 @@ assumes that peakrdl has been installed.
    the RAL without connecting to real hardware. Enter the following code into a file:
    ```python
    """
-   An demonstration of using peakrdl-python using the accelera generic example
+   A demonstration of using peakrdl-python using the accelera generic example
    """
    # import the top level RAL class
-   from some_register_map.reg_model.some_register_map import some_register_map_cls
+   from some_register_map.reg_model import RegModel
    # import the simulator class
-   from some_register_map.sim.some_register_map import some_register_map_simulator_cls
+   from some_register_map.sim import Simulator
    
    from some_register_map.lib import NormalCallbackSet
    
    if __name__ == '__main__':
        # create an instance of the RAL with the callbacks directed at the hardware simulator
-       hw_sim = some_register_map_simulator_cls(0)
-       ral = some_register_map_cls(callbacks=NormalCallbackSet(read_callback=hw_sim.read,
-                                                               write_callback=hw_sim.write))
+       hw_sim = Simulator(0)
+       ral = RegModel(callbacks=NormalCallbackSet(read_callback=hw_sim.read,
+                                                  write_callback=hw_sim.write))
    
        # read chip ID
        chip_id_part_number = ral.chip_id_reg.part_num.read()
@@ -817,6 +817,6 @@ _Legacy Enumeration Types_ in the documentation
 Version 2.0 introduced a significant change to the process for building the register model python
 code. This change was intended to reduce the size of the generated code by only generating 
 python classes for systemRDL components that required unique classes. The previous versions were 
-more conservative and tended to generate a lot of duplicate classes. 
+more conservative and tended to generate a lot of duplicate classes.
 
 

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/README.md

@@ -38,20 +38,20 @@ assumes that peakrdl has been installed.
    the RAL without connecting to real hardware. Enter the following code into a file:
    ```python
    """
-   An demonstration of using peakrdl-python using the accelera generic example
+   A demonstration of using peakrdl-python using the accelera generic example
    """
    # import the top level RAL class
-   from some_register_map.reg_model.some_register_map import some_register_map_cls
+   from some_register_map.reg_model import RegModel
    # import the simulator class
-   from some_register_map.sim.some_register_map import some_register_map_simulator_cls
+   from some_register_map.sim import Simulator
    
    from some_register_map.lib import NormalCallbackSet
    
    if __name__ == '__main__':
        # create an instance of the RAL with the callbacks directed at the hardware simulator
-       hw_sim = some_register_map_simulator_cls(0)
-       ral = some_register_map_cls(callbacks=NormalCallbackSet(read_callback=hw_sim.read,
-                                                               write_callback=hw_sim.write))
+       hw_sim = Simulator(0)
+       ral = RegModel(callbacks=NormalCallbackSet(read_callback=hw_sim.read,
+                                                  write_callback=hw_sim.write))
    
        # read chip ID
        chip_id_part_number = ral.chip_id_reg.part_num.read()
@@ -99,6 +99,6 @@ _Legacy Enumeration Types_ in the documentation
 Version 2.0 introduced a significant change to the process for building the register model python
 code. This change was intended to reduce the size of the generated code by only generating 
 python classes for systemRDL components that required unique classes. The previous versions were 
-more conservative and tended to generate a lot of duplicate classes. 
+more conservative and tended to generate a lot of duplicate classes.
 
 

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/docs/api_components.rst

@@ -18,22 +18,22 @@ Base Classes
 Address Maps
 ============
 
-.. autoclass:: peakrdl_python.lib.base.AddressMap
+.. autoclass:: peakrdl_python.lib.sections.AddressMap
     :members:
     :inherited-members:
 
-.. autoclass:: peakrdl_python.lib.base.AddressMapArray
+.. autoclass:: peakrdl_python.lib.sections.AddressMapArray
     :members:
     :inherited-members:
 
 Register Files
 ==============
 
-.. autoclass:: peakrdl_python.lib.base.RegFile
+.. autoclass:: peakrdl_python.lib.sections.RegFile
     :members:
     :inherited-members:
 
-.. autoclass:: peakrdl_python.lib.base.RegFileArray
+.. autoclass:: peakrdl_python.lib.sections.RegFileArray
     :members:
     :inherited-members:
 

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/docs/generated_package.rst

@@ -24,6 +24,22 @@ In the folder structure above:
 - ``lib`` - This is a package of base classes used by the register access layer (The copy of this can be skipped, see :ref:`skipping-lib-copy`)
 - ``sim_lib`` - This is a package of base classes used by the register access layer simulator (The copy of this can be skipped, see :ref:`skipping-lib-copy`)
 
+.. versionchanged:: 2.0.0
+
+    The ``reg_model`` was changed in version 2.0.0 to split it out into multiple modules rather
+    than building the whole register model in a single python module. This helps avoid
+    excessively large files which helps speed up the generation and loading time.
+
+Top Level Classes
+-----------------
+
+.. versionchanged:: 2.0.0
+
+    A new class aliases were added to the ``reg_model`` and ``sim`` packages to allow the register
+    model and simulator to be imported more easily. See the example below using ``RegModel`` and
+    ``Simulator``.
+
+
 Running the Unit Tests
 ======================
 

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/example/array_access/demo_array_access.py

@@ -1,17 +1,17 @@
 """
 A demonstration of array access for peakrdl-python
 """
-from array_access.reg_model.array_access import array_access_cls
-from array_access.sim.array_access import array_access_simulator_cls
+from array_access.reg_model import RegModel
+from array_access.sim import Simulator
 from array_access.lib.callbacks import NormalCallbackSet
 
 if __name__ == '__main__':
 
     # setup the simple simulator
-    sim = array_access_simulator_cls(0)
+    sim = Simulator(0)
 
     # create an instance of the class
-    regmodel = array_access_cls(callbacks=NormalCallbackSet(read_callback=sim.read))
+    regmodel = RegModel(callbacks=NormalCallbackSet(read_callback=sim.read))
 
     # access a entry in the 1D array
     print(regmodel.reg_array_1D[0].field_a.read())

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/example/enumerated_fields/demo_enumerated_fields.py

@@ -3,15 +3,15 @@ A demonstration of using enumeration for peakrdl-python
 """
 from enumerated_fields.lib import NormalCallbackSet
 
-from enumerated_fields.reg_model.enumerated_fields import enumerated_fields_cls as GPIO
-from enumerated_fields.sim.enumerated_fields import enumerated_fields_simulator_cls as HardwareSimulator
+from enumerated_fields.reg_model import RegModel
+from enumerated_fields.sim import Simulator
 
 if __name__ == '__main__':
 
     # create an instance of the hardware simulator
-    hw = HardwareSimulator(0)
+    hw = Simulator(0)
     # create an instance of the RAL with the callbacks directed at the hardware simulator
-    gpio = GPIO(callbacks=NormalCallbackSet(read_callback=hw.read, write_callback=hw.write))
+    gpio = RegModel(callbacks=NormalCallbackSet(read_callback=hw.read, write_callback=hw.write))
 
     # get the field values
     for field in gpio.gpio_strength.readable_fields:

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/example/optimised_access/demo_optimised_access.py

@@ -1,8 +1,8 @@
 """
 PeakRDL Python example to show the different methods to access the fields of a register
 """
-from optimised_access.reg_model.optimised_access import optimised_access_cls
-from optimised_access.sim.optimised_access import optimised_access_simulator_cls
+from optimised_access.reg_model import RegModel
+from optimised_access.sim import Simulator
 
 from optimised_access.lib import NormalCallbackSet
 
@@ -11,8 +11,8 @@ if __name__ == '__main__':
 
     # create an instance of the address map with the simulated callback necessary to demonstrate
     # the example
-    sim = optimised_access_simulator_cls(0)
-    dut = optimised_access_cls(callbacks=NormalCallbackSet(read_callback=sim.read,
+    sim = Simulator(0)
+    dut = RegModel(callbacks=NormalCallbackSet(read_callback=sim.read,
                                                            write_callback=sim.write))
 
     # configure the GPIO 0 and GPIO 1 without affecting the state of the GPIO 2 and GPIO 3

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/example/optimised_access/demo_optimised_array_access.py

@@ -1,8 +1,8 @@
 """
 PeakRDL Python example to show the different methods to access the a register array
 """
-from optimised_array_access.reg_model.optimised_array_access import optimised_array_access_cls
-from optimised_array_access.sim.optimised_array_access import optimised_array_access_simulator_cls
+from optimised_array_access.reg_model import RegModel
+from optimised_array_access.sim import Simulator
 
 from optimised_array_access.lib import NormalCallbackSet
 
@@ -12,8 +12,8 @@ if __name__ == '__main__':
 
     # create an instance of the address map with the simulated callback necessary to demonstrate
     # the example
-    sim = optimised_array_access_simulator_cls(0)
-    dut = optimised_array_access_cls(callbacks=NormalCallbackSet(read_block_callback=sim.read_block,
+    sim = Simulator(0)
+    dut = RegModel(callbacks=NormalCallbackSet(read_block_callback=sim.read_block,
                                                                  write_block_callback=sim.write_block,
                                                                  read_callback=sim.read,
                                                                  write_callback=sim.write))

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/example/overridden_names/demo_over_ridden_names.py

@@ -6,14 +6,14 @@ field_a respectively. However the python_inst_name has been used on change the n
 peakrdl-python register model to overridden_reg_a and overridden_field_a respectively
 
 """
-from over_ridden_names.reg_model.over_ridden_names import over_ridden_names_cls
+from over_ridden_names.reg_model import RegModel
 from over_ridden_names.lib import NormalCallbackSet
 from over_ridden_names.sim_lib.dummy_callbacks import dummy_read
 
 if __name__ == '__main__':
 
     # create an instance of the class
-    over_ridden_names = over_ridden_names_cls(callbacks=NormalCallbackSet(read_callback=dummy_read))
+    over_ridden_names = RegModel(callbacks=NormalCallbackSet(read_callback=dummy_read))
 
     # access the field value directly
     print(over_ridden_names.overridden_reg_a.overridden_field_a.read())

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/example/simulating_callbacks/flashing_the_LED.py

@@ -4,11 +4,11 @@ A demonstration of extended simulator behaviour in peakrdl-python
 import tkinter
 import tkinter as tk
 
-from mychip.reg_model.mychip import mychip_cls
-from mychip.sim.mychip import mychip_simulator_cls
+from mychip.reg_model import RegModel
+from mychip.sim import Simulator
 from mychip.lib import NormalCallbackSet
 
-class ChipSim(mychip_simulator_cls):
+class ChipSim(Simulator):
 
     def __init__(self):
 
@@ -54,7 +54,7 @@ class ChipSim(mychip_simulator_cls):
             self.LED.itemconfig(self.LED_inner, fill='black')
 
 
-def timer_event(chip: mychip_cls, sim_kt_root: tkinter.Tk) -> None:
+def timer_event(chip: RegModel, sim_kt_root: tkinter.Tk) -> None:
     """
     timer event which will invert the state of the LED and then set the timer event to run
     in 2s
@@ -91,7 +91,7 @@ if __name__ == '__main__':
                                   write_callback=chip_simulator.write)
 
     # created an instance of the register model and connect the callbacks to the simulator
-    mychip = mychip_cls(callbacks=callbacks)
+    mychip = RegModel(callbacks=callbacks)
 
     # configure the GPIO.PIN_0 as an output
     mychip.GPIO.GPIO_dir.PIN_0.write(mychip.GPIO.GPIO_dir.PIN_0.enum_cls.DIR_OUT)

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/example/tranversing_address_map/dumping_register_state_to_json_file.py

@@ -4,8 +4,8 @@ A demonstration of traversing the register model generated with peakrdl-python
 import json
 from typing import Union
 
-from chip_with_registers.reg_model.chip_with_registers import chip_with_registers_cls
-from chip_with_registers.sim.chip_with_registers import chip_with_registers_simulator_cls
+from chip_with_registers.reg_model import RegModel
+from chip_with_registers.sim import Simulator
 
 from chip_with_registers.lib import NormalCallbackSet, RegReadOnly, RegReadWrite, \
     MemoryReadOnly, MemoryReadWrite, RegFile, AddressMap, RegReadOnlyArray, RegReadWriteArray, \
@@ -139,8 +139,8 @@ if __name__ == '__main__':
 
     # create an instance of the address map with the simulated callback necessary to demonstrate
     # the example
-    sim = chip_with_registers_simulator_cls(0)
-    dut = chip_with_registers_cls(callbacks=NormalCallbackSet(read_callback=sim.read,
+    sim = Simulator(0)
+    dut = RegModel(callbacks=NormalCallbackSet(read_callback=sim.read,
                                                               write_callback=sim.write))
 
     # generate an instance of the RegisterDumper and write the registers to a file

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/example/tranversing_address_map/reseting_registers.py

@@ -3,14 +3,14 @@ A demonstration of traversing the register model generated with peakrdl-python
 """
 from typing import Union
 
-from chip_with_registers.reg_model.chip_with_registers import chip_with_registers_cls
-from chip_with_registers.sim.chip_with_registers import chip_with_registers_simulator_cls
+from chip_with_registers.reg_model import RegModel
+from chip_with_registers.sim import Simulator
 
 from chip_with_registers.lib import NormalCallbackSet,  RegWriteOnly, RegReadWrite, \
     MemoryWriteOnly, MemoryReadWrite, RegFile, AddressMap
 
 
-class chip_with_registers_cls_with_reset(chip_with_registers_cls):
+class chip_with_registers_cls_with_reset(RegModel):
     """
     Extends the chip_with_registers_cls class adding methods to reset all the registers to
     their defined reset values
@@ -101,7 +101,7 @@ if __name__ == '__main__':
 
     # create an instance of the address map with the simulated callback necessary to demonstrate
     # the example
-    sim = chip_with_registers_simulator_cls(0)
+    sim = Simulator(0)
     dut = chip_with_registers_cls_with_reset(callbacks=NormalCallbackSet(read_callback=sim.read,
                                                                          write_callback=sim.write))
 

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/example/tranversing_address_map/writing_register_state_from_json_file.py

@@ -4,8 +4,8 @@ A demonstration of traversing the register model generated with peakrdl-python
 import json
 from typing import Union, Dict, List
 
-from chip_with_registers.reg_model.chip_with_registers import chip_with_registers_cls
-from chip_with_registers.sim.chip_with_registers import chip_with_registers_simulator_cls
+from chip_with_registers.reg_model import RegModel
+from chip_with_registers.sim import Simulator
 
 from chip_with_registers.lib import NormalCallbackSet, RegWriteOnly, RegReadWrite, \
     MemoryWriteOnly, MemoryReadWrite, RegFile, AddressMap, RegWriteOnlyArray, RegReadWriteArray, \
@@ -216,9 +216,9 @@ if __name__ == '__main__':
 
     # create an instance of the address map with the simulated callback necessary to demonstrate
     # the example
-    sim = chip_with_registers_simulator_cls(0)
-    dut = chip_with_registers_cls(callbacks=NormalCallbackSet(read_callback=sim.read,
-                                                              write_callback=sim.write))
+    sim = Simulator(0)
+    dut = RegModel(callbacks=NormalCallbackSet(read_callback=sim.read,
+                                               write_callback=sim.write))
 
     # generate an instance of the RegisterWriter and write the template JSON file for registers
     # in the design. In the template all the values are set to null (None in python)

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/example/user_defined_properties/demo_user_defined_properties.py

@@ -1,15 +1,15 @@
 """
 A demonstration of user defined properties generated with peakrdl-python
 """
-from user_defined_property.reg_model.user_defined_property import user_defined_property_cls
+from user_defined_property.reg_model import RegModel
 from user_defined_property.sim_lib.dummy_callbacks import dummy_read, dummy_write
 from user_defined_property.lib.callbacks import NormalCallbackSet
 
 if __name__ == '__main__':
 
     # create an instance of the class
-    regmodel = user_defined_property_cls(callbacks=NormalCallbackSet(read_callback=dummy_read,
-                                                                     write_callback=dummy_write))
+    regmodel = RegModel(callbacks=NormalCallbackSet(read_callback=dummy_read,
+                                                    write_callback=dummy_write))
 
     # loop through the fields in the register access model and print out the value of the
     # component_usage property

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/example/why_ral/with_hal.py

@@ -3,8 +3,8 @@ An example to turn on GPIO 0 with a Hardware Abstaction Layer, built on top of t
 Register Abstraction Layer (RAL)
 """
 from enum import Enum, auto
-from gpio.reg_model.gpio import gpio_cls as GPIO
-from gpio.sim.gpio import gpio_simulator_cls as HardwareSimulator
+from gpio.reg_model import RegModel as GPIO
+from gpio.sim import Simulator as HardwareSimulator
 
 class GPIODir(Enum):
     """

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/example/why_ral/with_ral.py

@@ -1,8 +1,8 @@
 """
 An example to turn on GPIO 0 with the RAL, with using peakrdl-python
 """
-from gpio.reg_model.gpio import gpio_cls as GPIO
-from gpio.sim.gpio import gpio_simulator_cls as HardwareSimulator
+from gpio.reg_model import RegModel as GPIO
+from gpio.sim import Simulator as HardwareSimulator
 
 from gpio.lib import NormalCallbackSet
 

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/generate_and_test.py

@@ -175,9 +175,6 @@ if __name__ == '__main__':
         else:
             raise(RuntimeError('not a list'))
 
-    reg_model_class_name = CommandLineArgs.root_node +'_cls'
-    sim_class_name = CommandLineArgs.root_node + '_simulator_cls'
-
     rdlc.compile_file(CommandLineArgs.root_RDL_file)
     spec = rdlc.elaborate(top_def_name=CommandLineArgs.root_node).top
 
@@ -216,14 +213,14 @@ if __name__ == '__main__':
             cov.start()
 
         reg_model_module = __import__( 'generate_and_test_output.' +
-            CommandLineArgs.root_node + '.reg_model.' + CommandLineArgs.root_node,
-            globals(), locals(), [reg_model_class_name], 0)
+            CommandLineArgs.root_node + '.reg_model',
+            globals(), locals(), ['RegModel'], 0)
         sim_module = __import__( 'generate_and_test_output.' +
-            CommandLineArgs.root_node + '.sim.' + CommandLineArgs.root_node,
-            globals(), locals(), [sim_class_name], 0)
+            CommandLineArgs.root_node + '.sim',
+            globals(), locals(), ['Simulator'], 0)
 
 
-        dut_cls = getattr(reg_model_module, reg_model_class_name)
+        dut_cls = getattr(reg_model_module, 'RegModel')
 
         if CommandLineArgs.copy_libraries:
             peakrdl_python_package = __import__('generate_and_test_output.' + CommandLineArgs.root_node + '.lib',
@@ -243,7 +240,7 @@ if __name__ == '__main__':
             else:
                 callbackset_cls = getattr(peakrdl_python_package, 'NormalCallbackSet')
 
-        sim_cls = getattr(sim_module, sim_class_name)
+        sim_cls = getattr(sim_module, 'Simulator')
         sim = sim_cls(address=0)
         dut = dut_cls(callbacks=callbackset_cls(read_callback=sim.read,
                                                 write_callback=sim.write))

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/src/peakrdl_python/__about__.py

@@ -17,4 +17,4 @@ along with this program.  If not, see <https://www.gnu.org/licenses/>.
 
 Variables that describes the peakrdl-python Package
 """
-__version__ = "2.0.0rc3"
+__version__ = "2.0.0rc4"

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/src/peakrdl_python/__peakrdl__.py

@@ -28,6 +28,10 @@ from peakrdl.config import schema  # type: ignore[import]
 #pylint: enable=no-name-in-module,import-error
 
 from .exporter import PythonExporter
+from .exporter import DEFAULT_REGISTER_CLASS_PER_GENERATED_FILE
+from .exporter import DEFAULT_FIELD_CLASS_PER_GENERATED_FILE
+from .exporter import DEFAULT_ENUM_FIELD_CLASS_PER_GENERATED_FILE
+from .exporter import DEFAULT_MEMORY_CLASS_PER_GENERATED_FILE
 from .compiler_udp import PythonHideUDP, PythonInstNameUDP
 
 if TYPE_CHECKING:
@@ -99,6 +103,38 @@ class Exporter(ExporterSubcommandPlugin):
                                     'attributes as properties of the class that is built. Setting '
                                     'this will skip this reducign the size of the python code '
                                     'generated')
+        arg_group.add_argument('--register_class_per_generated_file',
+                               dest='register_class_per_generated_file',
+                               type=int,
+                               default=DEFAULT_REGISTER_CLASS_PER_GENERATED_FILE,
+                               help='Number of register class definitions to put in each python '
+                                    'module of the generated code. Make sure this is set to '
+                                    'ensure the file does not get too big otherwise the '
+                                    'generation and loading is slow')
+        arg_group.add_argument('--field_class_per_generated_file',
+                               dest='field_class_per_generated_file',
+                               type=int,
+                               default=DEFAULT_FIELD_CLASS_PER_GENERATED_FILE,
+                               help='Number of field class definitions to put in each python '
+                                    'module of the generated code. Make sure this is set to '
+                                    'ensure the file does not get too big otherwise the '
+                                    'generation and loading is slow')
+        arg_group.add_argument('--enum_field_class_per_generated_file',
+                               dest='enum_field_class_per_generated_file',
+                               type=int,
+                               default=DEFAULT_ENUM_FIELD_CLASS_PER_GENERATED_FILE,
+                               help='Number of enumerated field class definitions to put in each '
+                                    'python module of the generated code. Make sure this is set '
+                                    'to ensure the file does not get too big otherwise the '
+                                    'generation and loading is slow')
+        arg_group.add_argument('--memory_class_per_generated_file',
+                               dest='memory_class_per_generated_file',
+                               type=int,
+                               default=DEFAULT_MEMORY_CLASS_PER_GENERATED_FILE,
+                               help='Number of memory class definitions to put in each '
+                                    'python module of the generated code. Make sure this is set '
+                                    'to ensure the file does not get too big otherwise the '
+                                    'generation and loading is slow')
 
     def do_export(self, top_node: 'AddrmapNode', options: 'argparse.Namespace') -> None:
         """
@@ -133,5 +169,10 @@ class Exporter(ExporterSubcommandPlugin):
             hidden_inst_name_regex=options.hide_regex,
             skip_library_copy=options.skip_library_copy,
             legacy_enum_type=options.legacy_enum_type,
-            skip_systemrdl_name_and_desc_properties=options.skip_systemrdl_name_and_desc_properties
+            skip_systemrdl_name_and_desc_properties=
+                options.skip_systemrdl_name_and_desc_properties,
+            register_class_per_generated_file=options.register_class_per_generated_file,
+            field_class_per_generated_file=options.field_class_per_generated_file,
+            enum_field_class_per_generated_file=options.enum_field_class_per_generated_file,
+            memory_class_per_generated_file=options.memory_class_per_generated_file
         )

{peakrdl_python-2.0.0rc3 → peakrdl_python-2.0.0rc4}/src/peakrdl_python/_deploy_package.py

@@ -131,17 +131,20 @@ class _GeneratedRegModelRegistersPackage(PythonPackage):
         self.fields.create_empty_package(cleanup=cleanup)
         self.field_enum.create_empty_package(cleanup=cleanup)
 
+
 class _GeneratedRegModelPackage(PythonPackage):
 
     def __init__(self, path: Path):
         super().__init__(path=path)
 
-        self.registers = _GeneratedRegModelRegistersPackage(self.child_path('registers'))
+        self.registers = _GeneratedRegModelRegistersPackage(self.child_path('_registers'))
+        self.memories = self.child_package('_memories')
 
     def create_empty_package(self, cleanup: bool) -> None:
         # make the folder for this package and populate the empty __init__.py
         super().create_empty_package(cleanup=cleanup)
         self.registers.create_empty_package(cleanup=cleanup)
+        self.memories.create_empty_package(cleanup=cleanup)
 
 
 class GeneratedPackage(PythonPackage):