peakrdl-python 1.2.1rc4__tar.gz → 1.3.0__tar.gz

{peakrdl_python-1.2.1rc4 → peakrdl_python-1.3.0}/.github/workflows/action.yaml

@@ -144,6 +144,8 @@ jobs:
           python -m generate_and_test --RDL_source_file tests/testcases/user_defined_properties.rdl --root_node user_defined_properties --udp bool_property_to_include enum_property_to_include int_property_to_include str_property_to_include struct_property_to_include double_layer_struct_property_to_include
 
           python -m generate_and_test --RDL_source_file tests/testcases/reserved_elements.rdl --root_node reserved_elements --hide_regex "(?:[\w_\[\]]+\.)+RSVD"
+          
+          python -m generate_and_test --RDL_source_file tests/testcases/name_desc_all_levels.rdl --root_node name_desc_all_levels --skip_systemrdl_name_and_desc_properties
 
   peakrdl_integration:
     needs:

{peakrdl_python-1.2.1rc4 → peakrdl_python-1.3.0}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: peakrdl-python
-Version: 1.2.1rc4
+Version: 1.3.0
 Summary: Generate Python Register Access Layer (RAL) from SystemRDL
 Author: Keith Brady
 License:                     GNU GENERAL PUBLIC LICENSE

{peakrdl_python-1.2.1rc4 → peakrdl_python-1.3.0}/docs/generated_package.rst

@@ -411,7 +411,7 @@ User Defined Properties are not automatically included they must be specified, a
 
 .. code-block:: bash
 
-   peakrdl python chip_with_registers.rdl -o chip_with_registers
+   peakrdl python user_defined_properties.rdl -o . --udp component_usage
 
 The user defined properties are stored in a ``udp`` property of all component in the generated
 register access and can be accessed as follows:

{peakrdl_python-1.2.1rc4 → peakrdl_python-1.3.0}/example/user_defined_properties/demo_user_defined_properties.py

@@ -8,7 +8,7 @@ if __name__ == '__main__':
     regmodel = user_defined_property_cls(callbacks=NormalCallbackSet(read_callback=dummy_read,
                                                                      write_callback=dummy_write))
 
-    # loop through the the fields in the register access model and print out the value of the
+    # loop through the fields in the register access model and print out the value of the
     # component_usage property
     for field in regmodel.control_register.readable_fields:
         field_usage = field.udp['component_usage']

{peakrdl_python-1.2.1rc4 → peakrdl_python-1.3.0}/generate_and_test.py

@@ -96,6 +96,13 @@ CommandLineParser.add_argument('--legacy_enum_type', action='store_true',
                                help='peakrdl python has ways to define field encoding as enums a '
                                     'a new method and an old method based on IntEnum. Setting '
                                     'this to true will restore the old behaviour')
+CommandLineParser.add_argument('--skip_systemrdl_name_and_desc_properties',
+                               action='store_true',
+                               dest='skip_systemrdl_name_and_desc_properties',
+                               help='peakrdl python includes the system RDL name and desc '
+                                    'attributes as properties of the class that is built. Setting '
+                                    'this will skip this reducign the size of the python code '
+                                    'generated')
 
 
 def build_logging_cong(logfilepath:str):
@@ -183,14 +190,17 @@ if __name__ == '__main__':
 
     exporter = PythonExporter()
     start_time = time.time()
-    exporter.export(node=spec, path=str(CommandLineArgs.output_path / 'generate_and_test_output'),
-                    asyncoutput=CommandLineArgs.asyncoutput,
-                    delete_existing_package_content=not CommandLineArgs.suppress_cleanup,
-                    skip_library_copy=not CommandLineArgs.copy_libraries,
-                    legacy_block_access=CommandLineArgs.legacy_block_access,
-                    user_defined_properties_to_include=CommandLineArgs.udp,
-                    hidden_inst_name_regex=CommandLineArgs.hide_regex,
-                    legacy_enum_type=CommandLineArgs.legacy_enum_type)
+    exporter.export(
+        node=spec, path=str(CommandLineArgs.output_path / 'generate_and_test_output'),
+        asyncoutput=CommandLineArgs.asyncoutput,
+        delete_existing_package_content=not CommandLineArgs.suppress_cleanup,
+        skip_library_copy=not CommandLineArgs.copy_libraries,
+        legacy_block_access=CommandLineArgs.legacy_block_access,
+        user_defined_properties_to_include=CommandLineArgs.udp,
+        hidden_inst_name_regex=CommandLineArgs.hide_regex,
+        legacy_enum_type=CommandLineArgs.legacy_enum_type,
+        skip_systemrdl_name_and_desc_properties=
+        CommandLineArgs.skip_systemrdl_name_and_desc_properties)
     print(f'generation time {time.time() - start_time}s')
 
     if not CommandLineArgs.export_only:

{peakrdl_python-1.2.1rc4 → peakrdl_python-1.3.0}/src/peakrdl_python/__about__.py

@@ -17,4 +17,4 @@ along with this program.  If not, see <https://www.gnu.org/licenses/>.
 
 Variables that describes the peakrdl-python Package
 """
-__version__ = "1.2.1rc4"
+__version__ = "1.3.0"

{peakrdl_python-1.2.1rc4 → peakrdl_python-1.3.0}/src/peakrdl_python/__peakrdl__.py

@@ -93,6 +93,12 @@ class Exporter(ExporterSubcommandPlugin):
                                help='peakrdl python has two ways to define field encoding as '
                                      'enums new method and an old method based on IntEnum. '
                                      'Setting this to true will restore the old behaviour')
+        arg_group.add_argument('--skip_systemrdl_name_and_desc_properties', action='store_true',
+                               dest='skip_systemrdl_name_and_desc_properties',
+                               help='peakrdl python includes the system RDL name and desc '
+                                    'attributes as properties of the class that is built. Setting '
+                                    'this will skip this reducign the size of the python code '
+                                    'generated')
 
     def do_export(self, top_node: 'AddrmapNode', options: 'argparse.Namespace') -> None:
         """
@@ -126,5 +132,6 @@ class Exporter(ExporterSubcommandPlugin):
             user_defined_properties_to_include=options.udp,
             hidden_inst_name_regex=options.hide_regex,
             skip_library_copy=options.skip_library_copy,
-            legacy_enum_type=options.legacy_enum_type
+            legacy_enum_type=options.legacy_enum_type,
+            skip_systemrdl_name_and_desc_properties=options.skip_systemrdl_name_and_desc_properties
         )

{peakrdl_python-1.2.1rc4 → peakrdl_python-1.3.0}/src/peakrdl_python/exporter.py

@@ -300,7 +300,8 @@ class PythonExporter:
                            legacy_block_access: bool,
                            udp_to_include: Optional[list[str]],
                            hide_node_func: HideNodeCallback,
-                           legacy_enum_type: bool) -> None:
+                           legacy_enum_type: bool,
+                           skip_systemrdl_name_and_desc_properties: bool) -> None:
 
         def visible_nonsignal_node(node: Node) -> int:
             count = 0
@@ -361,7 +362,8 @@ class PythonExporter:
                                                   udp_to_include=udp_to_include),
             'hide_node_func': hide_node_func,
             'visible_nonsignal_node' : visible_nonsignal_node,
-            'legacy_enum_type': legacy_enum_type
+            'legacy_enum_type': legacy_enum_type,
+            'skip_systemrdl_name_and_desc_properties': skip_systemrdl_name_and_desc_properties
         }
         if legacy_block_access is True:
             context['get_array_typecode'] = get_array_typecode
@@ -380,8 +382,31 @@ class PythonExporter:
                            asyncoutput: bool,
                            legacy_block_access: bool) -> None:
 
+        # as a result of issue 202, where two registers existed at that same address,
+        # rather than iterating through the registers within the Jinja template
+        # we iterate through them in in advance so that cases of two registers at that same
+        # address can be identified
+        reg_dict:dict[int, Union[list[RegNode],RegNode]] = {}
+        for node in filter(lambda x : isinstance(x, RegNode),  top_block.descendants(unroll=True)):
+            if not isinstance(node, RegNode):
+                raise TypeError(f'node should be a register, got {type(node)}')
+            reg_addr = node.absolute_address
+            if reg_addr in reg_dict:
+                existing_entry = reg_dict[reg_addr]
+                # if the entry is already list simply append to it
+                if isinstance(existing_entry, list):
+                    existing_entry.append(node)
+                elif isinstance(existing_entry, RegNode):
+                    reg_dict[reg_addr] = [existing_entry, node]
+                else:
+                    raise TypeError(f'exiting entry of unexpected type: {type(existing_entry)}')
+            else:
+                reg_dict[reg_addr] = node
+
+
         context = {
             'top_node': top_block,
+            'reg_dict': reg_dict,
             'systemrdlRegNode': RegNode,
             'systemrdlMemNode': MemNode,
             'isinstance': isinstance,
@@ -389,6 +414,7 @@ class PythonExporter:
             'skip_lib_copy': skip_lib_copy,
             'version': __version__,
             'legacy_block_access': legacy_block_access,
+            'list': list
         }
 
         context.update(self.user_template_context)
@@ -472,19 +498,10 @@ class PythonExporter:
                        legacy_block_access: bool,
                        udp_to_include: Optional[list[str]],
                        hide_node_func: HideNodeCallback,
-                       legacy_enum_type: bool
+                       legacy_enum_type: bool,
+                       skip_systemrdl_name_and_desc_properties: bool,
                        ) -> None:
-        """
-
-        Args:
-            top_block:
-            package:
-            asyncoutput:
-            legacy_block_access:
-
-        Returns:
 
-        """
         # pylint: disable=too-many-locals
 
         blocks = AddressMaps(hide_node_callback=hide_node_func)
@@ -557,7 +574,8 @@ class PythonExporter:
                     self._get_dependent_property_enum(node=top_block,
                                                       udp_to_include=udp_to_include),
                 'hide_node_func': hide_node_func,
-                'legacy_enum_type': legacy_enum_type
+                'legacy_enum_type': legacy_enum_type,
+                'skip_systemrdl_name_and_desc_properties': skip_systemrdl_name_and_desc_properties
             }
 
             self.__stream_jinja_template(template_name="addrmap_tb.py.jinja",
@@ -597,7 +615,8 @@ class PythonExporter:
                show_hidden: bool = False,
                user_defined_properties_to_include: Optional[list[str]] = None,
                hidden_inst_name_regex: Optional[str] = None,
-               legacy_enum_type: bool = True) -> str:
+               legacy_enum_type: bool = True,
+               skip_systemrdl_name_and_desc_properties: bool = False) -> str:
         """
         Generated Python Code and Testbench
 
@@ -636,7 +655,11 @@ class PythonExporter:
             legacy_enum_type: version 1.2 introduced a new Enum type that allows system
                               rdl ``name`` and ``desc`` properties on field encoding
                               to be included. The legacy mode uses python IntEnum.
-
+            skip_systemrdl_name_and_desc_properties (bool) : version 1.2 introduced new properties
+                                                             that include the systemRDL name and
+                                                             desc as properties of the built
+                                                             python. Setting this option to
+                                                             ``True`` will exclude them.
 
         Returns:
             modules that have been exported:
@@ -687,12 +710,14 @@ class PythonExporter:
 
         self._build_node_type_table(top_block, hide_node_func)
 
-        self.__export_reg_model(top_block=top_block, package=package, asyncoutput=asyncoutput,
-                                skip_lib_copy=skip_library_copy,
-                                legacy_block_access=legacy_block_access,
-                                udp_to_include=user_defined_properties_to_include,
-                                hide_node_func=hide_node_func,
-                                legacy_enum_type=legacy_enum_type)
+        self.__export_reg_model(
+            top_block=top_block, package=package, asyncoutput=asyncoutput,
+            skip_lib_copy=skip_library_copy,
+            legacy_block_access=legacy_block_access,
+            udp_to_include=user_defined_properties_to_include,
+            hide_node_func=hide_node_func,
+            legacy_enum_type=legacy_enum_type,
+            skip_systemrdl_name_and_desc_properties=skip_systemrdl_name_and_desc_properties)
 
         self.__export_simulator(top_block=top_block, package=package, asyncoutput=asyncoutput,
                                 skip_lib_copy=skip_library_copy,
@@ -709,12 +734,14 @@ class PythonExporter:
                                      legacy_block_access=legacy_block_access,
                                      legacy_enum_type=legacy_enum_type)
             # export the tests themselves, these are broken down to one file per addressmap
-            self.__export_tests(top_block=top_block, package=package, asyncoutput=asyncoutput,
-                                skip_lib_copy=skip_library_copy,
-                                legacy_block_access=legacy_block_access,
-                                udp_to_include=user_defined_properties_to_include,
-                                hide_node_func=hide_node_func,
-                                legacy_enum_type=legacy_enum_type)
+            self.__export_tests(
+                top_block=top_block, package=package, asyncoutput=asyncoutput,
+                skip_lib_copy=skip_library_copy,
+                legacy_block_access=legacy_block_access,
+                udp_to_include=user_defined_properties_to_include,
+                hide_node_func=hide_node_func,
+                legacy_enum_type=legacy_enum_type,
+                skip_systemrdl_name_and_desc_properties=skip_systemrdl_name_and_desc_properties)
 
         return top_block.inst_name
 

{peakrdl_python-1.2.1rc4 → peakrdl_python-1.3.0}/src/peakrdl_python/sim_lib/simulator.py

@@ -81,10 +81,11 @@ class BaseSimulator(ABC):
         self.address = address
 
     @abstractmethod
-    def _build_registers(self) -> dict[int, Union[MemoryRegister, Register]]:
+    def _build_registers(self) -> dict[int, Union[list[Union[MemoryRegister, Register]],
+                                                  Union[MemoryRegister, Register]]]:
         """
-        populate the register structure, this method is intended to written by the generated code
-        based on then design
+        populate the register structure, this method is intended to implemented by the generated
+        code based on then design
         """
 
     @abstractmethod
@@ -145,7 +146,15 @@ class BaseSimulator(ABC):
         # see if the address is a register first this ensures that registers in memories are
         # accessed directly
         if addr in self._registers:
-            return self._registers[addr].read()
+            addr_entry = self._registers[addr]
+            if isinstance(addr_entry, list):
+                # search the list for a readable register
+                for inner_reg in addr_entry:
+                    # pylint: disable-next=protected-access
+                    if inner_reg._readable:
+                        return inner_reg.read()
+            else:
+                return addr_entry.read()
 
         potential_memory = self.memory_for_address(address=addr)
         if potential_memory is not None:
@@ -164,7 +173,14 @@ class BaseSimulator(ABC):
         # see if the address is a register first this ensures that registers in memories are
         # accessed directly
         if addr in self._registers:
-            self._registers[addr].write(data)
+            addr_entry = self._registers[addr]
+            if isinstance(addr_entry, list):
+                for inner_reg in addr_entry:
+                    # pylint: disable-next=protected-access
+                    if inner_reg._writable:
+                        inner_reg.write(data)
+            else:
+                addr_entry.write(data)
         else:
             potential_memory = self.memory_for_address(address=addr)
             if potential_memory is not None:
@@ -244,8 +260,13 @@ class BaseSimulator(ABC):
 
         """
         for reg in self._registers.values():
-            if reg.full_inst_name == name:
-                return reg
+            if isinstance(reg, list):
+                for reg_list_entry in reg:
+                    if reg_list_entry.full_inst_name == name:
+                        return reg_list_entry
+            else:
+                if reg.full_inst_name == name:
+                    return reg
 
         raise ValueError(f'register name not matched: {name}')
 
@@ -260,9 +281,15 @@ class BaseSimulator(ABC):
 
         """
         for reg in self._registers.values():
-            for field in reg.fields:
-                if field.full_inst_name == name:
-                    return field
+            if isinstance(reg, list):
+                for reg_list_entry in reg:
+                    for field in reg_list_entry.fields:
+                        if field.full_inst_name == name:
+                            return field
+            else:
+                for field in reg.fields:
+                    if field.full_inst_name == name:
+                        return field
 
         raise ValueError(f'field name not matched: {name}')
 
@@ -282,12 +309,21 @@ class BaseSimulator(ABC):
                 return mem.memory
 
         for reg in self._registers.values():
-            if reg.full_inst_name == name:
-                return reg
-
-            for field in reg.fields:
-                if field.full_inst_name == name:
-                    return field
+            if isinstance(reg, list):
+                for reg_list_entry in reg:
+                    if reg_list_entry.full_inst_name == name:
+                        return reg_list_entry
+
+                    for field in reg_list_entry.fields:
+                        if field.full_inst_name == name:
+                            return field
+            else:
+                if reg.full_inst_name == name:
+                    return reg
+
+                for field in reg.fields:
+                    if field.full_inst_name == name:
+                        return field
 
         raise ValueError(f'node name not matched: {name}')
 

{peakrdl_python-1.2.1rc4 → peakrdl_python-1.3.0}/src/peakrdl_python/templates/addrmap_tb.py.jinja

@@ -96,10 +96,14 @@ class {{fq_block_name}}_single_access({{top_node.inst_name}}_TestCase): # type:
         """
         {% for node in owned_elements.nodes -%}
         with self.subTest(msg='node: {{'.'.join(node.get_path_segments())}}'):
-            {% if node.get_property('name', default=None) is none %}
-            self.assertIsNone(self.dut.{{'.'.join(get_python_path_segments(node))}}.rdl_name)  # type: ignore[union-attr]
+            {% if skip_systemrdl_name_and_desc_properties %}
+                self.assertIsNone(self.dut.{{'.'.join(get_python_path_segments(node))}}.rdl_name)  # type: ignore[union-attr]
             {% else %}
+                {% if node.get_property('name', default=None) is none %}
+            self.assertIsNone(self.dut.{{'.'.join(get_python_path_segments(node))}}.rdl_name)  # type: ignore[union-attr]
+                {% else %}
             self.assertEqual(self.dut.{{'.'.join(get_python_path_segments(node))}}.rdl_name, {{node.get_property('name') | tojson}}) # type: ignore[union-attr]
+                {% endif %}
             {% endif %}
 
         {% endfor %}
@@ -110,10 +114,14 @@ class {{fq_block_name}}_single_access({{top_node.inst_name}}_TestCase): # type:
         """
         {% for node in owned_elements.nodes -%}
         with self.subTest(msg='node: {{'.'.join(node.get_path_segments())}}'):
-            {% if node.get_property('desc', default=None) is none %}
-            self.assertIsNone(self.dut.{{'.'.join(get_python_path_segments(node))}}.rdl_desc)  # type: ignore[union-attr]
+            {% if skip_systemrdl_name_and_desc_properties %}
+                self.assertIsNone(self.dut.{{'.'.join(get_python_path_segments(node))}}.rdl_desc)  # type: ignore[union-attr]
             {% else %}
+                {% if node.get_property('desc', default=None) is none %}
+            self.assertIsNone(self.dut.{{'.'.join(get_python_path_segments(node))}}.rdl_desc)  # type: ignore[union-attr]
+                {% else %}
             self.assertEqual(self.dut.{{'.'.join(get_python_path_segments(node))}}.rdl_desc, {{node.get_property('desc') | tojson}}) # type: ignore[union-attr]
+                {% endif %}
             {% endif %}
 
         {% endfor %}

{peakrdl_python-1.2.1rc4 → peakrdl_python-1.3.0}/src/peakrdl_python/templates/addrmap_universal_property.py.jinja

@@ -17,6 +17,7 @@ along with this program.  If not, see <https://www.gnu.org/licenses/>.
 
 {%- macro universal_properties(node) %}
 
+    {%- if not skip_systemrdl_name_and_desc_properties %}
     {%- if 'name' in node.list_properties() -%}
     @property
     def rdl_name(self) -> str:
@@ -28,4 +29,5 @@ along with this program.  If not, see <https://www.gnu.org/licenses/>.
     def rdl_desc(self) -> str:
         return {{ node.get_property('desc') | tojson}}
     {% endif %}
+    {% endif %}
 {%- endmacro %}

{peakrdl_python-1.2.1rc4 → peakrdl_python-1.3.0}/src/peakrdl_python/templates/sim_addrmap.py.jinja

@@ -30,18 +30,24 @@ from {% if skip_lib_copy %}peakrdl_python.{% else %}..{% endif %}sim_lib.simulat
 from {% if skip_lib_copy %}peakrdl_python.{% else %}..{% endif %}sim_lib.simulator import Simulator{% if legacy_block_access %}Legacy{% endif %}
 {%- endif %}
 
-class {{top_node.inst_name}}_simulator_cls(Simulator{% if legacy_block_access %}Legacy{% endif %}):
-
-    def _build_registers(self) -> dict[int, Union[MemoryRegister, Register]]:
-        return {
-        {%- for node in top_node.descendants(unroll=True) -%}
-            {% if isinstance(node, systemrdlRegNode) %}
-            {{node.absolute_address}} : {% if isinstance(node.parent, systemrdlMemNode) %}MemoryRegister(memory=self.memory_for_address_with_exception({{node.absolute_address}}).memory,memory_address_offset={{node.address_offset}},{% else %}Register({% endif %}width={{node.size*8}}, full_inst_name='{{'.'.join(node.get_path_segments())}}', readable={{node.has_sw_readable}}, writable={{node.has_sw_writable}},
+{%- macro single_reg_entry(node) %}
+    {% if isinstance(node.parent, systemrdlMemNode) %}MemoryRegister(memory=self.memory_for_address_with_exception({{node.absolute_address}}).memory,memory_address_offset={{node.address_offset}},{% else %}Register({% endif %}width={{node.size*8}}, full_inst_name='{{'.'.join(node.get_path_segments())}}', readable={{node.has_sw_readable}}, writable={{node.has_sw_writable}},
                                          fields=[
                                                 {%- for field in node.fields() -%}
                                                 FieldDefinition(high={{field.high}}, low={{field.low}}, msb={{field.msb}}, lsb={{field.lsb}}, inst_name='{{field.inst_name}}'),
                                                 {%- endfor %}
-                                                ]),
+                                                ])
+{%- endmacro %}
+
+class {{top_node.inst_name}}_simulator_cls(Simulator{% if legacy_block_access %}Legacy{% endif %}):
+
+    def _build_registers(self) -> dict[int, Union[list[Union[MemoryRegister, Register]], Union[MemoryRegister, Register]]]:
+        return {
+        {%- for addr, addr_entry in reg_dict.items() -%}
+            {% if isinstance(addr_entry, list) %}
+            {{addr}} : [{% for node in addr_entry %}{{single_reg_entry(node)}},{% endfor %}],
+            {% else %}
+            {{addr}} : {{single_reg_entry(addr_entry)}},
             {%- endif %}
         {%- endfor %}
         }

{peakrdl_python-1.2.1rc4 → peakrdl_python-1.3.0}/src/peakrdl_python.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: peakrdl-python
-Version: 1.2.1rc4
+Version: 1.3.0
 Summary: Generate Python Register Access Layer (RAL) from SystemRDL
 Author: Keith Brady
 License:                     GNU GENERAL PUBLIC LICENSE

{peakrdl_python-1.2.1rc4 → peakrdl_python-1.3.0}/src/peakrdl_python.egg-info/SOURCES.txt

@@ -137,6 +137,7 @@ tests/testcases/reg_name_stress.rdl
 tests/testcases/regfile_and_arrays.rdl
 tests/testcases/reserved_elements.rdl
 tests/testcases/same_but_different_enum.rdl
+tests/testcases/shared_register_issue_202
 tests/testcases/signals_definitions_at_various_levels.rdl
 tests/testcases/simple.rdl
 tests/testcases/simple.xml

peakrdl_python-1.3.0/tests/testcases/shared_register_issue_202

@@ -0,0 +1,24 @@
+addrmap shared_register_issue_202 {
+
+     reg {
+        field { fieldwidth=1; sw=rw; } enable;
+     } control ;
+
+     reg {
+        field { fieldwidth=16; sw=w; hw=r; } data;
+     } tx @ 4;
+
+     reg {
+        field { fieldwidth=16; sw=r; hw=w; } data;
+     } rx @ 4;
+
+     reg {
+        field { fieldwidth=8; sw=r; hw=w; } count;
+     } rx_fifo_fill;
+
+     reg {
+        field { fieldwidth=8; sw=r; hw=w; } count;
+     } tx_fifo_fill;
+
+};
+