peakrdl-python 1.2.1rc2__tar.gz → 1.2.1rc3__tar.gz

{peakrdl_python-1.2.1rc2 → peakrdl_python-1.2.1rc3}/.github/workflows/action.yaml

@@ -296,7 +296,6 @@ jobs:
     - name: Static checks
       run: |
 
-        # one of the test cases uses IPxact so we need the importer
         mypy testcase_output
         # pylint testcase_output/autopep8 --disable=duplicate-code,line-too-long,too-many-statements,invalid-name,unused-import,too-many-instance-attributes,too-many-arguments,too-many-lines
 

{peakrdl_python-1.2.1rc2 → peakrdl_python-1.2.1rc3}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: peakrdl-python
-Version: 1.2.1rc2
+Version: 1.2.1rc3
 Summary: Generate Python Register Access Layer (RAL) from SystemRDL
 Author: Keith Brady
 License:                     GNU GENERAL PUBLIC LICENSE

{peakrdl_python-1.2.1rc2 → peakrdl_python-1.2.1rc3}/src/peakrdl_python/__about__.py

@@ -17,4 +17,4 @@ along with this program.  If not, see <https://www.gnu.org/licenses/>.
 
 Variables that describes the peakrdl-python Package
 """
-__version__ = "1.2.1rc2"
+__version__ = "1.2.1rc3"

{peakrdl_python-1.2.1rc2 → peakrdl_python-1.2.1rc3}/src/peakrdl_python/templates/addrmap_tb.py.jinja

@@ -889,6 +889,7 @@ class {{fq_block_name}}_single_access({{top_node.inst_name}}_TestCase): # type:
                     write_callback_mock.reset_mock()
                     read_callback_mock.reset_mock()
 
+        kwargs : dict[str, Union[bool, {% if legacy_enum_type %}IntEnum{% else %}SystemRDLEnum{% endif %}, int]]
 
         {% for node in owned_elements.registers -%}
         {% if node.has_sw_writable %}
@@ -901,16 +902,16 @@ class {{fq_block_name}}_single_access({{top_node.inst_name}}_TestCase): # type:
                                                            '{{ safe_node_name(field) }}' {%- if not loop.last -%},{%- endif %}
                                                            {% endfor -%} ])
             {% else -%}
-            kwargs = {} # type: ignore[var-annotated]
+            kwargs = {}
             expected_value = 0
             {% for field in get_reg_writable_fields(node, hide_node_func) %}
             {%- if 'encode' in field.list_properties() %}
             rand_enum_value = random_enum_reg_value(self.dut.{{'.'.join(get_python_path_segments(field))}}.enum_cls)
             rand_field_value = rand_enum_value.value
-            kwargs['{{field.inst_name}}'] = rand_enum_value
+            kwargs['{{ safe_node_name(field)}}'] = rand_enum_value
             {%- else %}
             rand_field_value = random.randrange(0, {{ get_field_max_value_hex_string(field) }} + 1)
-            kwargs['{{field.inst_name}}'] = rand_field_value
+            kwargs['{{ safe_node_name(field)}}'] = rand_field_value
             {%- endif  %}
             expected_value = ( expected_value & {{get_field_inv_bitmask_hex_string(field)}} ) | (rand_field_value << {{ field.low }})
             {% endfor %}

{peakrdl_python-1.2.1rc2 → peakrdl_python-1.2.1rc3}/src/peakrdl_python.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: peakrdl-python
-Version: 1.2.1rc2
+Version: 1.2.1rc3
 Summary: Generate Python Register Access Layer (RAL) from SystemRDL
 Author: Keith Brady
 License:                     GNU GENERAL PUBLIC LICENSE

{peakrdl_python-1.2.1rc2 → peakrdl_python-1.2.1rc3}/tests/testcases/name_clash.rdl

@@ -27,6 +27,30 @@ addrmap name_clash {
         field { fieldwidth=1; } len = 1;
     } gpio_status;
 
+    reg {
+        /*
+        This test was introduced as part of #198 to check that a a field with write only and
+        remapped names is handled correctly
+        */
+        field { fieldwidth=1; sw = w; } from = 1;
+        field { fieldwidth=1; sw = r; } in = 1;
+        field { fieldwidth=1; sw = rw; } yield = 1;
+        field { fieldwidth=1; sw = w; encode = direction; } finally;
+        field { fieldwidth=1; sw = r; encode = direction; } pass;
+        field { fieldwidth=1; sw = rw; encode = direction; } is;
+    } gpio_field_rw;
+
+    reg {
+        default sw = r;
+        field { fieldwidth=1; sw = r; } in = 1;
+    } gpio_field_r;
+
+    reg {
+        default sw = w;
+        field { fieldwidth=1; sw = w; encode = direction; } pass;
+        field { fieldwidth=1; sw = w; } from = 1;
+    } gpio_field_w;
+
     reg {
         field { fieldwidth=1; } msb = 1;
         field { fieldwidth=1; python_inst_name="pass_field"; } pass = 1;