peakrdl-busdecoder 0.6.6__tar.gz → 0.6.7__tar.gz

{peakrdl_busdecoder-0.6.6 → peakrdl_busdecoder-0.6.7}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: peakrdl-busdecoder
-Version: 0.6.6
+Version: 0.6.7
 Summary: Generate a SystemVerilog bus decoder from SystemRDL for splitting CPU interfaces to multiple sub-address spaces
 Author: Arnav Sacheti
 License: LGPLv3

{peakrdl_busdecoder-0.6.6 → peakrdl_busdecoder-0.6.7}/pyproject.toml

@@ -4,7 +4,7 @@ build-backend = "setuptools.build_meta"
 
 [project]
 name = "peakrdl-busdecoder"
-version = "0.6.6"
+version = "0.6.7"
 requires-python = ">=3.10"
 dependencies = [
     "jinja2~=3.1",

{peakrdl_busdecoder-0.6.6 → peakrdl_busdecoder-0.6.7}/src/peakrdl_busdecoder/cpuif/apb3/apb3_tmpl.sv

@@ -37,4 +37,4 @@ assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err | cpuif_wr_err;
 //--------------------------------------------------------------------------
 // Fanin CPU Bus interface signals
 //--------------------------------------------------------------------------
-{{fanin|walk(cpuif=cpuif)}}
+{{fanin|walk(cpuif=cpuif)}}

{peakrdl_busdecoder-0.6.6 → peakrdl_busdecoder-0.6.7}/src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv

@@ -38,4 +38,4 @@ assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err | cpuif_wr_err;
 //--------------------------------------------------------------------------
 // Fanin CPU Bus interface signals
 //--------------------------------------------------------------------------
-{{fanin|walk(cpuif=cpuif)}}
+{{fanin|walk(cpuif=cpuif)}}

{peakrdl_busdecoder-0.6.6 → peakrdl_busdecoder-0.6.7}/src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif.py

@@ -77,8 +77,8 @@ class AXI4LiteCpuif(BaseCpuif):
             if self.is_interface and node.is_array and node.array_dimensions:
                 # Generate array index string [i0][i1]... for the intermediate signal
                 array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
-                fanin["cpuif_wr_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
-                fanin["cpuif_wr_err"] = f"{node.inst_name}_fanin_err{array_idx}"
+                fanin["cpuif_wr_ack"] = f"{node.inst_name}_fanin_wr_valid{array_idx}"
+                fanin["cpuif_wr_err"] = f"{node.inst_name}_fanin_wr_err{array_idx}"
             else:
                 # Read side: ack comes from RVALID; err if RRESP[1] is set (SLVERR/DECERR)
                 fanin["cpuif_wr_ack"] = self.signal("BVALID", node, "i")
@@ -119,4 +119,16 @@ class AXI4LiteCpuif(BaseCpuif):
             f"assign {inst_name}_fanin_ready{array_idx} = {master_prefix}{indexed_path}.RVALID;",
             f"assign {inst_name}_fanin_err{array_idx} = {master_prefix}{indexed_path}.RRESP[1];",
             f"assign {inst_name}_fanin_data{array_idx} = {master_prefix}{indexed_path}.RDATA;",
+            f"assign {inst_name}_fanin_wr_valid{array_idx} = {master_prefix}{indexed_path}.BVALID;",
+            f"assign {inst_name}_fanin_wr_err{array_idx} = {master_prefix}{indexed_path}.BRESP[1];",
+        ]
+
+    def fanin_intermediate_declarations(self, node: AddressableNode) -> list[str]:
+        if not node.array_dimensions:
+            return []
+
+        array_str = "".join(f"[{dim}]" for dim in node.array_dimensions)
+        return [
+            f"logic {node.inst_name}_fanin_wr_valid{array_str};",
+            f"logic {node.inst_name}_fanin_wr_err{array_str};",
         ]

{peakrdl_busdecoder-0.6.6 → peakrdl_busdecoder-0.6.7}/src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_tmpl.sv

@@ -26,9 +26,21 @@
 `endif
 {% endif -%}
 
+logic axi_wr_valid;
+logic axi_wr_invalid;
+logic cpuif_wr_ack_int;
+logic cpuif_rd_ack_int;
+
+assign axi_wr_valid = {{cpuif.signal("AWVALID")}} & {{cpuif.signal("WVALID")}};
+assign axi_wr_invalid = {{cpuif.signal("AWVALID")}} ^ {{cpuif.signal("WVALID")}};
+
+// Ready/acceptance follows the simplified single-beat requirement
+assign {{cpuif.signal("AWREADY")}} = axi_wr_valid;
+assign {{cpuif.signal("WREADY")}}  = axi_wr_valid;
+assign {{cpuif.signal("ARREADY")}} = {{cpuif.signal("ARVALID")}};
 
 assign cpuif_req     = {{cpuif.signal("AWVALID")}} | {{cpuif.signal("ARVALID")}};
-assign cpuif_wr_en   = {{cpuif.signal("AWVALID")}} & {{cpuif.signal("WVALID")}};
+assign cpuif_wr_en   = axi_wr_valid;
 assign cpuif_rd_en   = {{cpuif.signal("ARVALID")}};
 
 assign cpuif_wr_addr = {{cpuif.signal("AWADDR")}};
@@ -42,12 +54,14 @@ assign cpuif_wr_byte_en = {{cpuif.signal("WSTRB")}};
 // Read: ack=RVALID, err=RRESP[1] (SLVERR/DECERR), data=RDATA
 //
 assign {{cpuif.signal("RDATA")}}  = cpuif_rd_data;
-assign {{cpuif.signal("RVALID")}} = cpuif_rd_ack;
+assign cpuif_rd_ack_int = cpuif_rd_ack | cpuif_rd_sel.cpuif_err;
+assign {{cpuif.signal("RVALID")}} = cpuif_rd_ack_int;
 assign {{cpuif.signal("RRESP")}}  = (cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err) ? 2'b10 : 2'b00;
 
 // Write: ack=BVALID, err=BRESP[1]
-assign {{cpuif.signal("BVALID")}} = cpuif_wr_ack;
-assign {{cpuif.signal("BRESP")}}  = (cpuif_wr_err | cpuif_wr_sel.cpuif_err | cpuif_rd_sel.cpuif_err) ? 2'b10 : 2'b00;
+assign cpuif_wr_ack_int = cpuif_wr_ack | cpuif_wr_sel.cpuif_err | axi_wr_invalid;
+assign {{cpuif.signal("BVALID")}} = cpuif_wr_ack_int;
+assign {{cpuif.signal("BRESP")}}  = (cpuif_wr_err | cpuif_wr_sel.cpuif_err | cpuif_rd_sel.cpuif_err | axi_wr_invalid) ? 2'b10 : 2'b00;
 
 //--------------------------------------------------------------------------
 // Fanout CPU Bus interface signals
@@ -64,4 +78,4 @@ assign {{cpuif.signal("BRESP")}}  = (cpuif_wr_err | cpuif_wr_sel.cpuif_err | cpu
 //--------------------------------------------------------------------------
 // Fanin CPU Bus interface signals
 //--------------------------------------------------------------------------
-{{fanin|walk(cpuif=cpuif)}}
+{{fanin|walk(cpuif=cpuif)}}

{peakrdl_busdecoder-0.6.6 → peakrdl_busdecoder-0.6.7}/src/peakrdl_busdecoder/cpuif/base_cpuif.py

@@ -136,3 +136,7 @@ class BaseCpuif:
             List of assignment strings
         """
         return []  # Default: no intermediate assignments needed
+
+    def fanin_intermediate_declarations(self, node: AddressableNode) -> list[str]:
+        """Optional extra intermediate signal declarations for interface arrays."""
+        return []

{peakrdl_busdecoder-0.6.6 → peakrdl_busdecoder-0.6.7}/src/peakrdl_busdecoder/cpuif/fanin_gen.py

@@ -72,12 +72,12 @@ class FaninGenerator(BusDecoderListener):
     def __str__(self) -> str:
         wr_ifb = IfBody()
         with wr_ifb.cm("cpuif_wr_sel.cpuif_err") as b:
-            self._cpuif.fanin_wr(error=True)
+            b += self._cpuif.fanin_wr(error=True)
         self._stack[-1] += wr_ifb
 
         rd_ifb = IfBody()
         with rd_ifb.cm("cpuif_rd_sel.cpuif_err") as b:
-            self._cpuif.fanin_rd(error=True)
+            b += self._cpuif.fanin_rd(error=True)
         self._stack[-1] += rd_ifb
 
         return "\n".join(map(str, self._stack))

{peakrdl_busdecoder-0.6.6 → peakrdl_busdecoder-0.6.7}/src/peakrdl_busdecoder/cpuif/fanin_intermediate_gen.py

@@ -94,6 +94,9 @@ class FaninIntermediateGenerator(BusDecoderListener):
             f"logic [{self._cpuif.data_width - 1}:0] {inst_name}_fanin_data{array_str};"
         )
 
+        # Allow CPU interface to add extra intermediate declarations (e.g., write responses)
+        self._declarations.extend(self._cpuif.fanin_intermediate_declarations(node))
+
     def _generate_intermediate_assignments(self, node: AddressableNode) -> str:
         """Generate assignments from interface array to intermediate signals."""
         inst_name = node.inst_name

{peakrdl_busdecoder-0.6.6 → peakrdl_busdecoder-0.6.7}/src/peakrdl_busdecoder.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: peakrdl-busdecoder
-Version: 0.6.6
+Version: 0.6.7
 Summary: Generate a SystemVerilog bus decoder from SystemRDL for splitting CPU interfaces to multiple sub-address spaces
 Author: Arnav Sacheti
 License: LGPLv3

{peakrdl_busdecoder-0.6.6 → peakrdl_busdecoder-0.6.7}/uv.lock

@@ -658,7 +658,7 @@ wheels = [
 
 [[package]]
 name = "peakrdl-busdecoder"
-version = "0.6.6"
+version = "0.6.7"
 source = { editable = "." }
 dependencies = [
     { name = "jinja2" },