peakrdl-busdecoder 0.6.4__tar.gz → 0.6.6__tar.gz

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/.github/workflows/typecheck.yml

@@ -22,5 +22,5 @@ jobs:
       - name: Install package
         run: uv sync --extra cli
       
-      - name: Run pyrefly type check
-        run: uvx pyrefly check src/
+      - name: Run ty type check
+        run: uvx ty check src/

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: peakrdl-busdecoder
-Version: 0.6.4
+Version: 0.6.6
 Summary: Generate a SystemVerilog bus decoder from SystemRDL for splitting CPU interfaces to multiple sub-address spaces
 Author: Arnav Sacheti
 License: LGPLv3

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/docs/configuring.rst

@@ -1,7 +1,7 @@
 .. _peakrdl_cfg:
 
 Configuring PeakRDL-BusDecoder
-============================
+==============================
 
 If using the `PeakRDL command line tool <https://peakrdl.readthedocs.io/>`_,
 some aspects of the ``busdecoder`` command have additional configuration options

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/docs/licensing.rst

@@ -15,7 +15,7 @@ be contrary to this project's philosophy.
 
 
 What is covered by the LGPL v3 license?
---------------------------------------
+---------------------------------------
 The LGPL license is intended for the code generator itself. This includes all
 Python sources, Jinja template files, as well as testcase infrastructure not
 explicitly mentioned in the exemptions below.

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/pyproject.toml

@@ -4,7 +4,7 @@ build-backend = "setuptools.build_meta"
 
 [project]
 name = "peakrdl-busdecoder"
-version = "0.6.4"
+version = "0.6.6"
 requires-python = ">=3.10"
 dependencies = [
     "jinja2~=3.1",
@@ -65,7 +65,7 @@ test = [
     "cocotb>=1.8.0",
     "cocotb-bus>=0.2.1",
 ]
-tools = ["pyrefly>=0.37.0", "ruff>=0.14.0"]
+tools = ["ty>=0.0.7", "ruff>=0.14.0"]
 
 [project.entry-points."peakrdl.exporters"]
 busdecoder = "peakrdl_busdecoder.__peakrdl__:Exporter"
@@ -100,15 +100,12 @@ ignore = [
 quote-style = "double"
 indent-style = "space"
 
-# ---------------------- PYREFLY ----------------------
-[tool.pyrefly]
+# ---------------------- TY ----------------------
+[tool.ty.environment]
 python-version = "3.10"
 
-# Default behavior: check bodies of untyped defs & infer return types.
-untyped-def-behavior = "check-and-infer-return-type"
-
-project-includes = ["src/**/*"]
-project-excludes = ["**/__pycache__", "**/*venv/**/*"]
+[tool.ty.src]
+include = ["src"]
 
 # ---------------------- PYTEST ----------------------
 [tool.pytest.ini_options]

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/src/peakrdl_busdecoder/__peakrdl__.py

@@ -1,3 +1,5 @@
+from __future__ import annotations
+
 import functools
 from typing import TYPE_CHECKING, Any
 
@@ -69,7 +71,7 @@ class Exporter(ExporterSubcommandPlugin):
     def get_cpuifs(self) -> dict[str, type[BaseCpuif]]:
         return get_cpuifs(map(tuple, self.cfg["cpuifs"].items()))
 
-    def add_exporter_arguments(self, arg_group: "argparse.ArgumentParser") -> None:  # type: ignore
+    def add_exporter_arguments(self, arg_group: argparse._ActionsContainer) -> None:
         cpuifs = self.get_cpuifs()
 
         arg_group.add_argument(
@@ -122,7 +124,7 @@ class Exporter(ExporterSubcommandPlugin):
             """,
         )
 
-    def do_export(self, top_node: "AddrmapNode", options: "argparse.Namespace") -> None:
+    def do_export(self, top_node: AddrmapNode, options: argparse.Namespace) -> None:
         cpuifs = self.get_cpuifs()
 
         x = BusDecoderExporter()

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/src/peakrdl_busdecoder/cpuif/apb3/apb3_cpuif.py

@@ -45,42 +45,53 @@ class APB3Cpuif(BaseCpuif):
         fanout[self.signal("PADDR", node, "gi")] = self.signal("PADDR")
         fanout[self.signal("PWDATA", node, "gi")] = "cpuif_wr_data"
 
-        return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
+        return "\n".join(f"assign {kv[0]} = {kv[1]};" for kv in fanout.items())
 
-    def fanin(self, node: AddressableNode | None = None) -> str:
+    def fanin_wr(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
-            fanin["cpuif_rd_ack"] = "'0"
-            fanin["cpuif_rd_err"] = "'0"
+            fanin["cpuif_wr_ack"] = "'0"
+            fanin["cpuif_wr_err"] = "'0"
+            if error:
+                fanin["cpuif_wr_ack"] = "'1"
+                fanin["cpuif_wr_err"] = "cpuif_wr_sel.cpuif_err"
         else:
             # Use intermediate signals for interface arrays to avoid
             # non-constant indexing of interface arrays in procedural blocks
             if self.is_interface and node.is_array and node.array_dimensions:
                 # Generate array index string [i0][i1]... for the intermediate signal
                 array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
-                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
-                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
+                fanin["cpuif_wr_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_wr_err"] = f"{node.inst_name}_fanin_err{array_idx}"
             else:
-                fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
-                fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
-
-        return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
+                fanin["cpuif_wr_ack"] = self.signal("PREADY", node, "i")
+                fanin["cpuif_wr_err"] = self.signal("PSLVERR", node, "i")
+        return "\n".join(f"{kv[0]} = {kv[1]};" for kv in fanin.items())
 
-    def readback(self, node: AddressableNode | None = None) -> str:
+    def fanin_rd(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
             fanin["cpuif_rd_data"] = "'0"
+            if error:
+                fanin["cpuif_rd_ack"] = "'1"
+                fanin["cpuif_rd_err"] = "cpuif_rd_sel.cpuif_err"
         else:
             # Use intermediate signals for interface arrays to avoid
             # non-constant indexing of interface arrays in procedural blocks
             if self.is_interface and node.is_array and node.array_dimensions:
                 # Generate array index string [i0][i1]... for the intermediate signal
                 array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
                 fanin["cpuif_rd_data"] = f"{node.inst_name}_fanin_data{array_idx}"
             else:
+                fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
+                fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
                 fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
 
-        return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
+        return "\n".join(f"{kv[0]} = {kv[1]};" for kv in fanin.items())
 
     def fanin_intermediate_assignments(
         self, node: AddressableNode, inst_name: str, array_idx: str, master_prefix: str, indexed_path: str

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/src/peakrdl_busdecoder/cpuif/apb3/apb3_cpuif_flat.py

@@ -51,24 +51,34 @@ class APB3CpuifFlat(BaseCpuif):
         fanout[self.signal("PADDR", node, "gi")] = f"{{{'-'.join(addr_comp)}}}[{clog2(node.size) - 1}:0]"
         fanout[self.signal("PWDATA", node, "gi")] = "cpuif_wr_data"
 
-        return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
+        return "\n".join(f"assign {kv[0]} = {kv[1]};" for kv in fanout.items())
 
-    def fanin(self, node: AddressableNode | None = None) -> str:
+    def fanin_wr(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
-            fanin["cpuif_rd_ack"] = "'0"
-            fanin["cpuif_rd_err"] = "'0"
+            fanin["cpuif_wr_ack"] = "'0"
+            fanin["cpuif_wr_err"] = "'0"
+            if error:
+                fanin["cpuif_wr_ack"] = "'1"
+                fanin["cpuif_wr_err"] = "cpuif_wr_sel.cpuif_err"
         else:
-            fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
-            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
+            fanin["cpuif_wr_ack"] = self.signal("PREADY", node, "i")
+            fanin["cpuif_wr_err"] = self.signal("PSLVERR", node, "i")
 
-        return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
+        return "\n".join(f"{kv[0]} = {kv[1]};" for kv in fanin.items())
 
-    def readback(self, node: AddressableNode | None = None) -> str:
+    def fanin_rd(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
             fanin["cpuif_rd_data"] = "'0"
+            if error:
+                fanin["cpuif_rd_ack"] = "'1"
+                fanin["cpuif_rd_err"] = "cpuif_rd_sel.cpuif_err"
         else:
+            fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
+            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
             fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
 
-        return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
+        return "\n".join(f"{kv[0]} = {kv[1]};" for kv in fanin.items())

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/src/peakrdl_busdecoder/cpuif/apb3/apb3_tmpl.sv

@@ -19,8 +19,8 @@ assign cpuif_rd_addr = {{cpuif.signal("PADDR")}};
 assign cpuif_wr_data = {{cpuif.signal("PWDATA")}};
 
 assign {{cpuif.signal("PRDATA")}} = cpuif_rd_data;
-assign {{cpuif.signal("PREADY")}} = cpuif_rd_ack;
-assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
+assign {{cpuif.signal("PREADY")}} = cpuif_rd_ack | cpuif_wr_ack;
+assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err | cpuif_wr_err;
 
 //--------------------------------------------------------------------------
 // Fanout CPU Bus interface signals

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/src/peakrdl_busdecoder/cpuif/apb4/apb4_cpuif.py

@@ -48,42 +48,54 @@ class APB4Cpuif(BaseCpuif):
         fanout[self.signal("PWDATA", node, "gi")] = "cpuif_wr_data"
         fanout[self.signal("PSTRB", node, "gi")] = "cpuif_wr_byte_en"
 
-        return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
+        return "\n".join(f"assign {kv[0]} = {kv[1]};" for kv in fanout.items())
 
-    def fanin(self, node: AddressableNode | None = None) -> str:
+    def fanin_wr(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
-            fanin["cpuif_rd_ack"] = "'0"
-            fanin["cpuif_rd_err"] = "'0"
+            fanin["cpuif_wr_ack"] = "'0"
+            fanin["cpuif_wr_err"] = "'0"
+            if error:
+                fanin["cpuif_wr_ack"] = "'1"
+                fanin["cpuif_wr_err"] = "cpuif_wr_sel.cpuif_err"
         else:
             # Use intermediate signals for interface arrays to avoid
             # non-constant indexing of interface arrays in procedural blocks
             if self.is_interface and node.is_array and node.array_dimensions:
                 # Generate array index string [i0][i1]... for the intermediate signal
                 array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
-                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
-                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
+                fanin["cpuif_wr_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_wr_err"] = f"{node.inst_name}_fanin_err{array_idx}"
             else:
-                fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
-                fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
+                fanin["cpuif_wr_ack"] = self.signal("PREADY", node, "i")
+                fanin["cpuif_wr_err"] = self.signal("PSLVERR", node, "i")
 
-        return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
+        return "\n".join(f"{kv[0]} = {kv[1]};" for kv in fanin.items())
 
-    def readback(self, node: AddressableNode | None = None) -> str:
+    def fanin_rd(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
             fanin["cpuif_rd_data"] = "'0"
+            if error:
+                fanin["cpuif_rd_ack"] = "'1"
+                fanin["cpuif_rd_err"] = "cpuif_rd_sel.cpuif_err"
         else:
             # Use intermediate signals for interface arrays to avoid
             # non-constant indexing of interface arrays in procedural blocks
             if self.is_interface and node.is_array and node.array_dimensions:
                 # Generate array index string [i0][i1]... for the intermediate signal
                 array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
                 fanin["cpuif_rd_data"] = f"{node.inst_name}_fanin_data{array_idx}"
             else:
+                fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
+                fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
                 fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
 
-        return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
+        return "\n".join(f"{kv[0]} = {kv[1]};" for kv in fanin.items())
 
     def fanin_intermediate_assignments(
         self, node: AddressableNode, inst_name: str, array_idx: str, master_prefix: str, indexed_path: str

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/src/peakrdl_busdecoder/cpuif/apb4/apb4_cpuif_flat.py

@@ -53,24 +53,33 @@ class APB4CpuifFlat(BaseCpuif):
         fanout[self.signal("PWDATA", node, "gi")] = "cpuif_wr_data"
         fanout[self.signal("PSTRB", node, "gi")] = "cpuif_wr_byte_en"
 
-        return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
+        return "\n".join(f"assign {kv[0]} = {kv[1]};" for kv in fanout.items())
 
-    def fanin(self, node: AddressableNode | None = None) -> str:
+    def fanin_wr(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
-            fanin["cpuif_rd_ack"] = "'0"
-            fanin["cpuif_rd_err"] = "'0"
+            fanin["cpuif_wr_ack"] = "'0"
+            fanin["cpuif_wr_err"] = "'0"
+            if error:
+                fanin["cpuif_wr_ack"] = "'1"
+                fanin["cpuif_wr_err"] = "cpuif_wr_sel.cpuif_err"
         else:
-            fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
-            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
-
-        return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
+            fanin["cpuif_wr_ack"] = self.signal("PREADY", node, "i")
+            fanin["cpuif_wr_err"] = self.signal("PSLVERR", node, "i")
+        return "\n".join(f"{kv[0]} = {kv[1]};" for kv in fanin.items())
 
-    def readback(self, node: AddressableNode | None = None) -> str:
+    def fanin_rd(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
             fanin["cpuif_rd_data"] = "'0"
+            if error:
+                fanin["cpuif_rd_ack"] = "'1"
+                fanin["cpuif_rd_err"] = "cpuif_rd_sel.cpuif_err"
         else:
+            fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
+            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
             fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
 
-        return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
+        return "\n".join(f"{kv[0]} = {kv[1]};" for kv in fanin.items())

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv

@@ -20,8 +20,8 @@ assign cpuif_wr_data = {{cpuif.signal("PWDATA")}};
 assign cpuif_wr_byte_en = {{cpuif.signal("PSTRB")}};
 
 assign {{cpuif.signal("PRDATA")}} = cpuif_rd_data;
-assign {{cpuif.signal("PREADY")}} = cpuif_rd_ack;
-assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
+assign {{cpuif.signal("PREADY")}} = cpuif_rd_ack | cpuif_wr_ack; 
+assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err | cpuif_wr_err;
 
 //--------------------------------------------------------------------------
 // Fanout CPU Bus interface signals

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif.py

@@ -63,38 +63,50 @@ class AXI4LiteCpuif(BaseCpuif):
 
         return "\n".join(f"assign {lhs} = {rhs};" for lhs, rhs in fanout.items())
 
-    def fanin(self, node: AddressableNode | None = None) -> str:
+    def fanin_wr(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
-            fanin["cpuif_rd_ack"] = "'0"
-            fanin["cpuif_rd_err"] = "'0"
+            fanin["cpuif_wr_ack"] = "'0"
+            fanin["cpuif_wr_err"] = "'0"
+            if error:
+                fanin["cpuif_wr_ack"] = "'1"
+                fanin["cpuif_wr_err"] = "cpuif_wr_sel.cpuif_err"
         else:
             # Use intermediate signals for interface arrays to avoid
             # non-constant indexing of interface arrays in procedural blocks
             if self.is_interface and node.is_array and node.array_dimensions:
                 # Generate array index string [i0][i1]... for the intermediate signal
                 array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
-                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
-                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
+                fanin["cpuif_wr_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_wr_err"] = f"{node.inst_name}_fanin_err{array_idx}"
             else:
                 # Read side: ack comes from RVALID; err if RRESP[1] is set (SLVERR/DECERR)
-                fanin["cpuif_rd_ack"] = self.signal("RVALID", node, "i")
-                fanin["cpuif_rd_err"] = f"{self.signal('RRESP', node, 'i')}[1]"
+                fanin["cpuif_wr_ack"] = self.signal("BVALID", node, "i")
+                fanin["cpuif_wr_err"] = f"{self.signal('BRESP', node, 'i')}[1]"
 
         return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())
 
-    def readback(self, node: AddressableNode | None = None) -> str:
+    def fanin_rd(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
             fanin["cpuif_rd_data"] = "'0"
+            if error:
+                fanin["cpuif_rd_ack"] = "'1"
+                fanin["cpuif_rd_err"] = "cpuif_rd_sel.cpuif_err"
         else:
             # Use intermediate signals for interface arrays to avoid
             # non-constant indexing of interface arrays in procedural blocks
             if self.is_interface and node.is_array and node.array_dimensions:
                 # Generate array index string [i0][i1]... for the intermediate signal
                 array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
                 fanin["cpuif_rd_data"] = f"{node.inst_name}_fanin_data{array_idx}"
             else:
+                fanin["cpuif_rd_ack"] = self.signal("RVALID", node, "i")
+                fanin["cpuif_rd_err"] = f"{self.signal('RRESP', node, 'i')}[1]"
                 fanin["cpuif_rd_data"] = self.signal("RDATA", node, "i")
 
         return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif_flat.py

@@ -72,23 +72,33 @@ class AXI4LiteCpuifFlat(BaseCpuif):
 
         return "\n".join(f"assign {lhs} = {rhs};" for lhs, rhs in fanout.items())
 
-    def fanin(self, node: AddressableNode | None = None) -> str:
+    def fanin_wr(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
-            fanin["cpuif_rd_ack"] = "'0"
-            fanin["cpuif_rd_err"] = "'0"
+            fanin["cpuif_wr_ack"] = "'0"
+            fanin["cpuif_wr_err"] = "'0"
+            if error:
+                fanin["cpuif_wr_ack"] = "'1"
+                fanin["cpuif_wr_err"] = "cpuif_wr_sel.cpuif_err"
         else:
             # Read side: ack comes from RVALID; err if RRESP[1] is set (SLVERR/DECERR)
-            fanin["cpuif_rd_ack"] = self.signal("RVALID", node, "i")
-            fanin["cpuif_rd_err"] = f"{self.signal('RRESP', node, 'i')}[1]"
+            fanin["cpuif_wr_ack"] = self.signal("BVALID", node, "i")
+            fanin["cpuif_wr_err"] = f"{self.signal('BRESP', node, 'i')}[1]"
 
         return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())
 
-    def readback(self, node: AddressableNode | None = None) -> str:
+    def fanin_rd(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
             fanin["cpuif_rd_data"] = "'0"
+            if error:
+                fanin["cpuif_rd_ack"] = "'1"
+                fanin["cpuif_rd_err"] = "cpuif_rd_sel.cpuif_err"
         else:
+            fanin["cpuif_rd_ack"] = self.signal("RVALID", node, "i")
+            fanin["cpuif_rd_err"] = f"{self.signal('RRESP', node, 'i')}[1]"
             fanin["cpuif_rd_data"] = self.signal("RDATA", node, "i")
 
         return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/src/peakrdl_busdecoder/cpuif/base_cpuif.py

@@ -82,15 +82,15 @@ class BaseCpuif:
             loader=loader,
             undefined=jj.StrictUndefined,
         )
-        jj_env.tests["array"] = self.check_is_array  # type: ignore
-        jj_env.filters["clog2"] = clog2  # type: ignore
-        jj_env.filters["is_pow2"] = is_pow2  # type: ignore
-        jj_env.filters["roundup_pow2"] = roundup_pow2  # type: ignore
-        jj_env.filters["address_slice"] = self.get_address_slice  # type: ignore
-        jj_env.filters["get_path"] = lambda x: get_indexed_path(self.exp.ds.top_node, x, "i")  # type: ignore
-        jj_env.filters["walk"] = self.exp.walk  # type: ignore
-
-        context = {  # type: ignore
+        jj_env.tests["array"] = self.check_is_array
+        jj_env.filters["clog2"] = clog2
+        jj_env.filters["is_pow2"] = is_pow2
+        jj_env.filters["roundup_pow2"] = roundup_pow2
+        jj_env.filters["address_slice"] = self.get_address_slice
+        jj_env.filters["get_path"] = lambda x: get_indexed_path(self.exp.ds.top_node, x, "i")
+        jj_env.filters["walk"] = self.exp.walk
+
+        context = {
             "cpuif": self,
             "ds": self.exp.ds,
             "fanout": FanoutGenerator,
@@ -110,10 +110,10 @@ class BaseCpuif:
     def fanout(self, node: AddressableNode, array_stack: deque[int]) -> str:
         raise NotImplementedError
 
-    def fanin(self, node: AddressableNode | None = None) -> str:
+    def fanin_wr(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         raise NotImplementedError
 
-    def readback(self, node: AddressableNode | None = None) -> str:
+    def fanin_rd(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         raise NotImplementedError
 
     def fanin_intermediate_assignments(

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/src/peakrdl_busdecoder/cpuif/fanin_gen.py

@@ -20,8 +20,8 @@ class FaninGenerator(BusDecoderListener):
 
         self._stack: deque[Body] = deque()
         cb = CombinationalBody()
-        cb += cpuif.fanin()
-        cb += cpuif.readback()
+        cb += cpuif.fanin_wr()
+        cb += cpuif.fanin_rd()
         self._stack.append(cb)
 
     def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
@@ -48,15 +48,13 @@ class FaninGenerator(BusDecoderListener):
                 self._stack.append(fb)
 
         ifb = IfBody()
-        with ifb.cm(
-            f"cpuif_rd_sel.{get_indexed_path(self._cpuif.exp.ds.top_node, node)} || cpuif_wr_sel.{get_indexed_path(self._cpuif.exp.ds.top_node, node)}"
-        ) as b:
-            b += self._cpuif.fanin(node)
+        with ifb.cm(f"cpuif_wr_sel.{get_indexed_path(self._cpuif.exp.ds.top_node, node)}") as b:
+            b += self._cpuif.fanin_wr(node)
         self._stack[-1] += ifb
 
         ifb = IfBody()
         with ifb.cm(f"cpuif_rd_sel.{get_indexed_path(self._cpuif.exp.ds.top_node, node)}") as b:
-            b += self._cpuif.readback(node)
+            b += self._cpuif.fanin_rd(node)
         self._stack[-1] += ifb
 
         return action
@@ -72,4 +70,14 @@ class FaninGenerator(BusDecoderListener):
         super().exit_AddressableComponent(node)
 
     def __str__(self) -> str:
+        wr_ifb = IfBody()
+        with wr_ifb.cm("cpuif_wr_sel.cpuif_err") as b:
+            self._cpuif.fanin_wr(error=True)
+        self._stack[-1] += wr_ifb
+
+        rd_ifb = IfBody()
+        with rd_ifb.cm("cpuif_rd_sel.cpuif_err") as b:
+            self._cpuif.fanin_rd(error=True)
+        self._stack[-1] += rd_ifb
+
         return "\n".join(map(str, self._stack))

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/src/peakrdl_busdecoder/cpuif/interface.py

@@ -78,7 +78,7 @@ class SVInterface(Interface):
 
             # When unrolled, current_idx is set - append it to the name
             if child.current_idx is not None:
-                base = f"{base}_{'_'.join(map(str, child.current_idx))}"
+                base = f"{base}_{'_'.join(map(str, child.current_idx))}"  # ty: ignore
 
             # Only add array dimensions if this should be treated as an array
             if self.cpuif.check_is_array(child):

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/src/peakrdl_busdecoder/exporter.py

@@ -58,9 +58,9 @@ class BusDecoderExporter:
             loader=c_loader,
             undefined=jj.StrictUndefined,
         )
-        self.jj_env.filters["kwf"] = kwf  # type: ignore
-        self.jj_env.filters["walk"] = self.walk  # type: ignore
-        self.jj_env.filters["clog2"] = clog2  # type: ignore
+        self.jj_env.filters["kwf"] = kwf
+        self.jj_env.filters["walk"] = self.walk
+        self.jj_env.filters["clog2"] = clog2
 
     def export(self, node: RootNode | AddrmapNode, output_dir: str, **kwargs: Unpack[ExporterKwargs]) -> None:
         """
@@ -98,7 +98,7 @@ class BusDecoderExporter:
         else:
             top_node = node
 
-        self.ds = DesignState(top_node, kwargs)
+        self.ds = DesignState(top_node, kwargs)  # ty: ignore
 
         cpuif_cls: type[BaseCpuif] = kwargs.pop("cpuif_cls", None) or APB4Cpuif
 
@@ -113,7 +113,7 @@ class BusDecoderExporter:
         DesignValidator(self).do_validate()
 
         # Build Jinja template context
-        context = {  # type: ignore
+        context = {
             "version": version("peakrdl-busdecoder"),
             "cpuif": self.cpuif,
             "cpuif_decode": DecodeLogicGenerator,

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/src/peakrdl_busdecoder/utils.py

@@ -62,7 +62,6 @@ def ref_is_internal(top_node: AddrmapNode, ref: Node | PropertyReference) -> boo
     else:
         current_node = ref
 
-    # pyrefly: ignore[bad-assignment] - false positive due to circular type checking
     while current_node is not None:
         if current_node == top_node:
             # reached top node without finding any external components

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/src/peakrdl_busdecoder/validate_design.py

@@ -74,7 +74,9 @@ class DesignValidator(RDLListener):
                 f"instance '{node.inst_name}' must be a multiple of {alignment}",
                 node.inst.inst_src_ref,
             )
-        if node.is_array and (node.array_stride % alignment) != 0:  # type: ignore # is_array implies stride is not none
+        if node.is_array and (
+            node.array_stride is not None and (node.array_stride % alignment) != 0
+        ):  # is_array implies stride is not none
             self.msg.error(
                 "Unaligned registers are not supported. Address stride of "
                 f"instance array '{node.inst_name}' must be a multiple of {alignment}",

{peakrdl_busdecoder-0.6.4 → peakrdl_busdecoder-0.6.6}/src/peakrdl_busdecoder.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: peakrdl-busdecoder
-Version: 0.6.4
+Version: 0.6.6
 Summary: Generate a SystemVerilog bus decoder from SystemRDL for splitting CPU interfaces to multiple sub-address spaces
 Author: Arnav Sacheti
 License: LGPLv3