peakrdl-busdecoder 0.6.0__tar.gz → 0.6.3__tar.gz

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/.github/workflows/test.yml

@@ -45,6 +45,15 @@ jobs:
       - name: Run tests
         run: uv run pytest tests/ --cov=peakrdl_busdecoder --cov-report=xml --cov-report=term
       
+      - name: Upload coverage to Coveralls
+        if: matrix.python-version == '3.12'
+        env:
+          COVERALLS_REPO_TOKEN: ${{ secrets.COVERALLS_REPO_TOKEN }}
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+        run: |
+          uv pip install coveralls
+          uv run coveralls --service=github
+      
       - name: Upload coverage to Codecov
         uses: codecov/codecov-action@v4
         if: matrix.python-version == '3.12'

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: peakrdl-busdecoder
-Version: 0.6.0
+Version: 0.6.3
 Summary: Generate a SystemVerilog bus decoder from SystemRDL for splitting CPU interfaces to multiple sub-address spaces
 Author: Arnav Sacheti
 License: LGPLv3
@@ -26,9 +26,10 @@ Provides-Extra: cli
 Requires-Dist: peakrdl-cli>=1.2.3; extra == "cli"
 Dynamic: license-file
 
-[![Documentation Status](https://readthedocs.org/projects/peakrdl-busdecoder/badge/?version=latest)](http://peakrdl-busdecoder.readthedocs.io)
-[![build](https://github.com/arnavsacheti/PeakRDL-BusDecoder/workflows/build/badge.svg)](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions?query=workflow%3Abuild+branch%3Amain)
-[![Coverage Status](https://coveralls.io/repos/github/arnavsacheti/PeakRDL-BusDecoder/badge.svg?branch=main)](https://coveralls.io/github/arnavsacheti/PeakRDL-BusDecoder?branch=main)
+[![Build](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/build.yml/badge.svg)](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/build.yml)
+[![Test](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/test.yml/badge.svg)](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/test.yml)
+[![Documentation](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/docs.yml/badge.svg)](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/docs.yml)
+[![Coverage Status](https://coveralls.io/repos/github/arnavsacheti/PeakRDL-BusDecoder/badge.svg?branch=tests/coveralls)](https://coveralls.io/github/arnavsacheti/PeakRDL-BusDecoder?branch=tests/coveralls)
 [![PyPI - Python Version](https://img.shields.io/pypi/pyversions/peakrdl-busdecoder.svg)](https://pypi.org/project/peakrdl-busdecoder)
 
 # PeakRDL-BusDecoder

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/README.md

@@ -1,6 +1,7 @@
-[![Documentation Status](https://readthedocs.org/projects/peakrdl-busdecoder/badge/?version=latest)](http://peakrdl-busdecoder.readthedocs.io)
-[![build](https://github.com/arnavsacheti/PeakRDL-BusDecoder/workflows/build/badge.svg)](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions?query=workflow%3Abuild+branch%3Amain)
-[![Coverage Status](https://coveralls.io/repos/github/arnavsacheti/PeakRDL-BusDecoder/badge.svg?branch=main)](https://coveralls.io/github/arnavsacheti/PeakRDL-BusDecoder?branch=main)
+[![Build](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/build.yml/badge.svg)](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/build.yml)
+[![Test](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/test.yml/badge.svg)](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/test.yml)
+[![Documentation](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/docs.yml/badge.svg)](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/docs.yml)
+[![Coverage Status](https://coveralls.io/repos/github/arnavsacheti/PeakRDL-BusDecoder/badge.svg?branch=tests/coveralls)](https://coveralls.io/github/arnavsacheti/PeakRDL-BusDecoder?branch=tests/coveralls)
 [![PyPI - Python Version](https://img.shields.io/pypi/pyversions/peakrdl-busdecoder.svg)](https://pypi.org/project/peakrdl-busdecoder)
 
 # PeakRDL-BusDecoder

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/pyproject.toml

@@ -4,7 +4,7 @@ build-backend = "setuptools.build_meta"
 
 [project]
 name = "peakrdl-busdecoder"
-version = "0.6.0"
+version = "0.6.3"
 requires-python = ">=3.10"
 dependencies = [
     "jinja2~=3.1",

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/src/peakrdl_busdecoder/cpuif/apb3/apb3_cpuif.py

@@ -1,3 +1,4 @@
+from collections import deque
 from typing import TYPE_CHECKING, overload
 
 from systemrdl.node import AddressableNode
@@ -32,7 +33,7 @@ class APB3Cpuif(BaseCpuif):
     def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
         return self._interface.signal(signal, node, indexer)
 
-    def fanout(self, node: AddressableNode) -> str:
+    def fanout(self, node: AddressableNode, array_stack: deque[int]) -> str:
         fanout: dict[str, str] = {}
         fanout[self.signal("PSEL", node, "gi")] = (
             f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/src/peakrdl_busdecoder/cpuif/apb3/apb3_cpuif_flat.py

@@ -1,8 +1,10 @@
+from collections import deque
 from typing import TYPE_CHECKING
 
 from systemrdl.node import AddressableNode
 
-from ...utils import get_indexed_path
+from ...sv_int import SVInt
+from ...utils import clog2, get_indexed_path
 from ..base_cpuif import BaseCpuif
 from .apb3_interface import APB3FlatInterface
 
@@ -33,8 +35,12 @@ class APB3CpuifFlat(BaseCpuif):
     ) -> str:
         return self._interface.signal(signal, node, idx)
 
-    def fanout(self, node: AddressableNode) -> str:
+    def fanout(self, node: AddressableNode, array_stack: deque[int]) -> str:
         fanout: dict[str, str] = {}
+        addr_comp = [f"{self.signal('PADDR')}"]
+        for i, stride in enumerate(array_stack):
+            addr_comp.append(f"(gi{i}*{SVInt(stride, self.addr_width)})")
+
         fanout[self.signal("PSEL", node, "gi")] = (
             f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
         )
@@ -42,7 +48,7 @@ class APB3CpuifFlat(BaseCpuif):
         fanout[self.signal("PWRITE", node, "gi")] = (
             f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
         )
-        fanout[self.signal("PADDR", node, "gi")] = self.signal("PADDR")
+        fanout[self.signal("PADDR", node, "gi")] = f"{{{'-'.join(addr_comp)}}}[{clog2(node.size) - 1}:0]"
         fanout[self.signal("PWDATA", node, "gi")] = "cpuif_wr_data"
 
         return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/src/peakrdl_busdecoder/cpuif/apb3/apb3_interface.py

@@ -2,6 +2,7 @@
 
 from systemrdl.node import AddressableNode
 
+from ...utils import clog2
 from ..interface import FlatInterface, SVInterface
 
 
@@ -48,7 +49,7 @@ class APB3FlatInterface(FlatInterface):
             f"output logic {self.signal('PSEL', child)}",
             f"output logic {self.signal('PENABLE', child)}",
             f"output logic {self.signal('PWRITE', child)}",
-            f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('PADDR', child)}",
+            f"output logic [{clog2(child.size) - 1}:0] {self.signal('PADDR', child)}",
             f"output logic [{self.cpuif.data_width - 1}:0] {self.signal('PWDATA', child)}",
             f"input  logic [{self.cpuif.data_width - 1}:0] {self.signal('PRDATA', child)}",
             f"input  logic {self.signal('PREADY', child)}",

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/src/peakrdl_busdecoder/cpuif/apb4/apb4_cpuif.py

@@ -1,3 +1,4 @@
+from collections import deque
 from typing import TYPE_CHECKING, overload
 
 from systemrdl.node import AddressableNode
@@ -33,7 +34,7 @@ class APB4Cpuif(BaseCpuif):
     def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
         return self._interface.signal(signal, node, indexer)
 
-    def fanout(self, node: AddressableNode) -> str:
+    def fanout(self, node: AddressableNode, array_stack: deque[int]) -> str:
         fanout: dict[str, str] = {}
         fanout[self.signal("PSEL", node, "gi")] = (
             f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/src/peakrdl_busdecoder/cpuif/apb4/apb4_cpuif_flat.py

@@ -1,8 +1,10 @@
+from collections import deque
 from typing import TYPE_CHECKING
 
 from systemrdl.node import AddressableNode
 
-from ...utils import get_indexed_path
+from ...sv_int import SVInt
+from ...utils import clog2, get_indexed_path
 from ..base_cpuif import BaseCpuif
 from .apb4_interface import APB4FlatInterface
 
@@ -33,8 +35,12 @@ class APB4CpuifFlat(BaseCpuif):
     ) -> str:
         return self._interface.signal(signal, node, idx)
 
-    def fanout(self, node: AddressableNode) -> str:
+    def fanout(self, node: AddressableNode, array_stack: deque[int]) -> str:
         fanout: dict[str, str] = {}
+        addr_comp = [f"{self.signal('PADDR')}"]
+        for i, stride in enumerate(array_stack):
+            addr_comp.append(f"(gi{i}*{SVInt(stride, self.addr_width)})")
+
         fanout[self.signal("PSEL", node, "gi")] = (
             f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
         )
@@ -42,7 +48,7 @@ class APB4CpuifFlat(BaseCpuif):
         fanout[self.signal("PWRITE", node, "gi")] = (
             f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
         )
-        fanout[self.signal("PADDR", node, "gi")] = self.signal("PADDR")
+        fanout[self.signal("PADDR", node, "gi")] = f"{{{'-'.join(addr_comp)}}}[{clog2(node.size) - 1}:0]"
         fanout[self.signal("PPROT", node, "gi")] = self.signal("PPROT")
         fanout[self.signal("PWDATA", node, "gi")] = "cpuif_wr_data"
         fanout[self.signal("PSTRB", node, "gi")] = "cpuif_wr_byte_en"

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/src/peakrdl_busdecoder/cpuif/apb4/apb4_interface.py

@@ -2,6 +2,7 @@
 
 from systemrdl.node import AddressableNode
 
+from ...utils import clog2
 from ..interface import FlatInterface, SVInterface
 
 
@@ -50,7 +51,7 @@ class APB4FlatInterface(FlatInterface):
             f"output logic {self.signal('PSEL', child)}",
             f"output logic {self.signal('PENABLE', child)}",
             f"output logic {self.signal('PWRITE', child)}",
-            f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('PADDR', child)}",
+            f"output logic [{clog2(child.size) - 1}:0] {self.signal('PADDR', child)}",
             f"output logic [2:0] {self.signal('PPROT', child)}",
             f"output logic [{self.cpuif.data_width - 1}:0] {self.signal('PWDATA', child)}",
             f"output logic [{self.cpuif.data_width // 8 - 1}:0] {self.signal('PSTRB', child)}",

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv

@@ -6,8 +6,6 @@
         assert_bad_data_width: assert($bits({{cpuif.signal("PWDATA")}}) == {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH)
             else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("PWDATA")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
     end
-    assert_wr_sel: assert property (@(posedge {{cpuif.signal("PCLK")}}) {{cpuif.signal("PSEL")}} && {{cpuif.signal("PWRITE")}} |-> ##1 ({{cpuif.signal("PREADY")}} || {{cpuif.signal("PSLVERR")}}))
-        else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
 `endif
 {%- endif %}
 

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif.py

@@ -1,3 +1,4 @@
+from collections import deque
 from typing import TYPE_CHECKING, overload
 
 from systemrdl.node import AddressableNode
@@ -33,7 +34,7 @@ class AXI4LiteCpuif(BaseCpuif):
     def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
         return self._interface.signal(signal, node, indexer)
 
-    def fanout(self, node: AddressableNode) -> str:
+    def fanout(self, node: AddressableNode, array_stack: deque[int]) -> str:
         fanout: dict[str, str] = {}
 
         wr_sel = f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif_flat.py

@@ -1,8 +1,10 @@
+from collections import deque
 from typing import TYPE_CHECKING, overload
 
 from systemrdl.node import AddressableNode
 
-from ...utils import get_indexed_path
+from ...sv_int import SVInt
+from ...utils import clog2, get_indexed_path
 from ..base_cpuif import BaseCpuif
 from .axi4_lite_interface import AXI4LiteFlatInterface
 
@@ -35,15 +37,21 @@ class AXI4LiteCpuifFlat(BaseCpuif):
     def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
         return self._interface.signal(signal, node, indexer)
 
-    def fanout(self, node: AddressableNode) -> str:
+    def fanout(self, node: AddressableNode, array_stack: deque[int]) -> str:
         fanout: dict[str, str] = {}
+        waddr_comp = [f"{self.signal('AWADDR')}"]
+        raddr_comp = [f"{self.signal('ARADDR')}"]
+        for i, stride in enumerate(array_stack):
+            offset = f"(gi{i}*{SVInt(stride, self.addr_width)})"
+            waddr_comp.append(offset)
+            raddr_comp.append(offset)
 
         wr_sel = f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
         rd_sel = f"cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
 
         # Write address channel
         fanout[self.signal("AWVALID", node, "gi")] = wr_sel
-        fanout[self.signal("AWADDR", node, "gi")] = self.signal("AWADDR")
+        fanout[self.signal("AWADDR", node, "gi")] = f"{{{'-'.join(waddr_comp)}}}[{clog2(node.size) - 1}:0]"
         fanout[self.signal("AWPROT", node, "gi")] = self.signal("AWPROT")
 
         # Write data channel
@@ -56,7 +64,7 @@ class AXI4LiteCpuifFlat(BaseCpuif):
 
         # Read address channel
         fanout[self.signal("ARVALID", node, "gi")] = rd_sel
-        fanout[self.signal("ARADDR", node, "gi")] = self.signal("ARADDR")
+        fanout[self.signal("ARADDR", node, "gi")] = f"{{{'-'.join(raddr_comp)}}}[{clog2(node.size) - 1}:0]"
         fanout[self.signal("ARPROT", node, "gi")] = self.signal("ARPROT")
 
         # Read data channel (master -> slave)

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_interface.py

@@ -2,6 +2,7 @@
 
 from systemrdl.node import AddressableNode
 
+from ...utils import clog2
 from ..interface import FlatInterface, SVInterface
 
 
@@ -60,7 +61,7 @@ class AXI4LiteFlatInterface(FlatInterface):
             # Write address channel
             f"output logic {self.signal('AWVALID', child)}",
             f"input  logic {self.signal('AWREADY', child)}",
-            f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('AWADDR', child)}",
+            f"output logic [{clog2(child.size) - 1}:0] {self.signal('AWADDR', child)}",
             f"output logic [2:0] {self.signal('AWPROT', child)}",
             # Write data channel
             f"output logic {self.signal('WVALID', child)}",
@@ -74,7 +75,7 @@ class AXI4LiteFlatInterface(FlatInterface):
             # Read address channel
             f"output logic {self.signal('ARVALID', child)}",
             f"input  logic {self.signal('ARREADY', child)}",
-            f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('ARADDR', child)}",
+            f"output logic [{clog2(child.size) - 1}:0] {self.signal('ARADDR', child)}",
             f"output logic [2:0] {self.signal('ARPROT', child)}",
             # Read data channel
             f"input  logic {self.signal('RVALID', child)}",

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/src/peakrdl_busdecoder/cpuif/base_cpuif.py

@@ -1,5 +1,6 @@
 import inspect
 import os
+from collections import deque
 from typing import TYPE_CHECKING
 
 import jinja2 as jj
@@ -106,7 +107,7 @@ class BaseCpuif:
 
         return f"({cpuif_addr} - 'h{addr:x})[{clog2(size) - 1}:0]"
 
-    def fanout(self, node: AddressableNode) -> str:
+    def fanout(self, node: AddressableNode, array_stack: deque[int]) -> str:
         raise NotImplementedError
 
     def fanin(self, node: AddressableNode | None = None) -> str:

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/src/peakrdl_busdecoder/cpuif/fanout_gen.py

@@ -43,7 +43,7 @@ class FanoutGenerator(BusDecoderListener):
                 )
                 self._stack.append(fb)
 
-        self._stack[-1] += self._cpuif.fanout(node)
+        self._stack[-1] += self._cpuif.fanout(node, self._array_stride_stack)
 
         return action
 

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/src/peakrdl_busdecoder/validate_design.py

@@ -4,7 +4,7 @@ from systemrdl.node import AddressableNode, AddrmapNode, FieldNode, Node, Regfil
 from systemrdl.rdltypes.references import PropertyReference
 from systemrdl.walker import RDLListener, RDLWalker, WalkerAction
 
-from .utils import is_pow2, ref_is_internal, roundup_pow2
+from .utils import ref_is_internal
 
 if TYPE_CHECKING:
     from .exporter import BusDecoderExporter
@@ -159,27 +159,3 @@ class DesignValidator(RDLListener):
             else:
                 # Exiting top addrmap. Resolve final answer
                 self.contains_external_block = contains_external_block
-
-            if contains_external_block:
-                # Check that addressing follows strict alignment rules to allow
-                # for simplified address bit-pruning
-                if node.external:
-                    err_suffix = "is external"
-                else:
-                    err_suffix = "contains an external addrmap/regfile/mem"
-
-                req_align = roundup_pow2(node.size)
-                if (node.raw_address_offset % req_align) != 0:
-                    self.msg.error(
-                        f"Address offset +0x{node.raw_address_offset:x} of instance '{node.inst_name}' is not a power of 2 multiple of its size 0x{node.size:x}. "
-                        f"This is required by the busdecoder exporter if a component {err_suffix}.",
-                        node.inst.inst_src_ref,
-                    )
-                if node.is_array:
-                    assert node.array_stride is not None
-                    if not is_pow2(node.array_stride):
-                        self.msg.error(
-                            f"Address stride of instance array '{node.inst_name}' is not a power of 2"
-                            f"This is required by the busdecoder exporter if a component {err_suffix}.",
-                            node.inst.inst_src_ref,
-                        )

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/src/peakrdl_busdecoder.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: peakrdl-busdecoder
-Version: 0.6.0
+Version: 0.6.3
 Summary: Generate a SystemVerilog bus decoder from SystemRDL for splitting CPU interfaces to multiple sub-address spaces
 Author: Arnav Sacheti
 License: LGPLv3
@@ -26,9 +26,10 @@ Provides-Extra: cli
 Requires-Dist: peakrdl-cli>=1.2.3; extra == "cli"
 Dynamic: license-file
 
-[![Documentation Status](https://readthedocs.org/projects/peakrdl-busdecoder/badge/?version=latest)](http://peakrdl-busdecoder.readthedocs.io)
-[![build](https://github.com/arnavsacheti/PeakRDL-BusDecoder/workflows/build/badge.svg)](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions?query=workflow%3Abuild+branch%3Amain)
-[![Coverage Status](https://coveralls.io/repos/github/arnavsacheti/PeakRDL-BusDecoder/badge.svg?branch=main)](https://coveralls.io/github/arnavsacheti/PeakRDL-BusDecoder?branch=main)
+[![Build](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/build.yml/badge.svg)](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/build.yml)
+[![Test](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/test.yml/badge.svg)](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/test.yml)
+[![Documentation](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/docs.yml/badge.svg)](https://github.com/arnavsacheti/PeakRDL-BusDecoder/actions/workflows/docs.yml)
+[![Coverage Status](https://coveralls.io/repos/github/arnavsacheti/PeakRDL-BusDecoder/badge.svg?branch=tests/coveralls)](https://coveralls.io/github/arnavsacheti/PeakRDL-BusDecoder?branch=tests/coveralls)
 [![PyPI - Python Version](https://img.shields.io/pypi/pyversions/peakrdl-busdecoder.svg)](https://pypi.org/project/peakrdl-busdecoder)
 
 # PeakRDL-BusDecoder

{peakrdl_busdecoder-0.6.0 → peakrdl_busdecoder-0.6.3}/uv.lock

@@ -608,7 +608,7 @@ wheels = [
 
 [[package]]
 name = "peakrdl-busdecoder"
-version = "0.6.0"
+version = "0.6.3"
 source = { editable = "." }
 dependencies = [
     { name = "jinja2" },