pathsim 0.22.0__tar.gz → 0.22.2__tar.gz

{pathsim-0.22.0 → pathsim-0.22.2}/.github/workflows/pypi_deployment.yml

@@ -12,12 +12,12 @@ jobs:
   deploy:
     runs-on: ubuntu-latest  
     steps:
-    - uses: actions/checkout@v4
+    - uses: actions/checkout@v6
       with:
         fetch-depth: 0 
     
     - name: Set up Python
-      uses: actions/setup-python@v5
+      uses: actions/setup-python@v6
       with:
         python-version: '3.x'
     

{pathsim-0.22.0 → pathsim-0.22.2}/.github/workflows/tests_codecov.yml

@@ -4,9 +4,9 @@ jobs:
   test:
     runs-on: ubuntu-latest
     steps:
-      - uses: actions/checkout@v4
+      - uses: actions/checkout@v6
       - name: Set up Python
-        uses: actions/setup-python@v5
+        uses: actions/setup-python@v6
         with:
           python-version: '3.x'
       - name: Install dependencies

{pathsim-0.22.0 → pathsim-0.22.2}/.github/workflows/urlchecker.yml

@@ -8,7 +8,7 @@ jobs:
     runs-on: ubuntu-latest
 
     steps:
-    - uses: actions/checkout@v4
+    - uses: actions/checkout@v6
     - name: urls-checker
       uses: urlstechie/urlchecker-action@master
       with:

{pathsim-0.22.0 → pathsim-0.22.2}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: pathsim
-Version: 0.22.0
+Version: 0.22.2
 Summary: A differentiable block based hybrid system simulation framework.
 Author-email: Milan Rother <milan.rother@gmx.de>
 License: MIT
@@ -18,14 +18,14 @@ Requires-Dist: matplotlib>=3.1
 Requires-Dist: scipy>=1.2
 Provides-Extra: rf
 Requires-Dist: scikit-rf; extra == "rf"
+Provides-Extra: fmi
+Requires-Dist: FMPy; extra == "fmi"
 Provides-Extra: test
 Requires-Dist: pytest; extra == "test"
 Requires-Dist: pytest-cov; extra == "test"
 Requires-Dist: pytest-xdist; extra == "test"
 Requires-Dist: FMPy; extra == "test"
 Requires-Dist: scikit-rf; extra == "test"
-Provides-Extra: fmi
-Requires-Dist: FMPy; extra == "fmi"
 Dynamic: license-file
 
 <p align="center">

{pathsim-0.22.0 → pathsim-0.22.2}/pyproject.toml

@@ -19,9 +19,12 @@ requires-python = ">=3.8"
 dependencies = ["numpy>=1.15", "matplotlib>=3.1", "scipy>=1.2"]
 
 [project.optional-dependencies]
+# Both `rf` and `fmi` are deprecated as of v0.22 — the corresponding blocks
+# have moved to their own toolboxes (pathsim-rf, pathsim-fmi) and the extras
+# will be removed in v1.0.0. Install the toolboxes directly instead.
 rf = ["scikit-rf"]
-test = ["pytest", "pytest-cov", "pytest-xdist", "FMPy", "scikit-rf"]
 fmi = ["FMPy"]
+test = ["pytest", "pytest-cov", "pytest-xdist", "FMPy", "scikit-rf"]
 
 [project.urls]
 Homepage = "https://github.com/pathsim/pathsim"

{pathsim-0.22.0 → pathsim-0.22.2}/src/pathsim/_version.py

@@ -18,7 +18,7 @@ version_tuple: tuple[int | str, ...]
 commit_id: str | None
 __commit_id__: str | None
 
-__version__ = version = '0.22.0'
-__version_tuple__ = version_tuple = (0, 22, 0)
+__version__ = version = '0.22.2'
+__version_tuple__ = version_tuple = (0, 22, 2)
 
-__commit_id__ = commit_id = 'gfca397858'
+__commit_id__ = commit_id = 'gcb3b9ab4b'

{pathsim-0.22.0 → pathsim-0.22.2}/src/pathsim/blocks/_block.py

@@ -18,6 +18,32 @@ from ..utils.register import Register
 from ..utils.portreference import PortReference
 
 
+# HELPERS ===============================================================================
+
+def _labels_size(labels):
+    """Minimum register size required to hold all declared port labels.
+
+    Port labels map string aliases to integer port indices. The register has
+    to be large enough to address the highest declared index, otherwise blocks
+    with unconnected declared ports (e.g. a multi-input block placed without
+    connections) would default to the size 1 register and break positional
+    input access.
+
+    Parameters
+    ----------
+    labels : dict[str: int] | None
+        port label mapping (alias -> index)
+
+    Returns
+    -------
+    size : int | None
+        minimum register size, or None if no labels are declared
+    """
+    if not labels:
+        return None
+    return max(labels.values()) + 1
+
+
 # BASE BLOCK CLASS ======================================================================
 
 class Block:
@@ -84,11 +110,14 @@ class Block:
 
     def __init__(self):
 
-        #registers to hold input and output values
+        #registers to hold input and output values, pre-sized to the declared
+        #port labels so blocks with unconnected ports are still addressable
         self.inputs = Register(
+            size=_labels_size(self.input_port_labels),
             mapping=self.input_port_labels and self.input_port_labels.copy()
             )
         self.outputs = Register(
+            size=_labels_size(self.output_port_labels),
             mapping=self.output_port_labels and self.output_port_labels.copy()
             )
 

{pathsim-0.22.0 → pathsim-0.22.2}/src/pathsim/blocks/fmu.py

@@ -15,10 +15,16 @@ from .dynsys import DynamicalSystem
 from ..events.schedule import Schedule, ScheduleList
 from ..events.zerocrossing import ZeroCrossing
 from ..utils.fmuwrapper import FMUWrapper
+from ..utils.deprecation import deprecated
 
 
 # BLOCKS ================================================================================
 
+@deprecated(
+    version="1.0.0",
+    replacement="pathsim_fmi.CoSimulationFMU",
+    reason="This block has moved to the pathsim-fmi package: pip install pathsim-fmi",
+)
 class CoSimulationFMU(Block):
     """Co-Simulation FMU block using FMPy with support for FMI 2.0 and FMI 3.0.
 
@@ -105,6 +111,11 @@ class CoSimulationFMU(Block):
         return 0
 
 
+@deprecated(
+    version="1.0.0",
+    replacement="pathsim_fmi.ModelExchangeFMU",
+    reason="This block has moved to the pathsim-fmi package: pip install pathsim-fmi",
+)
 class ModelExchangeFMU(DynamicalSystem):
     """Model Exchange FMU block using FMPy with support for FMI 2.0 and FMI 3.0.
 

{pathsim-0.22.0 → pathsim-0.22.2}/src/pathsim/simulation.py

@@ -691,16 +691,17 @@ class Simulation:
         for block in self.blocks:
             block.inputs.reset()
 
+        #resolve all port indices so input/output registers are sized before
+        #graph assembly evaluates block passthrough via len(block) and before
+        #any block.update() runs (see Connection.resolve_ports)
+        for con in self.connections:
+            con.resolve_ports()
+
         #time the graph construction
         with Timer(verbose=False) as T:
             self.graph = Graph(self.blocks, self.connections)
         self._graph_dirty = False
 
-        #resolve all port indices so input/output registers are sized
-        #before any block.update() runs (see Connection.resolve_ports)
-        for con in self.connections:
-            con.resolve_ports()
-
         #create boosters for loop closing connections
         if self.graph.has_loops:
             self.boosters = [

{pathsim-0.22.0 → pathsim-0.22.2}/src/pathsim.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: pathsim
-Version: 0.22.0
+Version: 0.22.2
 Summary: A differentiable block based hybrid system simulation framework.
 Author-email: Milan Rother <milan.rother@gmx.de>
 License: MIT
@@ -18,14 +18,14 @@ Requires-Dist: matplotlib>=3.1
 Requires-Dist: scipy>=1.2
 Provides-Extra: rf
 Requires-Dist: scikit-rf; extra == "rf"
+Provides-Extra: fmi
+Requires-Dist: FMPy; extra == "fmi"
 Provides-Extra: test
 Requires-Dist: pytest; extra == "test"
 Requires-Dist: pytest-cov; extra == "test"
 Requires-Dist: pytest-xdist; extra == "test"
 Requires-Dist: FMPy; extra == "test"
 Requires-Dist: scikit-rf; extra == "test"
-Provides-Extra: fmi
-Requires-Dist: FMPy; extra == "fmi"
 Dynamic: license-file
 
 <p align="center">

{pathsim-0.22.0 → pathsim-0.22.2}/tests/pathsim/blocks/test_block.py

@@ -254,6 +254,33 @@ class TestBlock(unittest.TestCase):
         self.assertEqual(cache_info.misses, 1)
 
 
+    def test_register_sizing_from_port_labels(self):
+        """Registers are pre-sized to the declared port labels so blocks
+        with unconnected multi-port interfaces stay positionally addressable.
+        """
+
+        class _LabeledBlock(Block):
+            input_port_labels = {"a": 0, "b": 1}
+            output_port_labels = {"x": 0, "y": 1, "z": 2}
+
+        B = _LabeledBlock()
+
+        #registers sized to highest declared index + 1
+        self.assertEqual(len(B.inputs), 2)
+        self.assertEqual(len(B.outputs), 3)
+
+        #shape reflects declared ports even without connections
+        self.assertEqual(B.shape, (2, 3))
+
+        #all declared ports addressable and zero-initialized
+        self.assertEqual(B.inputs["b"], 0.0)
+        self.assertEqual(B.outputs["z"], 0.0)
+
+        #blocks without port labels keep the default size 1 registers
+        self.assertEqual(len(Block().inputs), 1)
+        self.assertEqual(len(Block().outputs), 1)
+
+
 # RUN TESTS LOCALLY ====================================================================
 
 if __name__ == '__main__':