lnoi400 2.1.1__tar.gz

lnoi400-2.1.1/LICENSE

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2023-2026 Luxtelligence
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

lnoi400-2.1.1/PKG-INFO

@@ -0,0 +1,218 @@
+Metadata-Version: 2.4
+Name: lnoi400
+Version: 2.1.1
+Summary: Luxtelligence gdsfactory PDK
+Author-email: Luxtelligence <foundry@luxtelligence.ai>
+License: MIT License
+        
+        Copyright (c) 2023-2026 Luxtelligence
+        
+        Permission is hereby granted, free of charge, to any person obtaining a copy
+        of this software and associated documentation files (the "Software"), to deal
+        in the Software without restriction, including without limitation the rights
+        to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+        copies of the Software, and to permit persons to whom the Software is
+        furnished to do so, subject to the following conditions:
+        
+        The above copyright notice and this permission notice shall be included in all
+        copies or substantial portions of the Software.
+        
+        THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+        IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+        FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+        AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+        LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+        OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+        SOFTWARE.
+        
+Keywords: python
+Classifier: Programming Language :: Python :: 3.11
+Classifier: Programming Language :: Python :: 3.12
+Classifier: Operating System :: OS Independent
+Requires-Python: ~=3.12.0
+Description-Content-Type: text/markdown
+License-File: LICENSE
+Requires-Dist: gdsfactory~=9.51.0
+Requires-Dist: gdsfactoryplus
+Requires-Dist: gplugins[sax]~=2.1.0
+Provides-Extra: dev
+Requires-Dist: pre-commit; extra == "dev"
+Requires-Dist: pytest; extra == "dev"
+Requires-Dist: pytest-cov; extra == "dev"
+Requires-Dist: pytest_regressions; extra == "dev"
+Requires-Dist: towncrier; extra == "dev"
+Provides-Extra: docs
+Requires-Dist: jupyter; extra == "docs"
+Requires-Dist: mkdocs-material; extra == "docs"
+Requires-Dist: mkdocs-with-pdf; extra == "docs"
+Requires-Dist: nbconvert; extra == "docs"
+Requires-Dist: mkdocstrings[python]>=0.27.0; extra == "docs"
+Requires-Dist: zensical<0.1.0,>=0.0.40; extra == "docs"
+Dynamic: license-file
+
+# Luxtelligence Process Design Kit (PDK) for gdsfactory
+
+Luxtelligence's PDK is built on a lithium tantalate/lithium niobate electro-optic platform, leveraging their large Pockels coefficients for high-speed modulation.
+
+<!-- BADGES:START -->
+[![Docs](https://github.com/gdsfactory/lxt_pdk_gf/actions/workflows/pages.yml/badge.svg)](https://github.com/gdsfactory/lxt_pdk_gf/actions/workflows/pages.yml)
+[![Tests](https://github.com/gdsfactory/lxt_pdk_gf/actions/workflows/test_code.yml/badge.svg)](https://github.com/gdsfactory/lxt_pdk_gf/actions/workflows/test_code.yml)
+[![DRC](https://github.com/gdsfactory/lxt_pdk_gf/raw/badges/drc.svg)](https://github.com/gdsfactory/lxt_pdk_gf/actions/workflows/drc.yml)
+[![Model Regression](https://github.com/gdsfactory/lxt_pdk_gf/actions/workflows/model_regression.yml/badge.svg)](https://github.com/gdsfactory/lxt_pdk_gf/actions/workflows/model_regression.yml)
+[![Test Coverage](https://github.com/gdsfactory/lxt_pdk_gf/raw/badges/coverage.svg)](https://github.com/gdsfactory/lxt_pdk_gf/actions/workflows/test_coverage.yml)
+[![Model Coverage](https://github.com/gdsfactory/lxt_pdk_gf/raw/badges/model_coverage.svg)](https://github.com/gdsfactory/lxt_pdk_gf/actions/workflows/model_coverage.yml)
+[![Issues](https://github.com/gdsfactory/lxt_pdk_gf/raw/badges/issues.svg)](https://github.com/gdsfactory/lxt_pdk_gf/issues)
+[![PRs](https://github.com/gdsfactory/lxt_pdk_gf/raw/badges/prs.svg)](https://github.com/gdsfactory/lxt_pdk_gf/pulls)
+<!-- BADGES:END -->
+
+
+![Luxtelligence](LXT_Logo.png)
+
+[Luxtelligence](https://luxtelligence.ai/) Process Design Kit (PDK) for gdsfactory. The Luxtelligence PDK contains a library of components that facilitate the design of photonic integrated circuits for Luxtelligence's foundry service. The PDK includes both electrical and optical building blocks that leverage Lithium Tantalate and Lithium Niobate's electro-optic effect and attractive optical properties. Each building block consists of a geometrical layout, defining the starting point for microfabrication of the integrated circuit, and a compact circuit model that approximates the real frequency-domain behaviour of the component.
+
+The `lxt_pdk_gf` PDK is released open-source to allow users to easily evaluate a sample of what Luxtelligence has to offer. Please [contact us](mailto:foundry@luxtelligence.ai) for information on advanced building blocks and variations on the standard PDK geometry.
+
+## Installation
+
+We recommend [KLayout](https://www.klayout.de/) as a layout viewer and editor for GDS and OASIS files. gdsfactory itself is based on and closely integrated with KLayout.
+
+Python 3.12 is required. We recommend [VSCode](https://code.visualstudio.com/) or [Google Antigravity](https://antigravity.google/) as IDEs.
+
+If you do not have Python installed, you can [download Anaconda](https://www.anaconda.com/download/). Once Python is available, clone the repository and install the package in editable mode:
+
+```
+git clone https://github.com/Luxtelligence/lxt_pdk_gf.git
+cd lxt_pdk_gf
+pip install -e .
+python install_tech.py
+```
+
+Restart KLayout afterwards to ensure the newly installed technology appears.
+
+## KLayout Layer Properties
+
+Each PDK has a `klayout/` folder containing `.lyp` layer property files (e.g. `ltoi300/klayout/` and `lnoi400/klayout/`). These files define the colours, fill patterns, and display names for every process layer.
+
+To activate them in KLayout:
+
+1. Open KLayout and go to **File → Setup**.
+2. Navigate to the **Application** section and select **Layer Properties**.
+3. Under **Default layer properties file**, click **Browse** and point it to the `.lyp` file for your PDK (e.g. `lxt_pdk_gf/ltoi300/klayout/ltoi300.lyp`).
+4. Click **Apply** and **OK**. Restart KLayout to apply the changes.
+
+## KLayout DRC
+
+Design Rule Check (DRC) runsets for KLayout can be downloaded from [resources.luxtelligence.ai](https://resources.luxtelligence.ai/request-access?resource=drc). The files have a `.lydrc` extension and are specific to the technology stack you are using.
+
+**Installation:**
+
+Place the downloaded `.lydrc` file(s) in your local KLayout DRC folder:
+
+```
+<user home folder>/Klayout/drc/
+```
+
+> **Note:** KLayout has a known issue where only the first DRC file in the `drc/` folder is actually used. It is recommended to keep **only one `.lydrc` file** in that folder at a time. If you need to switch between DRC scripts for different stacks, simply replace the file.
+
+**Running the DRC in KLayout:**
+
+1. Open your GDS layout in KLayout.
+2. Go to **Tools → DRC**.
+3. Click **Edit DRC Script** and select the `.lydrc` file corresponding to your process stack.
+4. Run the script. The results will appear in a dedicated DRC results window, where violations are listed and can be highlighted in the layout.
+
+> **Important:** Not every flagged violation necessarily needs to be corrected — some rules may be advisory or context-dependent. Conversely, the DRC script does not guarantee that all possible design errors are caught. Always review results in the context of your specific design intent and consult Luxtelligence if in doubt.
+
+## Examples
+
+### Chip edge, singulation, and polishing
+
+For LNOI400 edge couplers, **the outside edge of layer 6/1
+(`CHIP_EXCLUSION_ZONE`) is the physical chip edge**. Layer 6/0
+(`CHIP_CONTOUR`) serves other layout purposes and does not define the
+straight tip extension.
+
+The coupler tip extends **5 µm outside layer 6/1**, regardless of the total
+straight tip length. At least **5 µm of constant-width straight** remains
+inside that edge for successful singulation:
+
+| Process | Total straight tip (`input_ext`) | Outside 6/1 | Inside 6/1 |
+| --- | --- | --- | --- |
+| Singulation without polishing | 10 µm | 5 µm | 5 µm |
+| Singulation with polishing allowance | Approximately 30 µm | 5 µm | Approximately 25 µm |
+
+The longer polishing option keeps the width at the polished facet constant.
+Do not use the longer straight by default when polishing is not planned:
+the large tip mode interacts with silicon over a longer distance, which can
+increase edge-coupler insertion loss. The required polishing allowance depends
+on the planned process; approximately 30 µm is a guide, not a predicted loss
+or a fixed polishing removal depth.
+
+`lnoi400.cells.die_phix_rf()` uses the standard LXT chip frame and the 10 µm
+straight tip by default. For polishing, keep the same 5 µm facet offset and
+change only the straight length:
+
+```python
+import lnoi400
+from lnoi400 import cells
+
+lnoi400.PDK.activate()
+die = cells.die_phix_rf(
+    edge_coupler={
+        "component": "double_linear_inverse_taper_mirror",
+        "settings": {"input_ext": 30.0},
+    },
+    fiber_coupler_xoffset=5.0,
+)
+```
+
+Both right and optional left coupler arrays use this outward offset from 6/1.
+Custom couplers must supply at least 10 µm of constant-width straight tip.
+The low-level unmirrored `double_linear_inverse_taper` retains its zero-extension
+default; set `input_ext` explicitly when using it at a singulated chip edge.
+
+The die wrapper follows `chip_frame` dimension restrictions: nominal dimensions
+of 5000, 10000, and 20000 µm map to layer-6/0 extents of 4950, 10000, and
+20100 µm respectively, within the frame's existing tolerances. A nominal
+5000-by-5000 µm die is unsupported. Layer 6/1 adds `exclusion_zone_width` on
+each side. Pad offsets remain referenced to layer 6/0.
+
+After installing the PDK, you can verify that it is working correctly by running the Jupyter notebooks in the [docs/notebooks](https://github.com/Luxtelligence/lxt_pdk_gf/tree/main/docs/notebooks) folder.
+
+## Documentation
+
+- [PDK documentation](https://luxtelligence.github.io/lxt_pdk_gf/)
+- [gdsfactory documentation](https://gdsfactory.github.io/gdsfactory/)
+
+## Pre-commit
+
+Pre-commit hooks are centrally maintained in [pdk-ci-workflow-public](https://github.com/doplaydo/pdk-ci-workflow-public). `make dev` fetches the canonical config and installs the git hook.
+
+```bash
+make dev
+```
+
+## Tests
+
+Run the test suite:
+
+```bash
+make test
+```
+
+## Release
+
+1. Bump the version:
+
+```bash
+tbump 0.0.1
+```
+
+2. Push the tag:
+
+```bash
+git push --tags
+```
+This triggers the release workflow that builds wheels and uploads them.
+
+3. Create a pull request with the updated changelog since last release.

lnoi400-2.1.1/README.md

@@ -0,0 +1,166 @@
+# Luxtelligence Process Design Kit (PDK) for gdsfactory
+
+Luxtelligence's PDK is built on a lithium tantalate/lithium niobate electro-optic platform, leveraging their large Pockels coefficients for high-speed modulation.
+
+<!-- BADGES:START -->
+[![Docs](https://github.com/gdsfactory/lxt_pdk_gf/actions/workflows/pages.yml/badge.svg)](https://github.com/gdsfactory/lxt_pdk_gf/actions/workflows/pages.yml)
+[![Tests](https://github.com/gdsfactory/lxt_pdk_gf/actions/workflows/test_code.yml/badge.svg)](https://github.com/gdsfactory/lxt_pdk_gf/actions/workflows/test_code.yml)
+[![DRC](https://github.com/gdsfactory/lxt_pdk_gf/raw/badges/drc.svg)](https://github.com/gdsfactory/lxt_pdk_gf/actions/workflows/drc.yml)
+[![Model Regression](https://github.com/gdsfactory/lxt_pdk_gf/actions/workflows/model_regression.yml/badge.svg)](https://github.com/gdsfactory/lxt_pdk_gf/actions/workflows/model_regression.yml)
+[![Test Coverage](https://github.com/gdsfactory/lxt_pdk_gf/raw/badges/coverage.svg)](https://github.com/gdsfactory/lxt_pdk_gf/actions/workflows/test_coverage.yml)
+[![Model Coverage](https://github.com/gdsfactory/lxt_pdk_gf/raw/badges/model_coverage.svg)](https://github.com/gdsfactory/lxt_pdk_gf/actions/workflows/model_coverage.yml)
+[![Issues](https://github.com/gdsfactory/lxt_pdk_gf/raw/badges/issues.svg)](https://github.com/gdsfactory/lxt_pdk_gf/issues)
+[![PRs](https://github.com/gdsfactory/lxt_pdk_gf/raw/badges/prs.svg)](https://github.com/gdsfactory/lxt_pdk_gf/pulls)
+<!-- BADGES:END -->
+
+
+![Luxtelligence](LXT_Logo.png)
+
+[Luxtelligence](https://luxtelligence.ai/) Process Design Kit (PDK) for gdsfactory. The Luxtelligence PDK contains a library of components that facilitate the design of photonic integrated circuits for Luxtelligence's foundry service. The PDK includes both electrical and optical building blocks that leverage Lithium Tantalate and Lithium Niobate's electro-optic effect and attractive optical properties. Each building block consists of a geometrical layout, defining the starting point for microfabrication of the integrated circuit, and a compact circuit model that approximates the real frequency-domain behaviour of the component.
+
+The `lxt_pdk_gf` PDK is released open-source to allow users to easily evaluate a sample of what Luxtelligence has to offer. Please [contact us](mailto:foundry@luxtelligence.ai) for information on advanced building blocks and variations on the standard PDK geometry.
+
+## Installation
+
+We recommend [KLayout](https://www.klayout.de/) as a layout viewer and editor for GDS and OASIS files. gdsfactory itself is based on and closely integrated with KLayout.
+
+Python 3.12 is required. We recommend [VSCode](https://code.visualstudio.com/) or [Google Antigravity](https://antigravity.google/) as IDEs.
+
+If you do not have Python installed, you can [download Anaconda](https://www.anaconda.com/download/). Once Python is available, clone the repository and install the package in editable mode:
+
+```
+git clone https://github.com/Luxtelligence/lxt_pdk_gf.git
+cd lxt_pdk_gf
+pip install -e .
+python install_tech.py
+```
+
+Restart KLayout afterwards to ensure the newly installed technology appears.
+
+## KLayout Layer Properties
+
+Each PDK has a `klayout/` folder containing `.lyp` layer property files (e.g. `ltoi300/klayout/` and `lnoi400/klayout/`). These files define the colours, fill patterns, and display names for every process layer.
+
+To activate them in KLayout:
+
+1. Open KLayout and go to **File → Setup**.
+2. Navigate to the **Application** section and select **Layer Properties**.
+3. Under **Default layer properties file**, click **Browse** and point it to the `.lyp` file for your PDK (e.g. `lxt_pdk_gf/ltoi300/klayout/ltoi300.lyp`).
+4. Click **Apply** and **OK**. Restart KLayout to apply the changes.
+
+## KLayout DRC
+
+Design Rule Check (DRC) runsets for KLayout can be downloaded from [resources.luxtelligence.ai](https://resources.luxtelligence.ai/request-access?resource=drc). The files have a `.lydrc` extension and are specific to the technology stack you are using.
+
+**Installation:**
+
+Place the downloaded `.lydrc` file(s) in your local KLayout DRC folder:
+
+```
+<user home folder>/Klayout/drc/
+```
+
+> **Note:** KLayout has a known issue where only the first DRC file in the `drc/` folder is actually used. It is recommended to keep **only one `.lydrc` file** in that folder at a time. If you need to switch between DRC scripts for different stacks, simply replace the file.
+
+**Running the DRC in KLayout:**
+
+1. Open your GDS layout in KLayout.
+2. Go to **Tools → DRC**.
+3. Click **Edit DRC Script** and select the `.lydrc` file corresponding to your process stack.
+4. Run the script. The results will appear in a dedicated DRC results window, where violations are listed and can be highlighted in the layout.
+
+> **Important:** Not every flagged violation necessarily needs to be corrected — some rules may be advisory or context-dependent. Conversely, the DRC script does not guarantee that all possible design errors are caught. Always review results in the context of your specific design intent and consult Luxtelligence if in doubt.
+
+## Examples
+
+### Chip edge, singulation, and polishing
+
+For LNOI400 edge couplers, **the outside edge of layer 6/1
+(`CHIP_EXCLUSION_ZONE`) is the physical chip edge**. Layer 6/0
+(`CHIP_CONTOUR`) serves other layout purposes and does not define the
+straight tip extension.
+
+The coupler tip extends **5 µm outside layer 6/1**, regardless of the total
+straight tip length. At least **5 µm of constant-width straight** remains
+inside that edge for successful singulation:
+
+| Process | Total straight tip (`input_ext`) | Outside 6/1 | Inside 6/1 |
+| --- | --- | --- | --- |
+| Singulation without polishing | 10 µm | 5 µm | 5 µm |
+| Singulation with polishing allowance | Approximately 30 µm | 5 µm | Approximately 25 µm |
+
+The longer polishing option keeps the width at the polished facet constant.
+Do not use the longer straight by default when polishing is not planned:
+the large tip mode interacts with silicon over a longer distance, which can
+increase edge-coupler insertion loss. The required polishing allowance depends
+on the planned process; approximately 30 µm is a guide, not a predicted loss
+or a fixed polishing removal depth.
+
+`lnoi400.cells.die_phix_rf()` uses the standard LXT chip frame and the 10 µm
+straight tip by default. For polishing, keep the same 5 µm facet offset and
+change only the straight length:
+
+```python
+import lnoi400
+from lnoi400 import cells
+
+lnoi400.PDK.activate()
+die = cells.die_phix_rf(
+    edge_coupler={
+        "component": "double_linear_inverse_taper_mirror",
+        "settings": {"input_ext": 30.0},
+    },
+    fiber_coupler_xoffset=5.0,
+)
+```
+
+Both right and optional left coupler arrays use this outward offset from 6/1.
+Custom couplers must supply at least 10 µm of constant-width straight tip.
+The low-level unmirrored `double_linear_inverse_taper` retains its zero-extension
+default; set `input_ext` explicitly when using it at a singulated chip edge.
+
+The die wrapper follows `chip_frame` dimension restrictions: nominal dimensions
+of 5000, 10000, and 20000 µm map to layer-6/0 extents of 4950, 10000, and
+20100 µm respectively, within the frame's existing tolerances. A nominal
+5000-by-5000 µm die is unsupported. Layer 6/1 adds `exclusion_zone_width` on
+each side. Pad offsets remain referenced to layer 6/0.
+
+After installing the PDK, you can verify that it is working correctly by running the Jupyter notebooks in the [docs/notebooks](https://github.com/Luxtelligence/lxt_pdk_gf/tree/main/docs/notebooks) folder.
+
+## Documentation
+
+- [PDK documentation](https://luxtelligence.github.io/lxt_pdk_gf/)
+- [gdsfactory documentation](https://gdsfactory.github.io/gdsfactory/)
+
+## Pre-commit
+
+Pre-commit hooks are centrally maintained in [pdk-ci-workflow-public](https://github.com/doplaydo/pdk-ci-workflow-public). `make dev` fetches the canonical config and installs the git hook.
+
+```bash
+make dev
+```
+
+## Tests
+
+Run the test suite:
+
+```bash
+make test
+```
+
+## Release
+
+1. Bump the version:
+
+```bash
+tbump 0.0.1
+```
+
+2. Push the tag:
+
+```bash
+git push --tags
+```
+This triggers the release workflow that builds wheels and uploads them.
+
+3. Create a pull request with the updated changelog since last release.

lnoi400-2.1.1/_utils/bends.py

@@ -0,0 +1,109 @@
+import gdsfactory as gf
+import numpy as np
+from gdsfactory.cross_section import (
+    CrossSection,
+)
+from gdsfactory.typings import CrossSectionSpec
+
+from _utils.spline import (
+    bend_S_spline,
+    spline_clamped_path,
+)
+
+
+def L_turn_bend(
+    radius: float = 80.0,
+    p: float = 1.0,
+    with_arc_floorplan: bool = True,
+    cross_section: CrossSectionSpec = "xs_rwg700",
+    **kwargs,
+) -> gf.Component:
+    """
+    A 90-degrees bend following an Euler path, with linearly-varying curvature
+    (increasing and decreasing).
+    """
+
+    npoints = int(np.round(200 * radius / 80.0))
+    angle = 90.0
+
+    return gf.components.bend_euler(
+        radius=radius,
+        angle=angle,
+        p=p,
+        with_arc_floorplan=with_arc_floorplan,
+        npoints=npoints,
+        cross_section=cross_section,
+        **kwargs,
+    )
+
+
+def S_bend_vert(
+    v_offset: float = 25.0,
+    h_extent: float = 100.0,
+    dx_straight: float = 5.0,
+    cross_section: CrossSectionSpec = "xs_rwg700",
+) -> gf.Component:
+    """A spline bend that bridges a vertical displacement."""
+
+    if np.abs(v_offset) < 10.0:
+        raise ValueError(
+            f"The vertical distance bridged by the S-bend ({v_offset}) is too small."
+        )
+
+    if np.abs(h_extent / v_offset) < 3.5 or h_extent < 90.0:
+        raise ValueError(
+            f"The bend would be too tight. Increase h_extent from its current value of {h_extent}."
+        )
+
+    S_bend = gf.components.extend_ports(
+        bend_S_spline(
+            size=(h_extent, v_offset),
+            cross_section=cross_section,
+            npoints=int(np.round(2.5 * h_extent)),
+            path_method=spline_clamped_path,
+        ),
+        length=dx_straight,
+        cross_section=cross_section,
+    )
+
+    bend_cell = gf.Component()
+    bend_ref = bend_cell << S_bend
+    bend_ref.dmove(bend_ref.ports["o1"].dcenter, (0.0, 0.0))
+    bend_cell.add_port(name="o1", port=bend_ref.ports["o1"])
+    bend_cell.add_port(name="o2", port=bend_ref.ports["o2"])
+    bend_cell.flatten()
+
+    return bend_cell
+
+
+def bend_euler_tapered(
+    radius: float = 45.0,
+    w0: float = 3.0,
+    wc: float = 1.0,
+    cross_section: CrossSection = None,
+) -> gf.Component:
+    """A tapered bend following an Euler path."""
+
+    euler_path = gf.path.euler(
+        radius=radius,
+        angle=180.0,
+        p=1,
+        use_eff=True,
+    )
+    euler_path.start_angle = 0.0
+    euler_path.end_angle = 180.0
+
+    def width_fun(t):
+        if any(t > 1) or any(t < 0):
+            raise ValueError()
+        y = np.zeros_like(t)
+        y[t <= 0.5] = w0 + (wc - w0) * 2 * t[t <= 0.5]
+        y[t > 0.5] = -(wc - w0) * 2 * t[t > 0.5] + 2 * wc - w0
+        return y
+
+    if not cross_section:
+        raise ValueError("cross_section is required")
+
+    xs_tapered = cross_section(width_function=width_fun)
+
+    return euler_path.extrude(cross_section=xs_tapered)

lnoi400-2.1.1/_utils/cell_info.py

@@ -0,0 +1,17 @@
+from gdsfactory import Component
+
+
+def copy_info(dst: Component, src: Component, prefix: str | None = None) -> None:
+    """Copy `src.info` entries into `dst.info` with a prefix.
+
+    By default, the prefix is derived from `src.function_name` when available.
+    """
+    if not hasattr(dst, "info") or not hasattr(src, "info"):
+        raise ValueError("Both dst and src must expose an 'info' attribute.")
+
+    src_prefix = prefix or getattr(src, "function_name", None) or "cell"
+    src_data = (
+        src.info.model_dump() if hasattr(src.info, "model_dump") else dict(src.info)
+    )
+
+    dst.info.update({f"{src_prefix}_{key}": value for key, value in src_data.items()})

lnoi400-2.1.1/_utils/chip_floorplan.py

@@ -0,0 +1,66 @@
+import gdsfactory as gf
+
+
+@gf.cell(tags=["chip_floorplan"])
+def chip_frame(
+    size: tuple[float, float] = (10_000, 5000),
+    exclusion_zone_width: float = 50,
+    center: tuple[float, float] = None,
+    chip_contour_layer: tuple[int, int] = (6, 0),
+    chip_exclusion_zone_layer: tuple[int, int] = (6, 1),
+) -> gf.Component:
+    """Provide the chip extent and the exclusion zone around the chip frame.
+
+    @tags lnoi400-chip-edge
+
+    The outside edge of chip_exclusion_zone_layer (6/1) is the physical chip
+    edge. chip_contour_layer (6/0) is a separate design contour, not the facet.
+    In the exclusion zone, only the edge couplers routing to the chip facet should be placed.
+    Allowed chip dimensions (in either direction): 5000 um, 10000 um, 20000 um."""
+
+    # Check that the chip dimensions have the admissible values.
+
+    snapped_size = []
+
+    if size[0] <= 5050 and size[1] <= 5050:
+        raise (ValueError(f"The chip frame size {size} is not supported."))
+
+    if size[0] > 20200 or size[1] > 20200:
+        raise (ValueError(f"The chip frame size {size} is not supported."))
+
+    else:
+        for s in size:
+            if abs(s - 5000.0) <= 50.0:
+                snapped_size.append(4950.0)
+            elif abs(s - 10000.0) <= 100.0:
+                snapped_size.append(10000)
+            elif abs(s - 20000.0) <= 200:
+                snapped_size.append(20100)
+            else:
+                raise (ValueError(f"The chip frame size {size} is not supported."))
+
+    # Chip frame elements
+
+    inner_box = gf.components.rectangle(
+        size=tuple(snapped_size),
+        layer=chip_contour_layer,
+        centered=True,
+    )
+
+    outer_box = gf.components.rectangle(
+        size=tuple(s + 2 * exclusion_zone_width for s in snapped_size),
+        layer=chip_exclusion_zone_layer,
+        centered=True,
+    )
+
+    c = gf.Component()
+    ib = c << inner_box
+    ob = c << outer_box
+
+    if center:
+        ib.dmove(origin=(0.0, 0.0), destination=center)
+        ob.dmove(origin=(0.0, 0.0), destination=center)
+
+    c.flatten()
+
+    return c