librelane 3.1.0.dev4__tar.gz → 3.1.0.dev5__tar.gz

{librelane-3.1.0.dev4 → librelane-3.1.0.dev5}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: librelane
-Version: 3.1.0.dev4
+Version: 3.1.0.dev5
 Summary: An infrastructure for implementing chip design flows
 License-Expression: Apache-2.0
 Maintainer: Mohamed Gaber
@@ -80,7 +80,7 @@ LibreLane includes two reference flows (`Classic` and `Chip`) that are built
 entirely using open-source EDA tools.
 
 You can find the documentation
-[here](https://librelane.readthedocs.io/en/latest/getting_started/) to get
+[here](https://librelane.readthedocs.io/en/stable/getting_started/) to get
 started. You can discuss LibreLane in the
 [FOSSi Chat Matrix Server](https://fossi-chat.org).
 
@@ -121,7 +121,7 @@ Works for macOS and Linux (x86-64 and aarch64). Recommended, as it is more
 integrated with your filesystem and overall has less upload and download deltas.
 
 See
-[Nix-based installation](https://librelane.readthedocs.io/en/latest/installation/nix_installation/index.html)
+[Nix-based installation](https://librelane.readthedocs.io/en/stable/installation/nix_installation/index.html)
 in the docs for more info.
 
 ### Docker
@@ -129,7 +129,7 @@ in the docs for more info.
 Works for Windows, macOS and Linux (x86-64 and aarch64).
 
 See
-[Docker-based installation](https://librelane.readthedocs.io/en/latest/installation/docker_installation/index.html)
+[Docker-based installation](https://librelane.readthedocs.io/en/stable/installation/docker_installation/index.html)
 in the docs for more info.
 
 Do note you'll need to add `--dockerized` right after `librelane` in most CLI
@@ -145,7 +145,9 @@ python3 -m pip install --upgrade librelane
 ```
 
 Python-only installations are presently unsupported and entirely at your own
-risk.
+risk, but you may consult
+[Manual installation](https://librelane.readthedocs.io/en/stable/installation/manual_installation/index.html)
+in the docs for more info.
 
 ## Usage
 

{librelane-3.1.0.dev4 → librelane-3.1.0.dev5}/Readme.md

@@ -45,7 +45,7 @@ LibreLane includes two reference flows (`Classic` and `Chip`) that are built
 entirely using open-source EDA tools.
 
 You can find the documentation
-[here](https://librelane.readthedocs.io/en/latest/getting_started/) to get
+[here](https://librelane.readthedocs.io/en/stable/getting_started/) to get
 started. You can discuss LibreLane in the
 [FOSSi Chat Matrix Server](https://fossi-chat.org).
 
@@ -86,7 +86,7 @@ Works for macOS and Linux (x86-64 and aarch64). Recommended, as it is more
 integrated with your filesystem and overall has less upload and download deltas.
 
 See
-[Nix-based installation](https://librelane.readthedocs.io/en/latest/installation/nix_installation/index.html)
+[Nix-based installation](https://librelane.readthedocs.io/en/stable/installation/nix_installation/index.html)
 in the docs for more info.
 
 ### Docker
@@ -94,7 +94,7 @@ in the docs for more info.
 Works for Windows, macOS and Linux (x86-64 and aarch64).
 
 See
-[Docker-based installation](https://librelane.readthedocs.io/en/latest/installation/docker_installation/index.html)
+[Docker-based installation](https://librelane.readthedocs.io/en/stable/installation/docker_installation/index.html)
 in the docs for more info.
 
 Do note you'll need to add `--dockerized` right after `librelane` in most CLI
@@ -110,7 +110,9 @@ python3 -m pip install --upgrade librelane
 ```
 
 Python-only installations are presently unsupported and entirely at your own
-risk.
+risk, but you may consult
+[Manual installation](https://librelane.readthedocs.io/en/stable/installation/manual_installation/index.html)
+in the docs for more info.
 
 ## Usage
 

{librelane-3.1.0.dev4 → librelane-3.1.0.dev5}/librelane/config/variable.py

@@ -245,6 +245,8 @@ class Macro:
 
         # we need to make a copy here, as we're modifying the dictionary as we iterate
         for instance_name, instance in self.instances.copy().items():
+            if not isinstance(instance, Instance):
+                instance = Instance(**instance)
             if (array := instance.array) is not None:
                 # we have a macro to expand
                 # first, check it's valid

{librelane-3.1.0.dev4 → librelane-3.1.0.dev5}/librelane/scripts/openroad/common/io.tcl

@@ -129,7 +129,7 @@ proc read_current_sdc {} {
     }
 
     puts "Reading design constraints file at '$::env(_SDC_IN)'…"
-    if {[catch {read_sdc $::env(_SDC_IN)} errmsg]} {
+    if {[catch {log_cmd read_sdc $::env(_SDC_IN)} errmsg]} {
         puts stderr $errmsg
         exit 1
     }
@@ -137,10 +137,10 @@ proc read_current_sdc {} {
     if { ![string_in_file $::env(_SDC_IN) "set_propagated_clock"] && ![string_in_file $::env(_SDC_IN) "unset_propagated_clock"] } {
         if { [info exists ::env(OPENLANE_SDC_IDEAL_CLOCKS)] && $::env(OPENLANE_SDC_IDEAL_CLOCKS) } {
             puts "\[INFO\] No information on clock propagation in input SDC file-- unpropagating all clocks."
-            unset_propagated_clock [all_clocks]
+            log_cmd unset_propagated_clock [all_clocks]
         } else {
             puts "\[INFO\] No information on clock propagation in input SDC file-- propagating all clocks."
-            set_propagated_clock [all_clocks]
+            log_cmd set_propagated_clock [all_clocks]
         }
     }
 
@@ -158,6 +158,12 @@ proc read_current_sdc {} {
         unset ::env(SYNTH_DRIVING_CELL_PIN)
         set ::env(SYNTH_DRIVING_CELL) $synth_driving_cell_bk
     }
+
+    # this maneuver is so it ends up in the report directory even if it's not
+    # the step directory
+    puts "%OL_CREATE_REPORT resolved.sdc"
+    write_sdc /dev/stdout
+    puts "%OL_END_REPORT"
 }
 
 proc read_pad_cfg {} {
@@ -210,20 +216,20 @@ proc read_current_netlist {args} {
 
     if { [info exists flags(-powered)] } {
         puts "Reading top-level powered netlist at '$::env(CURRENT_PNL)'…"
-        if {[catch {read_verilog $::env(CURRENT_PNL)} errmsg]} {
+        if {[catch {log_cmd read_verilog $::env(CURRENT_PNL)} errmsg]} {
             puts stderr $errmsg
             exit 1
         }
     } else {
         puts "Reading top-level netlist at '$::env(CURRENT_NL)'…"
-        if {[catch {read_verilog $::env(CURRENT_NL)} errmsg]} {
+        if {[catch {log_cmd read_verilog $::env(CURRENT_NL)} errmsg]} {
             puts stderr $errmsg
             exit 1
         }
     }
 
     puts "Linking design '$::env(DESIGN_NAME)' from netlist…"
-    link_design $::env(DESIGN_NAME)
+    log_cmd link_design $::env(DESIGN_NAME)
     set_global_vars
     read_current_sdc
 }
@@ -237,27 +243,27 @@ proc read_timing_info {args} {
         return
     }
     set corner_name $::env(_CURRENT_CORNER_NAME)
-    log_cm define_corners $corner_name
+    log_cmd define_corners $corner_name
 
     puts "Reading timing models for corner $corner_name…"
 
     foreach lib $::env(_CURRENT_CORNER_LIBS) {
         puts "Reading cell library for the '$corner_name' corner at '$lib'…"
-        read_liberty -corner $corner_name $lib
+        log_cmd read_liberty -corner $corner_name $lib
     }
 
     if { [info exists ::env(EXTRA_LIBS) ] } {
         puts "Reading explicitly-specified extra libs for $corner_name…"
         foreach extra_lib $::env(EXTRA_LIBS) {
             puts "Reading extra timing library for the '$corner_name' corner at '$extra_lib'…"
-            read_liberty -corner $corner_name $extra_lib
+            log_cmd read_liberty -corner $corner_name $extra_lib
         }
     }
 
     set blackbox_wildcard {/// sta-blackbox}
     foreach nl $::env(_CURRENT_CORNER_NETLISTS) {
         puts "Reading macro netlist at '$nl'…"
-        if { [catch {read_verilog $nl} err] } {
+        if { [catch {log_cmd read_verilog $nl} err] } {
             puts stderr "Error while reading macro netlist '$nl':"
             puts stderr $err
             puts stderr "Make sure that this a gate-level netlist and not an RTL file."
@@ -268,7 +274,7 @@ proc read_timing_info {args} {
         foreach verilog_file $::env(EXTRA_VERILOG_MODELS) {
             if { [string_in_file $verilog_file $blackbox_wildcard] } {
                 puts "Found '$blackbox_wildcard' in '$verilog_file', skipping…"
-            } elseif { [catch {puts "Reading Verilog model at '$verilog_file'…"; read_verilog $verilog_file} err] } {
+            } elseif { [catch {puts "Reading Verilog model at '$verilog_file'…"; log_cmd read_verilog $verilog_file} err] } {
                 puts stderr "Error while reading $verilog_file:"
                 puts stderr $err
                 puts stderr "Make sure that this a gate-level netlist and not an RTL file, otherwise, you can add the following comment '$blackbox_wildcard' in the file to skip it and blackbox the modules inside if needed."
@@ -295,7 +301,7 @@ proc read_spefs {} {
     if { [info exists ::env(_CURRENT_SPEF_BY_CORNER)] } {
         set corner_name $::env(_CURRENT_CORNER_NAME)
         puts "Reading top-level design parasitics for the '$corner_name' corner at '$::env(_CURRENT_SPEF_BY_CORNER)'…"
-        read_spef -corner $corner_name $::env(_CURRENT_SPEF_BY_CORNER)
+        log_cmd read_spef -corner $corner_name $::env(_CURRENT_SPEF_BY_CORNER)
     }
     if { [info exists ::env(_CURRENT_CORNER_SPEFS)] } {
         set corner_name $::env(_CURRENT_CORNER_NAME)
@@ -303,7 +309,7 @@ proc read_spefs {} {
             set instance_path [lshift spefs]
             foreach spef $spefs {
                 puts "Reading '$instance_path' parasitics for the '$corner_name' corner at '$spef'…"
-                read_spef -corner $corner_name -path $instance_path $spef
+                log_cmd read_spef -corner $corner_name -path $instance_path $spef
             }
         }
     }
@@ -316,7 +322,7 @@ proc read_spefs {} {
                 if { "[get_property $cell ref_name]" eq "$module_name"} {
                     set instance_path [get_property $cell full_name]
                     puts "Reading '$instance_path' parasitics for the '$corner_name' corner at '$spef'…"
-                    read_spef -corner $corner_name -path $instance_path $spef
+                    log_cmd read_spef -corner $corner_name -path $instance_path $spef
                 }
             }
         }
@@ -336,7 +342,7 @@ proc read_pnr_libs {args} {
         lappend corner_names $corner_name
     }
 
-    define_corners {*}[array name corner]
+    log_cmd define_corners {*}[array name corner]
 
     foreach corner_name [array name corner] {
         puts "Reading timing models for corner $corner_name…"
@@ -344,14 +350,14 @@ proc read_pnr_libs {args} {
         set corner_models $corner($corner_name)
         foreach model $corner_models {
             puts "Reading timing library for the '$corner_name' corner at '$model'…"
-            read_liberty -corner $corner_name $model
+            log_cmd read_liberty -corner $corner_name $model
         }
 
         if { [info exists ::env(EXTRA_LIBS) ] } {
             puts "Reading explicitly-specified extra libs for $corner_name…"
             foreach extra_lib $::env(EXTRA_LIBS) {
                 puts "Reading extra timing library for the '$corner_name' corner at '$extra_lib'…"
-                read_liberty -corner $corner_name $extra_lib
+                log_cmd read_liberty -corner $corner_name $extra_lib
             }
         }
     }
@@ -361,7 +367,7 @@ proc read_tech_lef {{tlef_key "TECH_LEF"}} {
     set tlef $::env($tlef_key)
 
     puts "Reading technology LEF file at '$tlef'…"
-    read_lef $tlef
+    log_cmd read_lef $tlef
 
     # Make fake I/O sites
     if { [info exists ::env(PAD_FAKE_SITES)] } {
@@ -370,7 +376,7 @@ proc read_tech_lef {{tlef_key "TECH_LEF"}} {
             set height [lindex $size 1]
 
             puts "Making fake IO site $site_name…"
-            make_fake_io_site -name $site_name -width $width -height $height
+            log_cmd make_fake_io_site -name $site_name -width $width -height $height
         }
     }
 }
@@ -378,24 +384,24 @@ proc read_tech_lef {{tlef_key "TECH_LEF"}} {
 proc read_other_lefs {} {
     foreach lef $::env(CELL_LEFS) {
         puts "Reading cell LEF file at '$lef'…"
-        read_lef $lef
+        log_cmd read_lef $lef
     }
     if { [info exist ::env(MACRO_LEFS)] } {
         foreach lef $::env(MACRO_LEFS) {
             puts "Reading macro LEF file at '$lef'…"
-            read_lef $lef
+            log_cmd read_lef $lef
         }
     }
     if { [info exist ::env(PAD_LEFS)] } {
         foreach lef $::env(PAD_LEFS) {
             puts "Reading gpio pad LEF file at '$lef'…"
-            read_lef $lef
+            log_cmd read_lef $lef
         }
     }
     if { [info exist ::env(EXTRA_LEFS)] } {
         foreach lef $::env(EXTRA_LEFS) {
             puts "Reading extra LEF file at '$lef'…"
-            read_lef $lef
+            log_cmd read_lef $lef
         }
     }
 }
@@ -416,7 +422,7 @@ proc read_current_odb {args} {
 
     read_pnr_libs
     puts "Reading OpenROAD database at '$::env(CURRENT_ODB)'…"
-    if { [ catch {read_db $::env(CURRENT_ODB)} errmsg ]} {
+    if { [ catch {log_cmd read_db $::env(CURRENT_ODB)} errmsg ]} {
         puts stderr $errmsg
         exit 1
     }

{librelane-3.1.0.dev4 → librelane-3.1.0.dev5}/librelane/scripts/openroad/gui.tcl

@@ -14,18 +14,18 @@
 source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
 
 puts "Reading OpenROAD database at '$::env(CURRENT_ODB)'…"
-if { [ catch {read_db $::env(CURRENT_ODB)} errmsg ]} {
+if { [ catch {log_cmd read_db $::env(CURRENT_ODB)} errmsg ]} {
     puts stderr $errmsg
     exit 1
 }
 
 set_global_vars
 
-define_corners $::env(DEFAULT_CORNER)
+log_cmd define_corners $::env(DEFAULT_CORNER)
 
 foreach lib $::env(_PNR_LIBS) {
     puts "Reading library file at '$lib'…"
-    read_liberty $lib
+    log_cmd read_liberty $lib
 }
 
 read_current_sdc
@@ -33,5 +33,5 @@ read_current_sdc
 if { [info exists ::env(_CURRENT_SPEF_BY_CORNER)] } {
     set corner_name $::env(_CURRENT_CORNER_NAME)
     puts "Reading top-level design parasitics for the '$corner_name' corner at '$::env(_CURRENT_SPEF_BY_CORNER)'…"
-    read_spef -corner $corner_name $::env(_CURRENT_SPEF_BY_CORNER)
+    log_cmd read_spef -corner $corner_name $::env(_CURRENT_SPEF_BY_CORNER)
 }

{librelane-3.1.0.dev4 → librelane-3.1.0.dev5}/librelane/scripts/openroad/sta/corner.tcl

@@ -23,7 +23,7 @@
 
 source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
 
-set_cmd_units\
+log_cmd set_cmd_units\
     -time ns\
     -capacitance pF\
     -current mA\
@@ -39,9 +39,9 @@ if { [namespace exists ::ord] } {
 
     # Internal API- brittle
     if { [grt::have_routes] } {
-        estimate_parasitics -global_routing
+        log_cmd estimate_parasitics -global_routing
     } elseif { [est::check_corner_wire_cap] } {
-        estimate_parasitics -placement
+        log_cmd estimate_parasitics -placement
     }
 } else {
     read_timing_info

{librelane-3.1.0.dev4 → librelane-3.1.0.dev5}/librelane/scripts/pyosys/synthesize.py

@@ -34,7 +34,7 @@
 import os
 import json
 import shutil
-from typing import List, Optional
+from typing import List, Optional, Tuple
 
 import click
 
@@ -42,6 +42,27 @@ from ys_common import ys, yosys_version_at_least
 from construct_abc_script import ABCScriptCreator
 
 
+def stat_json(d: ys.Design, lib_arguments: Tuple[str, ...], report_dir: str):
+    """
+    hack: work around https://github.com/YosysHQ/yosys/issues/6442
+    """
+    raw = os.path.join(report_dir, "stat.json.raw")
+    parseable = os.path.join(report_dir, "stat.json")
+    d.tee("stat", "-json", *lib_arguments, o=raw)
+    with (
+        open(raw, encoding="utf8") as f_in,
+        open(parseable, "w", encoding="utf8") as f_out,
+    ):
+        char = " "
+        # skip until first { or EOF
+        while char != "{" and char != "":
+            char = f_in.read(1)
+        # if EOF reached, print nothing, just close
+        if char != "":
+            f_out.write("{")  # { already consumed, replace it before writing the rest
+            f_out.write(f_in.read())
+
+
 def librelane_proc(d: ys.Design, report_dir: str):
     d.run_pass("proc_clean")  # Clean up unused procedures
     d.run_pass("proc_rmdead")  # Remove dead procedures
@@ -357,7 +378,7 @@ def synthesize(
         d.run_pass("splitnets")
         d.run_pass("opt_clean", "-purge")
         d.tee("check", o=os.path.join(report_dir, "chk.rpt"))
-        d.tee("stat", "-json", *lib_arguments, o=os.path.join(report_dir, "stat.json"))
+        stat_json(d, lib_arguments, report_dir)
         d.tee("stat", *lib_arguments, o=os.path.join(report_dir, "stat.rpt"))
 
         noattr_flag = []
@@ -523,7 +544,7 @@ def synthesize(
             d.run_pass("insbuf", "-buf", *config["SYNTH_BUFFER_CELL"].split("/"))
 
         d.tee("check", o=os.path.join(report_dir, "chk.rpt"))
-        d.tee("stat", "-json", *lib_arguments, o=os.path.join(report_dir, "stat.json"))
+        stat_json(d, lib_arguments, report_dir)
         d.tee("stat", *lib_arguments, o=os.path.join(report_dir, "stat.rpt"))
 
         if config["SYNTH_AUTONAME"]:

{librelane-3.1.0.dev4 → librelane-3.1.0.dev5}/librelane/steps/pyosys.py

@@ -622,8 +622,8 @@ class SynthesisCommon(VerilogStep):
         view_updates, metric_updates = super().run(state_in, **kwargs)
 
         stats_file = os.path.join(self.step_dir, "reports", "stat.json")
-        stats_str = open(stats_file).read()
-        stats = json.loads(stats_str, parse_float=Decimal)
+        with open(stats_file, encoding="utf8") as f:
+            stats = json.load(f, parse_float=Decimal)
 
         metric_updates["design__instance__count"] = stats["design"]["num_cells"]
         if chip_area := stats["design"].get("area"):  # needs nonzero area

{librelane-3.1.0.dev4 → librelane-3.1.0.dev5}/librelane/steps/step.py

@@ -135,10 +135,13 @@ class DefaultOutputProcessor(OutputProcessor[Dict[str, Any]]):
 
     * ``%OL_CREATE_REPORT <file>``\\: Starts redirecting all output from
       standard output to a report file inside the step directory, with the
-      name <file>.
-    * ``%OL_END_REPORT``: Stops redirection behavior.
+      name <file>. Note that %OL_ commands take priority: a repeated call of
+      %OL_CREATE_REPORT will open a new report, closing the previous one, and
+      all metric calls will not be forwarded to the report.
+    * ``%OL_END_REPORT``: Stops redirection behavior, closing the report.
     * ``%OL_METRIC <name> <value>``\\: Adds a string metric with the name <name>
-      and the value <value> to this function's returned object.
+      and the value <value> to this function's returned object, with leading
+      and trailing whitespace stripped.
     * ``%OL_METRIC_F <name> <value>``\\: Adds a floating-point metric with the
       name <name> and the value <value> to this function's returned object.
     * ``%OL_METRIC_I <name> <value>``\\: Adds an integer metric with the name
@@ -170,13 +173,13 @@ class DefaultOutputProcessor(OutputProcessor[Dict[str, Any]]):
                 self.current_rpt.close()
             self.current_rpt = None
         elif line.startswith(METRIC_LOCUS):
-            command, name, value = line.split(" ", maxsplit=3)
+            command, name, value = line.split(" ", maxsplit=2)
             metric_type: Union[Type[str], Type[int], Type[Decimal]] = str
             if command.endswith("_I"):
                 metric_type = int
             elif command.endswith("_F"):
                 metric_type = Decimal
-            self.generated_metrics[name] = metric_type(value)
+            self.generated_metrics[name] = metric_type(value.strip())
         elif self.current_rpt is not None:
             # No echo- the timing reports especially can be very large
             # and terminal emulators will slow the flow down.

{librelane-3.1.0.dev4 → librelane-3.1.0.dev5}/pyproject.toml

@@ -1,6 +1,6 @@
 [project]
 name = "librelane"
-version = "3.1.0.dev4"
+version = "3.1.0.dev5"
 description = "An infrastructure for implementing chip design flows"
 maintainers = [
     {name = "Mohamed Gaber", email = "donn@fossi-foundation.org"},