librelane 3.1.0.dev1__tar.gz → 3.1.0.dev2__tar.gz

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: librelane
-Version: 3.1.0.dev1
+Version: 3.1.0.dev2
 Summary: An infrastructure for implementing chip design flows
 License-Expression: Apache-2.0
 Maintainer: Mohamed Gaber

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/config/config.py

@@ -495,10 +495,10 @@ class Config(GenericImmutableDict[str, Any]):
         :param pdk: A process design kit to use. Required unless specified via the
             "PDK" key in a configuration object.
 
-        :param pdk_root: Required if Volare is not installed.
+        :param pdk_root: Required if Ciel is not installed.
 
-            If Volare is installed, this value can be used to optionally override
-            Volare's default.
+            If Ciel is installed, this value can be used to optionally override
+            Ciel's default.
 
         :param scl: A standard cell library to use. If not specified, the PDK's
             default standard cell library will be used instead.
@@ -713,7 +713,7 @@ class Config(GenericImmutableDict[str, Any]):
                 pdk=pdk,
                 pdkpath=pdkpath,
                 scl=mutable[SpecialKeys.scl],
-                pad=mutable.get(SpecialKeys.pad, None),
+                pad=mutable.get(SpecialKeys.pad, pad),
                 design_dir=design_dir,
             )
         )
@@ -833,6 +833,11 @@ class Config(GenericImmutableDict[str, Any]):
         if scl is not None:
             pdk_config[SpecialKeys.scl] = scl
 
+            # HACK: Prevent loading default SCL cfg vars for old openlane PDK
+            # configs
+            # For more info: https://github.com/librelane/librelane/issues/932
+            pdk_config["STD_CELL_LIBRARY_OPT"] = scl
+
         if pad is not None:
             pdk_config[SpecialKeys.pad] = pad
 

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/config/flow.py

@@ -39,6 +39,12 @@ pdk_variables = [
         "Specifies the default standard cell library to be used under the specified PDK. Must be a valid C identifier, i.e., matches the regular expression `[_a-zA-Z][_a-zA-Z0-9]+`.",
         pdk=True,
     ),
+    Variable(
+        "PAD_CELL_LIBRARY",
+        Optional[str],
+        "Specifies the default pad cell library to be used under the specified PDK. Must be a valid C identifier, i.e., matches the regular expression `[_a-zA-Z][_a-zA-Z0-9]+`.",
+        pdk=True,
+    ),
     Variable(
         "VDD_PIN",
         str,

librelane-3.1.0.dev2/librelane/pdk_hashes.yaml

@@ -0,0 +1,3 @@
+sky130: 74c0e6b118a67d94c24172143d3bd597473fa63d
+gf180mcu: b344c97eacc2aaf8e14ae7e43e2e9dc0871de2c0
+ihp-sg13g2: c4b8b4e5e7a05f375cca3815d51b3a37721fbf5c

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/magic/def/antenna_check.tcl

@@ -12,6 +12,9 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 source $::env(SCRIPTS_DIR)/magic/def/read.tcl
+drc off
+crashbackups disable
+locking disable
 
 load $::env(DESIGN_NAME) -dereference
 

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/magic/def/mag.tcl

@@ -13,7 +13,10 @@
 # limitations under the License.
 
 source $::env(SCRIPTS_DIR)/magic/def/read.tcl
+drc off
+crashbackups disable
+locking disable
 
 save $::env(SAVE_MAG)
 
-puts "[INFO] Done exporting $::env(SAVE_MAG)."
+puts "[INFO] Done exporting $::env(SAVE_MAG)."

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/magic/def/mag_gds.tcl

@@ -18,6 +18,7 @@
 source $::env(SCRIPTS_DIR)/magic/common/read.tcl
 drc off
 crashbackups disable
+locking disable
 
 gds noduplicates true
 gds readonly true

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/magic/drc.tcl

@@ -17,6 +17,7 @@
 # limitations under the License.
 
 crashbackups disable
+locking disable
 units internal
 
 # Read in maglef views in order to blackbox cells

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/magic/extract_spice.tcl

@@ -20,6 +20,9 @@ puts $f [expr {((round([magic::cif scale output] * 10000)) / 10000.0) * 1}]
 close $f
 
 source $::env(SCRIPTS_DIR)/magic/common/read.tcl
+drc off
+crashbackups disable
+locking disable
 
 if { $::env(MAGIC_EXT_USE_GDS) } {
     gds read $::env(CURRENT_GDS)

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/magic/gds/drc_batch.tcl

@@ -12,6 +12,9 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
+crashbackups disable
+locking disable
+
 if { [info exists ::env(TECH)] } {
     tech load $::env(TECH)
 }

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/magic/gds/erase_box.tcl

@@ -12,6 +12,10 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
+drc off
+crashbackups disable
+locking disable
+
 tech unlock *
 
 gds read $::env(CURRENT_GDS)

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/magic/gds/extras_mag.tcl

@@ -17,6 +17,8 @@
 # corresponding maglefs
 
 drc off
+crashbackups disable
+locking disable
 
 gds readonly true
 gds rescale false

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/magic/gds/mag_with_pointers.tcl

@@ -13,6 +13,8 @@
 # limitations under the License.
 
 drc off
+crashbackups disable
+locking disable
 
 gds readonly true
 gds rescale false

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/magic/get_bbox.tcl

@@ -1,3 +1,7 @@
+drc off
+crashbackups disable
+locking disable
+
 gds read $::env(_GDS_IN)
 load $::env(_MACRO_NAME_IN)
 set curunits [units]

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/magic/lef/extras_maglef.tcl

@@ -15,6 +15,8 @@
 # convert all external macros to maglef views with GDS_* pointers
 
 drc off
+crashbackups disable
+locking disable
 
 if {  [info exist ::env(EXTRA_LEFS)] } {
 	foreach lef_file $::env(EXTRA_LEFS) {

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/magic/lef/maglef.tcl

@@ -13,6 +13,8 @@
 # limitations under the License.
 
 drc off
+crashbackups disable
+locking disable
 
 lef read $::env(signoff_results)/$::env(DESIGN_NAME).lef
 

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/magic/lef.tcl

@@ -16,6 +16,9 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 drc off
+crashbackups disable
+locking disable
+
 if { $::env(MAGIC_LEF_WRITE_USE_GDS) } {
     gds read $::env(CURRENT_GDS)
 } else {

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/magic/spice_rcx.tcl

@@ -16,6 +16,10 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
+drc off
+crashbackups disable
+locking disable
+
 # we do always want to read the GDS for this
 gds read $::env(CURRENT_GDS)
 

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/odbpy/power_utils.py

@@ -52,8 +52,15 @@ class Design(object):
             netname_by_bit = {}
 
             for netname, info in yosys_design_object["netnames"].items():
-                for bit in info["bits"]:
-                    netname_by_bit[bit] = netname
+                assert len(info["bits"]) > 0
+                # Single bit net, return name directly
+                if len(info["bits"]) == 1:
+                    netname_by_bit[info["bits"][0]] = netname
+                # Append bit index to signal name
+                else:
+                    offset = info.get("offset", 0)
+                    for index, bit in enumerate(info["bits"]):
+                        netname_by_bit[bit] = f"{netname}[{offset + index}]"
 
             self.verilog_net_names_by_bit_by_module[top_module] = netname_by_bit
         return self.verilog_net_names_by_bit_by_module[top_module][target_bit]

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/openroad/common/io.tcl

@@ -588,7 +588,11 @@ proc write_libs {} {
         foreach corner_name [lln::get_corner_names] {
             set target $::env(_LIB_SAVE_DIR)/$::env(DESIGN_NAME)__$corner_name.lib
             puts "Writing timing models for the $corner_name corner to $target…"
-            write_timing_model -corner $corner_name $target
+            if {[string length [namespace which sta::scenes]] != 0} {
+                write_timing_model -scene $corner_name $target
+            } else {
+                write_timing_model -corner $corner_name $target
+            }
         }
     }
 }

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/openroad/common/pad_cfg.tcl

@@ -20,6 +20,11 @@ puts "\[INFO\] Generating padring…"
 set block [ord::get_db_block]
 set units [$block getDefUnits]
 
+# Round a micrometer value to nanometer
+proc round_um_nm {value} {
+    return [expr double(round($value * 1000)) / 1000]
+}
+
 # Pad Placement Algorithm
 #
 # For all sides:
@@ -128,15 +133,15 @@ foreach side $sides {
 
     set space_between_pads [expr $space_for_fill / ([llength $::env($side)] + 1)]
     puts "space_between_pads: $space_between_pads"
-    
-    # Round to minimum site width (min. filler)
-    set space_between_pads_min_filler [expr round(floor($space_between_pads / $pad_site_width) * $pad_site_width * 1000) / 1000]
-    puts "space_between_pads_min_filler: $space_between_pads_min_filler"
+
+    # Round to PAD_SPACING_MULTIPLE
+    set space_between_pads_multiple [round_um_nm [expr floor($space_between_pads / $::env(PAD_SPACING_MULTIPLE)) * $::env(PAD_SPACING_MULTIPLE)]]
+    puts "space_between_pads_multiple: $space_between_pads_multiple"
 
     # The spacing for the pads on the side (the remaining space)
-    set space_side [expr round(($space_for_fill - $space_between_pads_min_filler * ([llength $::env($side)] - 1)) / 2 * 1000) / 1000]
+    set space_side [round_um_nm [expr ($space_for_fill - $space_between_pads_multiple * ([llength $::env($side)] - 1)) / 2]]
     
-    if { $space_side != round(floor($space_side / $pad_site_width) * $pad_site_width * 1000) / 1000 } {
+    if { $space_side != [round_um_nm [expr floor($space_side / $pad_site_width) * $pad_site_width]] } {
         puts "\[Error\] The remaining area for the pads on the side ($space_side) is not divisible by the minimum site width (minimum filler: $pad_site_width)."
         exit 1
     }
@@ -166,7 +171,7 @@ foreach side $sides {
         place_pad -row [dict get $row_names $side] -location $cur_pos $inst_name -master $master_name
         
         # Increment current position
-        set cur_pos [expr $cur_pos + $space_between_pads_min_filler + $width]
+        set cur_pos [expr $cur_pos + $space_between_pads_multiple + $width]
     }
 }
 
@@ -178,10 +183,18 @@ place_corners $::env(PAD_CORNER)
 puts "\[INFO\] Placing filler cells…"
 
 # Place filler cells
-place_io_fill -row IO_NORTH {*}$::env(PAD_FILLERS)
-place_io_fill -row IO_SOUTH {*}$::env(PAD_FILLERS)
-place_io_fill -row IO_WEST {*}$::env(PAD_FILLERS)
-place_io_fill -row IO_EAST {*}$::env(PAD_FILLERS)
+if {!$::env(PAD_TRIM_ROWS) || ($::env(PAD_NORTH) ne "")} { place_io_fill -row IO_NORTH {*}$::env(PAD_FILLERS) }
+if {!$::env(PAD_TRIM_ROWS) || ($::env(PAD_SOUTH) ne "")} { place_io_fill -row IO_SOUTH {*}$::env(PAD_FILLERS) }
+if {!$::env(PAD_TRIM_ROWS) || ($::env(PAD_WEST) ne "")} { place_io_fill -row IO_WEST {*}$::env(PAD_FILLERS) }
+if {!$::env(PAD_TRIM_ROWS) || ($::env(PAD_EAST) ne "")} { place_io_fill -row IO_EAST {*}$::env(PAD_FILLERS) }
+
+puts "\[INFO\] Deleting corner cells (if required)…"
+
+# Delete corner cells if required
+if {$::env(PAD_TRIM_ROWS) && ($::env(PAD_NORTH) eq "") && ($::env(PAD_WEST) eq "")} { odb::dbInst_destroy [$block findInst IO_CORNER_NORTH_WEST_INST] }
+if {$::env(PAD_TRIM_ROWS) && ($::env(PAD_NORTH) eq "") && ($::env(PAD_EAST) eq "")} { odb::dbInst_destroy [$block findInst IO_CORNER_NORTH_EAST_INST] }
+if {$::env(PAD_TRIM_ROWS) && ($::env(PAD_SOUTH) eq "") && ($::env(PAD_WEST) eq "")} { odb::dbInst_destroy [$block findInst IO_CORNER_SOUTH_WEST_INST] }
+if {$::env(PAD_TRIM_ROWS) && ($::env(PAD_SOUTH) eq "") && ($::env(PAD_EAST) eq "")} { odb::dbInst_destroy [$block findInst IO_CORNER_SOUTH_EAST_INST] }
 
 puts "\[INFO\] Connecting ring signals…"
 
@@ -246,3 +259,4 @@ if { [info exists ::env(PAD_PLACE_IO_TERMINALS)] } {
 # Remove io rows to avoid causing confusion with the other tools
 puts "\[INFO\] Removing I/O rows…"
 remove_io_rows
+

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/openroad/repair_design.tcl

@@ -33,12 +33,15 @@ if { $::env(DESIGN_REPAIR_REMOVE_BUFFERS) } {
     remove_buffers
 }
 
+# Use SYNTH_BUFFER_CELL as buffer, since OpenROAD may select a hold/delay buffer
+# See: https://github.com/librelane/librelane/pull/961
+
 if { $::env(DESIGN_REPAIR_BUFFER_INPUT_PORTS) } {
-    buffer_ports -inputs
+    buffer_ports -inputs -buffer_cell [lindex [split $::env(SYNTH_BUFFER_CELL) "/"] 0]
 }
 
 if { $::env(DESIGN_REPAIR_BUFFER_OUTPUT_PORTS) } {
-    buffer_ports -outputs
+    buffer_ports -outputs -buffer_cell [lindex [split $::env(SYNTH_BUFFER_CELL) "/"] 0]
 }
 
 set arg_list [list]

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/pyosys/json_header.py

@@ -43,6 +43,11 @@ def json_header(
             "__librelane__",
             "__pnr__",
         ]
+        + (
+            [f"PAD_{config['PAD_CELL_LIBRARY']}"]
+            if "PAD_CELL_LIBRARY" in config
+            else []
+        )
         + (
             []
             if config.get("VERILOG_POWER_DEFINE") is None

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/scripts/pyosys/synthesize.py

@@ -157,6 +157,7 @@ def librelane_synth(
 ):
 
     d.run_pass("hierarchy", "-check", "-top", top, "-nokeep_prints", "-nokeep_asserts")
+    d.run_pass("chformal", "-remove")
     librelane_proc(d, report_dir)
 
     if keep_hierarchy_min_cost:
@@ -251,12 +252,20 @@ def synthesize(
     extra = json.load(open(extra_in))
 
     includes = config.get("VERILOG_INCLUDE_DIRS") or []
-    defines = (config.get("VERILOG_DEFINES") or []) + [
-        f"PDK_{config['PDK'].replace('-','_')}",
-        f"SCL_{config['STD_CELL_LIBRARY']}",
-        "__librelane__",
-        "__pnr__",
-    ]
+    defines = (
+        (config.get("VERILOG_DEFINES") or [])
+        + [
+            f"PDK_{config['PDK'].replace('-','_')}",
+            f"SCL_{config['STD_CELL_LIBRARY']}",
+            "__librelane__",
+            "__pnr__",
+        ]
+        + (
+            [f"PAD_{config['PAD_CELL_LIBRARY']}"]
+            if "PAD_CELL_LIBRARY" in config
+            else []
+        )
+    )
 
     blackbox_models = extra["blackbox_models"]
     libs = extra["libs_synth"]

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/steps/common_variables.py

@@ -286,7 +286,7 @@ pdn_variables = [
     Variable(
         "PDN_RAIL_WIDTH",
         Decimal,
-        "Defines the width of PDN rails on the `FP_PDN_RAILS_LAYER` layer.",
+        "Defines the width of PDN rails on the `PDN_RAIL_LAYER` layer.",
         units="µm",
         pdk=True,
         deprecated_names=["FP_PDN_RAIL_WIDTH"],

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/steps/klayout.py

@@ -171,7 +171,7 @@ class Render(KLayoutStep):
     id = "KLayout.Render"
     name = "Render Image (w/ KLayout)"
 
-    inputs = [DesignFormat.DEF]
+    inputs = []
     outputs = []
 
     config_vars = KLayoutStep.config_vars + [
@@ -216,10 +216,14 @@ class Render(KLayoutStep):
     def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
         views_updates: ViewsUpdate = {}
 
-        input_view = state_in[DesignFormat.DEF]
+        input_view = state_in.get(DesignFormat.DEF)
+
         if gds := state_in.get(DesignFormat.GDS):
             input_view = gds
 
+        if input_view is None:
+            raise StepError(f"{id} requires at least one of LEF or GDS as input.")
+
         assert isinstance(input_view, Path)
 
         klayout_render = os.path.join(
@@ -434,7 +438,7 @@ class DRC(KLayoutStep):
     Unlike most steps, the KLayout scripts vary quite wildly by PDK. If a PDK
     is not supported by this step, it will simply be skipped.
 
-    Currently, only sky130A and sky130B are supported.
+    Currently, sky130, gf180mcu and ihp-sg13 are supported.
     """
 
     id = "KLayout.DRC"
@@ -455,7 +459,7 @@ class DRC(KLayoutStep):
         ),
         Variable(
             "KLAYOUT_DRC_OPTIONS",
-            Optional[Dict[str, Union[bool, int, str]]],
+            Optional[Dict[str, Union[int, bool, str]]],
             "Options passed directly to the KLayout DRC runset. They vary from one PDK to another.",
             pdk=True,
         ),
@@ -513,9 +517,6 @@ class DRC(KLayoutStep):
         if threads != "1":
             opts.extend(
                 [
-                    "-rd",
-                    f"thr={threads}",
-                    # Use "threads" if possible
                     "-rd",
                     f"threads={threads}",
                 ]
@@ -602,6 +603,8 @@ class DRC(KLayoutStep):
                 "-rd",
                 f"seal={seal}",
                 "-rd",
+                f"thr={threads}",
+                "-rd",
                 f"threads={threads}",
             ],
             env=env,
@@ -658,7 +661,7 @@ class DRC(KLayoutStep):
             opts.extend(
                 [
                     "-rd",
-                    f"thr={threads}",
+                    f"threads={threads}",
                 ]
             )
 
@@ -727,7 +730,7 @@ class DRC(KLayoutStep):
             opts.extend(
                 [
                     "-rd",
-                    f"thr={threads}",
+                    f"threads={threads}",
                 ]
             )
 

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/steps/openroad.py

@@ -1267,6 +1267,19 @@ class PadRing(OpenROADStep):
             Optional[List[str]],
             "The pad instance names for the west pad row.",
         ),
+        Variable(
+            "PAD_SPACING_MULTIPLE",
+            Decimal,
+            "The spacing between the pad cells will be a multiple of this value. Please ensure that the remaining space on the sides is divisible by the minimum site width.",
+            default=1,
+            units="µm",
+        ),
+        Variable(
+            "PAD_TRIM_ROWS",
+            bool,
+            "If any of `PAD_[SOUTH|EAST|NORTH|WEST]` is empty, skip io fill for those rows and delete the corners with two neighbouring empty rows.",
+            default=False,
+        ),
     ]
 
     def get_script_path(self):

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/librelane/steps/verilator.py

@@ -77,6 +77,12 @@ class Lint(Step):
             "When a latch is inferred by an `always` block that is not explicitly marked as `always_latch`, report this as a linter error.",
             default=True,
         ),
+        Variable(
+            "LINTER_ERROR_ON_MULTIDRIVEN",
+            bool,
+            "When a net has multiple drivers, report this as a linter error.",
+            default=True,
+        ),
         Variable(
             "VERILOG_DEFINES",
             Optional[List[str]],
@@ -162,7 +168,11 @@ class Lint(Step):
             f"SCL_{self.config['STD_CELL_LIBRARY']}",
             "__librelane__",
             "__pnr__",
-        ]
+        ] + (
+            [f"PAD_{self.config['PAD_CELL_LIBRARY']}"]
+            if "PAD_CELL_LIBRARY" in self.config
+            else []
+        )
         if verilog_power_define := self.config.get("VERILOG_POWER_DEFINE"):
             defines += [verilog_power_define]
 
@@ -197,6 +207,10 @@ class Lint(Step):
         if self.config["LINTER_ERROR_ON_LATCH"]:
             extra_args.append("--Werror-LATCH")
 
+        # It's more user-friendly to catch multiple-driver conflicts here in Verilator (if possible) than later in Yosys.
+        if self.config["LINTER_ERROR_ON_MULTIDRIVEN"]:
+            extra_args.append("--Werror-MULTIDRIVEN")
+
         if include_dirs := self.config["VERILOG_INCLUDE_DIRS"]:
             extra_args.extend([f"-I{dir}" for dir in include_dirs])
 

{librelane-3.1.0.dev1 → librelane-3.1.0.dev2}/pyproject.toml

@@ -1,6 +1,6 @@
 [project]
 name = "librelane"
-version = "3.1.0.dev1"
+version = "3.1.0.dev2"
 description = "An infrastructure for implementing chip design flows"
 maintainers = [
     {name = "Mohamed Gaber", email = "donn@fossi-foundation.org"},

librelane-3.1.0.dev1/librelane/pdk_hashes.yaml

@@ -1,3 +0,0 @@
-sky130: d815bb30c9afdf9e264c276a8a2b533108dea3d0
-gf180mcu: d815bb30c9afdf9e264c276a8a2b533108dea3d0
-ihp-sg13g2: c4b8b4e5e7a05f375cca3815d51b3a37721fbf5c