librelane 3.0.4__tar.gz → 3.1.0.dev2__tar.gz

{librelane-3.0.4 → librelane-3.1.0.dev2}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: librelane
-Version: 3.0.4
+Version: 3.1.0.dev2
 Summary: An infrastructure for implementing chip design flows
 License-Expression: Apache-2.0
 Maintainer: Mohamed Gaber

{librelane-3.0.4 → librelane-3.1.0.dev2}/librelane/common/toolbox.py

@@ -232,10 +232,16 @@ class Toolbox(object):
 
         timing_corner = timing_corner or config["DEFAULT_CORNER"]
 
-        all_libs: List[Path] = self.filter_views(config, config["LIB"], timing_corner)
+        # Filter the cell libs
+        all_libs: List[Path] = self.filter_views(
+            config, config["CELL_LIBS"], timing_corner
+        )
         if len(all_libs) == 0:
             warn(f"No SCL lib files found for {timing_corner}.")
 
+        # Add optional I/O pad libs
+        all_libs += self.filter_views(config, config["PAD_LIBS"], timing_corner)
+
         all_netlists: List[Path] = []
         all_spefs: List[Tuple[str, Path]] = []
 

{librelane-3.0.4 → librelane-3.1.0.dev2}/librelane/config/config.py

@@ -495,10 +495,10 @@ class Config(GenericImmutableDict[str, Any]):
         :param pdk: A process design kit to use. Required unless specified via the
             "PDK" key in a configuration object.
 
-        :param pdk_root: Required if Volare is not installed.
+        :param pdk_root: Required if Ciel is not installed.
 
-            If Volare is installed, this value can be used to optionally override
-            Volare's default.
+            If Ciel is installed, this value can be used to optionally override
+            Ciel's default.
 
         :param scl: A standard cell library to use. If not specified, the PDK's
             default standard cell library will be used instead.
@@ -713,7 +713,7 @@ class Config(GenericImmutableDict[str, Any]):
                 pdk=pdk,
                 pdkpath=pdkpath,
                 scl=mutable[SpecialKeys.scl],
-                pad=mutable.get(SpecialKeys.pad, None),
+                pad=mutable.get(SpecialKeys.pad, pad),
                 design_dir=design_dir,
             )
         )

{librelane-3.0.4 → librelane-3.1.0.dev2}/librelane/config/flow.py

@@ -18,7 +18,7 @@
 import os
 
 from decimal import Decimal
-from typing import List, Optional, Dict, Sequence, Union, Tuple
+from typing import List, Optional, Dict, Sequence, Union, Tuple, Literal
 
 from .variable import Variable, Macro
 from ..common import Path, get_script_dir
@@ -39,6 +39,12 @@ pdk_variables = [
         "Specifies the default standard cell library to be used under the specified PDK. Must be a valid C identifier, i.e., matches the regular expression `[_a-zA-Z][_a-zA-Z0-9]+`.",
         pdk=True,
     ),
+    Variable(
+        "PAD_CELL_LIBRARY",
+        Optional[str],
+        "Specifies the default pad cell library to be used under the specified PDK. Must be a valid C identifier, i.e., matches the regular expression `[_a-zA-Z][_a-zA-Z0-9]+`.",
+        pdk=True,
+    ),
     Variable(
         "VDD_PIN",
         str,
@@ -127,9 +133,10 @@ scl_variables = [
         deprecated_names=["DECAP_CELL"],
     ),
     Variable(
-        "LIB",
+        "CELL_LIBS",
         Dict[str, List[Path]],
         "A map from corner patterns to a list of associated liberty files. Exactly one entry must match the `DEFAULT_CORNER`.",
+        deprecated_names=["LIB"],
         pdk=True,
     ),
     Variable(
@@ -427,9 +434,10 @@ option_variables = [
 
 pad_variables = [
     Variable(
-        "PAD_GDS",
-        Optional[List[Path]],
-        "Path(s) to IO pad GDS file(s).",
+        "PAD_LIBS",
+        Optional[Dict[str, List[Path]]],
+        "A map from corner patterns to a list of associated liberty files. Exactly one entry must match the `DEFAULT_CORNER`.",
+        default={},
         pdk=True,
     ),
     Variable(
@@ -438,6 +446,12 @@ pad_variables = [
         "Path(s) to IO pad LEF file(s).",
         pdk=True,
     ),
+    Variable(
+        "PAD_GDS",
+        Optional[List[Path]],
+        "Path(s) to IO pad GDS file(s).",
+        pdk=True,
+    ),
     Variable(
         "PAD_VERILOG_MODELS",
         Optional[List[Path]],
@@ -456,12 +470,6 @@ pad_variables = [
         description="A circuit-design language view of the io pad library.",
         pdk=True,
     ),
-    Variable(
-        "PAD_LIBS",
-        Optional[Dict[str, List[Path]]],
-        "A map from corner patterns to a list of associated liberty files. Exactly one entry must match the `DEFAULT_CORNER`.",
-        pdk=True,
-    ),
     Variable(
         "PAD_CORNER",
         Optional[List[str]],
@@ -535,6 +543,27 @@ pad_variables = [
         units="µm",
         pdk=True,
     ),
+    Variable(
+        "PAD_ROTATION_HORIZONTAL",
+        Optional[Literal["R0", "MY", "R90", "MXR90", "R180", "MX", "R270", "MYR90"]],
+        "Rotation to apply to the horizontal sites to ensure pads are placed correctly.",
+        default="R0",
+        pdk=True,
+    ),
+    Variable(
+        "PAD_ROTATION_VERTICAL",
+        Optional[Literal["R0", "MY", "R90", "MXR90", "R180", "MX", "R270", "MYR90"]],
+        "Rotation to apply to the vertical sites to ensure pads are placed correctly.",
+        default="R0",
+        pdk=True,
+    ),
+    Variable(
+        "PAD_ROTATION_CORNER",
+        Optional[Literal["R0", "MY", "R90", "MXR90", "R180", "MX", "R270", "MYR90"]],
+        "Rotation to apply to the corner sites to ensure pads are placed correctly.",
+        default="R0",
+        pdk=True,
+    ),
 ]
 
 flow_common_variables = pdk_variables + scl_variables + option_variables + pad_variables

{librelane-3.0.4 → librelane-3.1.0.dev2}/librelane/config/pdk_compat.py

@@ -203,9 +203,9 @@ def migrate_old_config(config: Mapping[str, Any]) -> Dict[str, Any]:
         corner = f"*_{pvt}"
         lib_sta[corner] = lib_list
 
-    if (
-        new["PDK"].startswith("sky130") or new["PDK"].startswith("gf180mcu")
-    ) and "LIB" not in config:
+    if (new["PDK"].startswith("sky130") or new["PDK"].startswith("gf180mcu")) and (
+        "LIB" not in config and "CELL_LIBS" not in config
+    ):
         process_sta("LIB_SYNTH")
         process_sta("LIB_SLOWEST")
         process_sta("LIB_FASTEST")

librelane-3.1.0.dev2/librelane/pdk_hashes.yaml

@@ -0,0 +1,3 @@
+sky130: 74c0e6b118a67d94c24172143d3bd597473fa63d
+gf180mcu: b344c97eacc2aaf8e14ae7e43e2e9dc0871de2c0
+ihp-sg13g2: c4b8b4e5e7a05f375cca3815d51b3a37721fbf5c

{librelane-3.0.4 → librelane-3.1.0.dev2}/librelane/scripts/magic/common/read.tcl

@@ -56,34 +56,37 @@ proc read_pad_lef {} {
     }
 }
 
-proc read_pdk_gds {} {
-    set old_rescale [gds rescale]
-    set old_readonly [gds readonly]
+proc _read_gds {env_name} {
+    # Pre-check
+    if { ![info exist ::env($env_name)] } {
+        return
+    }
+
+    # Save options
+    set old [list]
+    lappend old [gds rescale]
+    lappend old [gds readonly]
     gds rescale false
     gds readonly true
-    set gds_files_in $::env(CELL_GDS)
+
+    # Read GDS
+    set gds_files_in $::env($env_name)
     foreach gds_file $gds_files_in {
         puts "> gds read $gds_file"
         gds read $gds_file
     }
-    gds rescale $old_rescale
-    gds readonly $old_readonly
+
+    # Restore options
+    gds rescale [lindex $old 0]
+    gds readonly [lindex $old 1]
+}
+
+proc read_pdk_gds {} {
+    _read_gds CELL_GDS
 }
 
 proc read_macro_gds {} {
-    set old_rescale [gds rescale]
-    set old_readonly [gds readonly]
-    gds rescale false
-    gds readonly true
-    if { [info exist ::env(MACRO_GDS_FILES)] } {
-        set gds_files_in $::env(MACRO_GDS_FILES)
-        foreach gds_file $gds_files_in {
-            puts "> gds read $gds_file"
-            gds read $gds_file
-        }
-    }
-    gds rescale $old_rescale
-    gds readonly $old_readonly
+    _read_gds MACRO_GDS_FILES
 }
 
 proc read_macro_gds_blackbox {} {
@@ -104,35 +107,11 @@ proc read_macro_gds_blackbox {} {
 }
 
 proc read_extra_gds {} {
-    set old_rescale [gds rescale]
-    set old_readonly [gds readonly]
-    gds rescale false
-    gds readonly true
-    if {  [info exist ::env(EXTRA_GDS)] } {
-        set gds_files_in $::env(EXTRA_GDS)
-        foreach gds_file $gds_files_in {
-            puts "> gds read $gds_file"
-            gds read $gds_file
-        }
-    }
-    gds rescale $old_rescale
-    gds readonly $old_readonly
+    _read_gds EXTRA_GDS
 }
 
 proc read_pad_gds {} {
-    set old_rescale [gds rescale]
-    set old_readonly [gds readonly]
-    gds rescale false
-    gds readonly true
-    if { [info exist ::env(PAD_GDS)] } {
-        set gds_files_in $::env(PAD_GDS)
-        foreach gds_file $gds_files_in {
-            puts "> gds read $gds_file"
-            gds read $gds_file
-        }
-    }
-    gds rescale $old_rescale
-    gds readonly $old_readonly
+    _read_gds PAD_GDS
 }
 
 proc read_def {} {

{librelane-3.0.4 → librelane-3.1.0.dev2}/librelane/scripts/magic/drc.tcl

@@ -33,6 +33,10 @@ if { [info exists ::env(MAGIC_DRC_MAGLEFS)] } {
 gds noduplicates true
 gds readonly true
 
+# Enable maskhints so that DRC rules against generated layers are run
+# against the closest possible version to what's actually in the GDS
+gds maskhints true
+
 # Flatten cells
 if { [info exists ::env(MAGIC_GDS_FLATGLOB)] } {
     foreach {gds_flatglob} $::env(MAGIC_GDS_FLATGLOB) {

{librelane-3.0.4 → librelane-3.1.0.dev2}/librelane/scripts/odbpy/power_utils.py

@@ -52,8 +52,15 @@ class Design(object):
             netname_by_bit = {}
 
             for netname, info in yosys_design_object["netnames"].items():
-                for bit in info["bits"]:
-                    netname_by_bit[bit] = netname
+                assert len(info["bits"]) > 0
+                # Single bit net, return name directly
+                if len(info["bits"]) == 1:
+                    netname_by_bit[info["bits"][0]] = netname
+                # Append bit index to signal name
+                else:
+                    offset = info.get("offset", 0)
+                    for index, bit in enumerate(info["bits"]):
+                        netname_by_bit[bit] = f"{netname}[{offset + index}]"
 
             self.verilog_net_names_by_bit_by_module[top_module] = netname_by_bit
         return self.verilog_net_names_by_bit_by_module[top_module][target_bit]

{librelane-3.0.4 → librelane-3.1.0.dev2}/librelane/scripts/openroad/common/io.tcl

@@ -235,13 +235,6 @@ proc read_timing_info {args} {
             read_liberty -corner $corner_name $extra_lib
         }
     }
-    
-    if { [info exists ::env(PAD_LIBS) ] } {
-        foreach lib $::env(PAD_LIBS) {
-            puts "Reading gpio pad timing for the '$corner_name' corner at '$lib'…"
-            read_liberty -corner $corner_name $lib
-        }
-    }
 
     set blackbox_wildcard {/// sta-blackbox}
     foreach nl $::env(_CURRENT_CORNER_NETLISTS) {
@@ -343,13 +336,6 @@ proc read_pnr_libs {args} {
                 read_liberty -corner $corner_name $extra_lib
             }
         }
-        
-        if { [info exists ::env(PAD_LIBS) ] } {
-            foreach pad_lib $::env(PAD_LIBS) {
-                puts "Reading gpio pad timing library for the '$corner_name' corner at '$pad_lib'…"
-                read_liberty -corner $corner_name $pad_lib
-            }
-        }
     }
 }
 

{librelane-3.0.4 → librelane-3.1.0.dev2}/librelane/scripts/openroad/common/pad_cfg.tcl

@@ -20,6 +20,11 @@ puts "\[INFO\] Generating padring…"
 set block [ord::get_db_block]
 set units [$block getDefUnits]
 
+# Round a micrometer value to nanometer
+proc round_um_nm {value} {
+    return [expr double(round($value * 1000)) / 1000]
+}
+
 # Pad Placement Algorithm
 #
 # For all sides:
@@ -74,7 +79,10 @@ make_io_sites \
     -horizontal_site $::env(PAD_SITE_NAME) \
     -vertical_site $::env(PAD_SITE_NAME) \
     -corner_site $::env(PAD_CORNER_SITE_NAME) \
-    -offset $::env(PAD_EDGE_SPACING)
+    -offset $::env(PAD_EDGE_SPACING) \
+    -rotation_horizontal $::env(PAD_ROTATION_HORIZONTAL) \
+    -rotation_vertical $::env(PAD_ROTATION_VERTICAL) \
+    -rotation_corner $::env(PAD_ROTATION_CORNER)
 
 set sides {PAD_SOUTH PAD_EAST PAD_NORTH PAD_WEST}
 set vertical_sides [list PAD_EAST PAD_WEST]
@@ -125,15 +133,15 @@ foreach side $sides {
 
     set space_between_pads [expr $space_for_fill / ([llength $::env($side)] + 1)]
     puts "space_between_pads: $space_between_pads"
-    
-    # Round to minimum site width (min. filler)
-    set space_between_pads_min_filler [expr round(floor($space_between_pads / $pad_site_width) * $pad_site_width * 1000) / 1000]
-    puts "space_between_pads_min_filler: $space_between_pads_min_filler"
+
+    # Round to PAD_SPACING_MULTIPLE
+    set space_between_pads_multiple [round_um_nm [expr floor($space_between_pads / $::env(PAD_SPACING_MULTIPLE)) * $::env(PAD_SPACING_MULTIPLE)]]
+    puts "space_between_pads_multiple: $space_between_pads_multiple"
 
     # The spacing for the pads on the side (the remaining space)
-    set space_side [expr round(($space_for_fill - $space_between_pads_min_filler * ([llength $::env($side)] - 1)) / 2 * 1000) / 1000]
+    set space_side [round_um_nm [expr ($space_for_fill - $space_between_pads_multiple * ([llength $::env($side)] - 1)) / 2]]
     
-    if { $space_side != round(floor($space_side / $pad_site_width) * $pad_site_width * 1000) / 1000 } {
+    if { $space_side != [round_um_nm [expr floor($space_side / $pad_site_width) * $pad_site_width]] } {
         puts "\[Error\] The remaining area for the pads on the side ($space_side) is not divisible by the minimum site width (minimum filler: $pad_site_width)."
         exit 1
     }
@@ -150,7 +158,7 @@ foreach side $sides {
     # For all instances
     foreach inst_name $::env($side) {
         if { [set inst [$block findInst $inst_name]] == "NULL" } {
-            puts stderr "\[ERROR\] No instance $instance_name found."
+            puts stderr "\[ERROR\] No instance $inst_name found."
             exit 1
         }
         set master_name [[$inst getMaster] getName]
@@ -163,7 +171,7 @@ foreach side $sides {
         place_pad -row [dict get $row_names $side] -location $cur_pos $inst_name -master $master_name
         
         # Increment current position
-        set cur_pos [expr $cur_pos + $space_between_pads_min_filler + $width]
+        set cur_pos [expr $cur_pos + $space_between_pads_multiple + $width]
     }
 }
 
@@ -175,10 +183,18 @@ place_corners $::env(PAD_CORNER)
 puts "\[INFO\] Placing filler cells…"
 
 # Place filler cells
-place_io_fill -row IO_NORTH {*}$::env(PAD_FILLERS)
-place_io_fill -row IO_SOUTH {*}$::env(PAD_FILLERS)
-place_io_fill -row IO_WEST {*}$::env(PAD_FILLERS)
-place_io_fill -row IO_EAST {*}$::env(PAD_FILLERS)
+if {!$::env(PAD_TRIM_ROWS) || ($::env(PAD_NORTH) ne "")} { place_io_fill -row IO_NORTH {*}$::env(PAD_FILLERS) }
+if {!$::env(PAD_TRIM_ROWS) || ($::env(PAD_SOUTH) ne "")} { place_io_fill -row IO_SOUTH {*}$::env(PAD_FILLERS) }
+if {!$::env(PAD_TRIM_ROWS) || ($::env(PAD_WEST) ne "")} { place_io_fill -row IO_WEST {*}$::env(PAD_FILLERS) }
+if {!$::env(PAD_TRIM_ROWS) || ($::env(PAD_EAST) ne "")} { place_io_fill -row IO_EAST {*}$::env(PAD_FILLERS) }
+
+puts "\[INFO\] Deleting corner cells (if required)…"
+
+# Delete corner cells if required
+if {$::env(PAD_TRIM_ROWS) && ($::env(PAD_NORTH) eq "") && ($::env(PAD_WEST) eq "")} { odb::dbInst_destroy [$block findInst IO_CORNER_NORTH_WEST_INST] }
+if {$::env(PAD_TRIM_ROWS) && ($::env(PAD_NORTH) eq "") && ($::env(PAD_EAST) eq "")} { odb::dbInst_destroy [$block findInst IO_CORNER_NORTH_EAST_INST] }
+if {$::env(PAD_TRIM_ROWS) && ($::env(PAD_SOUTH) eq "") && ($::env(PAD_WEST) eq "")} { odb::dbInst_destroy [$block findInst IO_CORNER_SOUTH_WEST_INST] }
+if {$::env(PAD_TRIM_ROWS) && ($::env(PAD_SOUTH) eq "") && ($::env(PAD_EAST) eq "")} { odb::dbInst_destroy [$block findInst IO_CORNER_SOUTH_EAST_INST] }
 
 puts "\[INFO\] Connecting ring signals…"
 
@@ -243,3 +259,4 @@ if { [info exists ::env(PAD_PLACE_IO_TERMINALS)] } {
 # Remove io rows to avoid causing confusion with the other tools
 puts "\[INFO\] Removing I/O rows…"
 remove_io_rows
+

{librelane-3.0.4 → librelane-3.1.0.dev2}/librelane/scripts/openroad/common/pdn_cfg.tcl

@@ -139,6 +139,7 @@ if { $::env(PDN_CORE_RING) == 1 } {
         append_if_flag arg_list PDN_CORE_RING_ALLOW_OUT_OF_DIE -allow_out_of_die
         append_if_flag arg_list PDN_CORE_RING_CONNECT_TO_PADS -connect_to_pads
         append_if_equals arg_list PDN_EXTEND_TO "boundary" -extend_to_boundary
+        append_if_exists_argument arg_list PDN_CORE_RING_CONNECT_TO_PAD_LAYERS -connect_to_pad_layers
 
         set pdn_core_vertical_layer $::env(PDN_VERTICAL_LAYER)
         set pdn_core_horizontal_layer $::env(PDN_HORIZONTAL_LAYER)

{librelane-3.0.4 → librelane-3.1.0.dev2}/librelane/scripts/openroad/repair_design.tcl

@@ -33,12 +33,15 @@ if { $::env(DESIGN_REPAIR_REMOVE_BUFFERS) } {
     remove_buffers
 }
 
+# Use SYNTH_BUFFER_CELL as buffer, since OpenROAD may select a hold/delay buffer
+# See: https://github.com/librelane/librelane/pull/961
+
 if { $::env(DESIGN_REPAIR_BUFFER_INPUT_PORTS) } {
-    buffer_ports -inputs
+    buffer_ports -inputs -buffer_cell [lindex [split $::env(SYNTH_BUFFER_CELL) "/"] 0]
 }
 
 if { $::env(DESIGN_REPAIR_BUFFER_OUTPUT_PORTS) } {
-    buffer_ports -outputs
+    buffer_ports -outputs -buffer_cell [lindex [split $::env(SYNTH_BUFFER_CELL) "/"] 0]
 }
 
 set arg_list [list]

{librelane-3.0.4 → librelane-3.1.0.dev2}/librelane/scripts/pyosys/json_header.py

@@ -43,6 +43,11 @@ def json_header(
             "__librelane__",
             "__pnr__",
         ]
+        + (
+            [f"PAD_{config['PAD_CELL_LIBRARY']}"]
+            if "PAD_CELL_LIBRARY" in config
+            else []
+        )
         + (
             []
             if config.get("VERILOG_POWER_DEFINE") is None

{librelane-3.0.4 → librelane-3.1.0.dev2}/librelane/scripts/pyosys/synthesize.py

@@ -157,6 +157,7 @@ def librelane_synth(
 ):
 
     d.run_pass("hierarchy", "-check", "-top", top, "-nokeep_prints", "-nokeep_asserts")
+    d.run_pass("chformal", "-remove")
     librelane_proc(d, report_dir)
 
     if keep_hierarchy_min_cost:
@@ -251,12 +252,20 @@ def synthesize(
     extra = json.load(open(extra_in))
 
     includes = config.get("VERILOG_INCLUDE_DIRS") or []
-    defines = (config.get("VERILOG_DEFINES") or []) + [
-        f"PDK_{config['PDK'].replace('-','_')}",
-        f"SCL_{config['STD_CELL_LIBRARY']}",
-        "__librelane__",
-        "__pnr__",
-    ]
+    defines = (
+        (config.get("VERILOG_DEFINES") or [])
+        + [
+            f"PDK_{config['PDK'].replace('-','_')}",
+            f"SCL_{config['STD_CELL_LIBRARY']}",
+            "__librelane__",
+            "__pnr__",
+        ]
+        + (
+            [f"PAD_{config['PAD_CELL_LIBRARY']}"]
+            if "PAD_CELL_LIBRARY" in config
+            else []
+        )
+    )
 
     blackbox_models = extra["blackbox_models"]
     libs = extra["libs_synth"]

{librelane-3.0.4 → librelane-3.1.0.dev2}/librelane/steps/common_variables.py

@@ -263,6 +263,12 @@ pdn_variables = [
         default=False,
         pdk=True,
     ),
+    Variable(
+        "PDN_CORE_RING_CONNECT_TO_PAD_LAYERS",
+        Optional[List[str]],
+        "Restrict the pad pins layers to this list.",
+        pdk=True,
+    ),
     Variable(
         "PDN_CORE_RING_ALLOW_OUT_OF_DIE",
         bool,

{librelane-3.0.4 → librelane-3.1.0.dev2}/librelane/steps/klayout.py

@@ -171,7 +171,7 @@ class Render(KLayoutStep):
     id = "KLayout.Render"
     name = "Render Image (w/ KLayout)"
 
-    inputs = [DesignFormat.DEF]
+    inputs = []
     outputs = []
 
     config_vars = KLayoutStep.config_vars + [
@@ -216,10 +216,14 @@ class Render(KLayoutStep):
     def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
         views_updates: ViewsUpdate = {}
 
-        input_view = state_in[DesignFormat.DEF]
+        input_view = state_in.get(DesignFormat.DEF)
+
         if gds := state_in.get(DesignFormat.GDS):
             input_view = gds
 
+        if input_view is None:
+            raise StepError(f"{id} requires at least one of LEF or GDS as input.")
+
         assert isinstance(input_view, Path)
 
         klayout_render = os.path.join(
@@ -434,7 +438,7 @@ class DRC(KLayoutStep):
     Unlike most steps, the KLayout scripts vary quite wildly by PDK. If a PDK
     is not supported by this step, it will simply be skipped.
 
-    Currently, only sky130A and sky130B are supported.
+    Currently, sky130, gf180mcu and ihp-sg13 are supported.
     """
 
     id = "KLayout.DRC"
@@ -455,7 +459,7 @@ class DRC(KLayoutStep):
         ),
         Variable(
             "KLAYOUT_DRC_OPTIONS",
-            Optional[Dict[str, Union[bool, int, str]]],
+            Optional[Dict[str, Union[int, bool, str]]],
             "Options passed directly to the KLayout DRC runset. They vary from one PDK to another.",
             pdk=True,
         ),
@@ -513,9 +517,6 @@ class DRC(KLayoutStep):
         if threads != "1":
             opts.extend(
                 [
-                    "-rd",
-                    f"thr={threads}",
-                    # Use "threads" if possible
                     "-rd",
                     f"threads={threads}",
                 ]
@@ -602,6 +603,8 @@ class DRC(KLayoutStep):
                 "-rd",
                 f"seal={seal}",
                 "-rd",
+                f"thr={threads}",
+                "-rd",
                 f"threads={threads}",
             ],
             env=env,
@@ -658,7 +661,7 @@ class DRC(KLayoutStep):
             opts.extend(
                 [
                     "-rd",
-                    f"thr={threads}",
+                    f"threads={threads}",
                 ]
             )
 
@@ -727,7 +730,7 @@ class DRC(KLayoutStep):
             opts.extend(
                 [
                     "-rd",
-                    f"thr={threads}",
+                    f"threads={threads}",
                 ]
             )
 

{librelane-3.0.4 → librelane-3.1.0.dev2}/librelane/steps/odb.py

@@ -972,7 +972,8 @@ class CellFrequencyTables(OdbpyStep):
         kwargs, env = self.extract_env(kwargs)
 
         env_copy = env.copy()
-        lib_list = self.toolbox.filter_views(self.config, self.config["LIB"])
+        lib_list = self.toolbox.filter_views(self.config, self.config["CELL_LIBS"])
+        lib_list += self.toolbox.filter_views(self.config, self.config["PAD_LIBS"])
         env_copy["_PNR_LIBS"] = TclStep.value_to_tcl(lib_list)
         super().run_subprocess(
             [

{librelane-3.0.4 → librelane-3.1.0.dev2}/librelane/steps/openroad.py

@@ -317,7 +317,8 @@ class OpenROADStep(TclStep):
     def prepare_env(self, env: dict, state: State) -> dict:
         env = super().prepare_env(env, state)
 
-        lib_list = self.toolbox.filter_views(self.config, self.config["LIB"])
+        lib_list = self.toolbox.filter_views(self.config, self.config["CELL_LIBS"])
+        lib_list += self.toolbox.filter_views(self.config, self.config["PAD_LIBS"])
         lib_list += self.toolbox.get_macro_views(self.config, DesignFormat.LIB)
 
         env["_SDC_IN"] = self.config["PNR_SDC_FILE"] or self.config["FALLBACK_SDC"]
@@ -1266,6 +1267,19 @@ class PadRing(OpenROADStep):
             Optional[List[str]],
             "The pad instance names for the west pad row.",
         ),
+        Variable(
+            "PAD_SPACING_MULTIPLE",
+            Decimal,
+            "The spacing between the pad cells will be a multiple of this value. Please ensure that the remaining space on the sides is divisible by the minimum site width.",
+            default=1,
+            units="µm",
+        ),
+        Variable(
+            "PAD_TRIM_ROWS",
+            bool,
+            "If any of `PAD_[SOUTH|EAST|NORTH|WEST]` is empty, skip io fill for those rows and delete the corners with two neighbouring empty rows.",
+            default=False,
+        ),
     ]
 
     def get_script_path(self):
@@ -2239,7 +2253,8 @@ class IRDropReport(OpenROADStep):
         elif len(spefs_in) < 1:
             raise StepException("No SPEF file found for the default corner.")
 
-        libs_in = self.toolbox.filter_views(self.config, self.config["LIB"])
+        libs_in = self.toolbox.filter_views(self.config, self.config["CELL_LIBS"])
+        libs_in += self.toolbox.filter_views(self.config, self.config["PAD_LIBS"])
 
         if self.config["VSRC_LOC_FILES"] is None:
             self.warn(