librelane 3.0.4__tar.gz → 3.0.5__tar.gz

{librelane-3.0.4 → librelane-3.0.5}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: librelane
-Version: 3.0.4
+Version: 3.0.5
 Summary: An infrastructure for implementing chip design flows
 License-Expression: Apache-2.0
 Maintainer: Mohamed Gaber
@@ -23,7 +23,7 @@ Requires-Dist: lxml (>=4.9.0)
 Requires-Dist: psutil (>=5.9.0)
 Requires-Dist: pyyaml (>=5,<7)
 Requires-Dist: rapidfuzz (>=3.9.0,<4)
-Requires-Dist: rich (>=12,<15)
+Requires-Dist: rich (>=12,<16)
 Requires-Dist: semver (>=3.0.2,<4)
 Requires-Dist: yamlcore (>=0.0.2,<0.1.0)
 Project-URL: Bug Tracker, https://github.com/librelane/librelane/issues

{librelane-3.0.4 → librelane-3.0.5}/librelane/steps/pyosys.py

@@ -194,18 +194,6 @@ class PyosysStep(Step):
             deprecated_names=["FULL_ADDER_MAP"],
             pdk=True,
         ),
-        Variable(
-            "SYNTH_MUX_MAP",
-            Optional[Path],
-            "A path to a file containing the mux mapping for Yosys.",
-            pdk=True,
-        ),
-        Variable(
-            "SYNTH_MUX4_MAP",
-            Optional[Path],
-            "A path to a file containing the mux4 mapping for Yosys.",
-            pdk=True,
-        ),
         Variable(
             "SYNTH_CLOCKGATE_MIN_WIDTH",
             Optional[int],

{librelane-3.0.4 → librelane-3.0.5}/librelane/steps/yosys.py

@@ -196,18 +196,6 @@ class YosysStep(TclStep):
             deprecated_names=["FULL_ADDER_MAP"],
             pdk=True,
         ),
-        Variable(
-            "SYNTH_MUX_MAP",
-            Optional[Path],
-            "A path to a file containing the mux mapping for Yosys.",
-            pdk=True,
-        ),
-        Variable(
-            "SYNTH_MUX4_MAP",
-            Optional[Path],
-            "A path to a file containing the mux4 mapping for Yosys.",
-            pdk=True,
-        ),
         Variable(
             "YOSYS_LOG_LEVEL",
             Literal["ALL", "WARNING", "ERROR"],

{librelane-3.0.4 → librelane-3.0.5}/pyproject.toml

@@ -1,6 +1,6 @@
 [project]
 name = "librelane"
-version = "3.0.4"
+version = "3.0.5"
 description = "An infrastructure for implementing chip design flows"
 maintainers = [
     {name = "Mohamed Gaber", email = "donn@fossi-foundation.org"},
@@ -13,7 +13,7 @@ dependencies = [
   "click>=8,<8.3",
   "cloup>=3.0.5,<4",
   "pyyaml>=5,<7",
-  "rich>=12,<15",
+  "rich>=12,<16",
   "ciel>=2.3.1,<3",
   "lxml>=4.9.0",
   "deprecated>=1.2.10,<2",