librelane 3.0.3__tar.gz → 3.1.0.dev1__tar.gz

{librelane-3.0.3 → librelane-3.1.0.dev1}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: librelane
-Version: 3.0.3
+Version: 3.1.0.dev1
 Summary: An infrastructure for implementing chip design flows
 License-Expression: Apache-2.0
 Maintainer: Mohamed Gaber

{librelane-3.0.3 → librelane-3.1.0.dev1}/librelane/common/toolbox.py

@@ -232,10 +232,16 @@ class Toolbox(object):
 
         timing_corner = timing_corner or config["DEFAULT_CORNER"]
 
-        all_libs: List[Path] = self.filter_views(config, config["LIB"], timing_corner)
+        # Filter the cell libs
+        all_libs: List[Path] = self.filter_views(
+            config, config["CELL_LIBS"], timing_corner
+        )
         if len(all_libs) == 0:
             warn(f"No SCL lib files found for {timing_corner}.")
 
+        # Add optional I/O pad libs
+        all_libs += self.filter_views(config, config["PAD_LIBS"], timing_corner)
+
         all_netlists: List[Path] = []
         all_spefs: List[Tuple[str, Path]] = []
 

{librelane-3.0.3 → librelane-3.1.0.dev1}/librelane/config/config.py

@@ -833,11 +833,6 @@ class Config(GenericImmutableDict[str, Any]):
         if scl is not None:
             pdk_config[SpecialKeys.scl] = scl
 
-            # HACK: Prevent loading default SCL cfg vars for old openlane PDK
-            # configs
-            # For more info: https://github.com/librelane/librelane/issues/932
-            pdk_config["STD_CELL_LIBRARY_OPT"] = scl
-
         if pad is not None:
             pdk_config[SpecialKeys.pad] = pad
 

{librelane-3.0.3 → librelane-3.1.0.dev1}/librelane/config/flow.py

@@ -18,7 +18,7 @@
 import os
 
 from decimal import Decimal
-from typing import List, Optional, Dict, Sequence, Union, Tuple
+from typing import List, Optional, Dict, Sequence, Union, Tuple, Literal
 
 from .variable import Variable, Macro
 from ..common import Path, get_script_dir
@@ -127,9 +127,10 @@ scl_variables = [
         deprecated_names=["DECAP_CELL"],
     ),
     Variable(
-        "LIB",
+        "CELL_LIBS",
         Dict[str, List[Path]],
         "A map from corner patterns to a list of associated liberty files. Exactly one entry must match the `DEFAULT_CORNER`.",
+        deprecated_names=["LIB"],
         pdk=True,
     ),
     Variable(
@@ -427,9 +428,10 @@ option_variables = [
 
 pad_variables = [
     Variable(
-        "PAD_GDS",
-        Optional[List[Path]],
-        "Path(s) to IO pad GDS file(s).",
+        "PAD_LIBS",
+        Optional[Dict[str, List[Path]]],
+        "A map from corner patterns to a list of associated liberty files. Exactly one entry must match the `DEFAULT_CORNER`.",
+        default={},
         pdk=True,
     ),
     Variable(
@@ -438,6 +440,12 @@ pad_variables = [
         "Path(s) to IO pad LEF file(s).",
         pdk=True,
     ),
+    Variable(
+        "PAD_GDS",
+        Optional[List[Path]],
+        "Path(s) to IO pad GDS file(s).",
+        pdk=True,
+    ),
     Variable(
         "PAD_VERILOG_MODELS",
         Optional[List[Path]],
@@ -456,12 +464,6 @@ pad_variables = [
         description="A circuit-design language view of the io pad library.",
         pdk=True,
     ),
-    Variable(
-        "PAD_LIBS",
-        Optional[Dict[str, List[Path]]],
-        "A map from corner patterns to a list of associated liberty files. Exactly one entry must match the `DEFAULT_CORNER`.",
-        pdk=True,
-    ),
     Variable(
         "PAD_CORNER",
         Optional[List[str]],
@@ -535,6 +537,27 @@ pad_variables = [
         units="µm",
         pdk=True,
     ),
+    Variable(
+        "PAD_ROTATION_HORIZONTAL",
+        Optional[Literal["R0", "MY", "R90", "MXR90", "R180", "MX", "R270", "MYR90"]],
+        "Rotation to apply to the horizontal sites to ensure pads are placed correctly.",
+        default="R0",
+        pdk=True,
+    ),
+    Variable(
+        "PAD_ROTATION_VERTICAL",
+        Optional[Literal["R0", "MY", "R90", "MXR90", "R180", "MX", "R270", "MYR90"]],
+        "Rotation to apply to the vertical sites to ensure pads are placed correctly.",
+        default="R0",
+        pdk=True,
+    ),
+    Variable(
+        "PAD_ROTATION_CORNER",
+        Optional[Literal["R0", "MY", "R90", "MXR90", "R180", "MX", "R270", "MYR90"]],
+        "Rotation to apply to the corner sites to ensure pads are placed correctly.",
+        default="R0",
+        pdk=True,
+    ),
 ]
 
 flow_common_variables = pdk_variables + scl_variables + option_variables + pad_variables

{librelane-3.0.3 → librelane-3.1.0.dev1}/librelane/config/pdk_compat.py

@@ -203,9 +203,9 @@ def migrate_old_config(config: Mapping[str, Any]) -> Dict[str, Any]:
         corner = f"*_{pvt}"
         lib_sta[corner] = lib_list
 
-    if (
-        new["PDK"].startswith("sky130") or new["PDK"].startswith("gf180mcu")
-    ) and "LIB" not in config:
+    if (new["PDK"].startswith("sky130") or new["PDK"].startswith("gf180mcu")) and (
+        "LIB" not in config and "CELL_LIBS" not in config
+    ):
         process_sta("LIB_SYNTH")
         process_sta("LIB_SLOWEST")
         process_sta("LIB_FASTEST")

librelane-3.1.0.dev1/librelane/pdk_hashes.yaml

@@ -0,0 +1,3 @@
+sky130: d815bb30c9afdf9e264c276a8a2b533108dea3d0
+gf180mcu: d815bb30c9afdf9e264c276a8a2b533108dea3d0
+ihp-sg13g2: c4b8b4e5e7a05f375cca3815d51b3a37721fbf5c

{librelane-3.0.3 → librelane-3.1.0.dev1}/librelane/scripts/magic/common/read.tcl

@@ -56,34 +56,37 @@ proc read_pad_lef {} {
     }
 }
 
-proc read_pdk_gds {} {
-    set old_rescale [gds rescale]
-    set old_readonly [gds readonly]
+proc _read_gds {env_name} {
+    # Pre-check
+    if { ![info exist ::env($env_name)] } {
+        return
+    }
+
+    # Save options
+    set old [list]
+    lappend old [gds rescale]
+    lappend old [gds readonly]
     gds rescale false
     gds readonly true
-    set gds_files_in $::env(CELL_GDS)
+
+    # Read GDS
+    set gds_files_in $::env($env_name)
     foreach gds_file $gds_files_in {
         puts "> gds read $gds_file"
         gds read $gds_file
     }
-    gds rescale $old_rescale
-    gds readonly $old_readonly
+
+    # Restore options
+    gds rescale [lindex $old 0]
+    gds readonly [lindex $old 1]
+}
+
+proc read_pdk_gds {} {
+    _read_gds CELL_GDS
 }
 
 proc read_macro_gds {} {
-    set old_rescale [gds rescale]
-    set old_readonly [gds readonly]
-    gds rescale false
-    gds readonly true
-    if { [info exist ::env(MACRO_GDS_FILES)] } {
-        set gds_files_in $::env(MACRO_GDS_FILES)
-        foreach gds_file $gds_files_in {
-            puts "> gds read $gds_file"
-            gds read $gds_file
-        }
-    }
-    gds rescale $old_rescale
-    gds readonly $old_readonly
+    _read_gds MACRO_GDS_FILES
 }
 
 proc read_macro_gds_blackbox {} {
@@ -104,35 +107,11 @@ proc read_macro_gds_blackbox {} {
 }
 
 proc read_extra_gds {} {
-    set old_rescale [gds rescale]
-    set old_readonly [gds readonly]
-    gds rescale false
-    gds readonly true
-    if {  [info exist ::env(EXTRA_GDS)] } {
-        set gds_files_in $::env(EXTRA_GDS)
-        foreach gds_file $gds_files_in {
-            puts "> gds read $gds_file"
-            gds read $gds_file
-        }
-    }
-    gds rescale $old_rescale
-    gds readonly $old_readonly
+    _read_gds EXTRA_GDS
 }
 
 proc read_pad_gds {} {
-    set old_rescale [gds rescale]
-    set old_readonly [gds readonly]
-    gds rescale false
-    gds readonly true
-    if { [info exist ::env(PAD_GDS)] } {
-        set gds_files_in $::env(PAD_GDS)
-        foreach gds_file $gds_files_in {
-            puts "> gds read $gds_file"
-            gds read $gds_file
-        }
-    }
-    gds rescale $old_rescale
-    gds readonly $old_readonly
+    _read_gds PAD_GDS
 }
 
 proc read_def {} {

{librelane-3.0.3 → librelane-3.1.0.dev1}/librelane/scripts/magic/drc.tcl

@@ -32,6 +32,10 @@ if { [info exists ::env(MAGIC_DRC_MAGLEFS)] } {
 gds noduplicates true
 gds readonly true
 
+# Enable maskhints so that DRC rules against generated layers are run
+# against the closest possible version to what's actually in the GDS
+gds maskhints true
+
 # Flatten cells
 if { [info exists ::env(MAGIC_GDS_FLATGLOB)] } {
     foreach {gds_flatglob} $::env(MAGIC_GDS_FLATGLOB) {

{librelane-3.0.3 → librelane-3.1.0.dev1}/librelane/scripts/openroad/common/io.tcl

@@ -235,13 +235,6 @@ proc read_timing_info {args} {
             read_liberty -corner $corner_name $extra_lib
         }
     }
-    
-    if { [info exists ::env(PAD_LIBS) ] } {
-        foreach lib $::env(PAD_LIBS) {
-            puts "Reading gpio pad timing for the '$corner_name' corner at '$lib'…"
-            read_liberty -corner $corner_name $lib
-        }
-    }
 
     set blackbox_wildcard {/// sta-blackbox}
     foreach nl $::env(_CURRENT_CORNER_NETLISTS) {
@@ -343,13 +336,6 @@ proc read_pnr_libs {args} {
                 read_liberty -corner $corner_name $extra_lib
             }
         }
-        
-        if { [info exists ::env(PAD_LIBS) ] } {
-            foreach pad_lib $::env(PAD_LIBS) {
-                puts "Reading gpio pad timing library for the '$corner_name' corner at '$pad_lib'…"
-                read_liberty -corner $corner_name $pad_lib
-            }
-        }
     }
 }
 
@@ -602,11 +588,7 @@ proc write_libs {} {
         foreach corner_name [lln::get_corner_names] {
             set target $::env(_LIB_SAVE_DIR)/$::env(DESIGN_NAME)__$corner_name.lib
             puts "Writing timing models for the $corner_name corner to $target…"
-            if {[string length [namespace which sta::scenes]] != 0} {
-                write_timing_model -scene $corner_name $target
-            } else {
-                write_timing_model -corner $corner_name $target
-            }
+            write_timing_model -corner $corner_name $target
         }
     }
 }

{librelane-3.0.3 → librelane-3.1.0.dev1}/librelane/scripts/openroad/common/pad_cfg.tcl

@@ -74,7 +74,10 @@ make_io_sites \
     -horizontal_site $::env(PAD_SITE_NAME) \
     -vertical_site $::env(PAD_SITE_NAME) \
     -corner_site $::env(PAD_CORNER_SITE_NAME) \
-    -offset $::env(PAD_EDGE_SPACING)
+    -offset $::env(PAD_EDGE_SPACING) \
+    -rotation_horizontal $::env(PAD_ROTATION_HORIZONTAL) \
+    -rotation_vertical $::env(PAD_ROTATION_VERTICAL) \
+    -rotation_corner $::env(PAD_ROTATION_CORNER)
 
 set sides {PAD_SOUTH PAD_EAST PAD_NORTH PAD_WEST}
 set vertical_sides [list PAD_EAST PAD_WEST]
@@ -150,7 +153,7 @@ foreach side $sides {
     # For all instances
     foreach inst_name $::env($side) {
         if { [set inst [$block findInst $inst_name]] == "NULL" } {
-            puts stderr "\[ERROR\] No instance $instance_name found."
+            puts stderr "\[ERROR\] No instance $inst_name found."
             exit 1
         }
         set master_name [[$inst getMaster] getName]

{librelane-3.0.3 → librelane-3.1.0.dev1}/librelane/scripts/openroad/common/pdn_cfg.tcl

@@ -139,6 +139,7 @@ if { $::env(PDN_CORE_RING) == 1 } {
         append_if_flag arg_list PDN_CORE_RING_ALLOW_OUT_OF_DIE -allow_out_of_die
         append_if_flag arg_list PDN_CORE_RING_CONNECT_TO_PADS -connect_to_pads
         append_if_equals arg_list PDN_EXTEND_TO "boundary" -extend_to_boundary
+        append_if_exists_argument arg_list PDN_CORE_RING_CONNECT_TO_PAD_LAYERS -connect_to_pad_layers
 
         set pdn_core_vertical_layer $::env(PDN_VERTICAL_LAYER)
         set pdn_core_horizontal_layer $::env(PDN_HORIZONTAL_LAYER)

{librelane-3.0.3 → librelane-3.1.0.dev1}/librelane/steps/common_variables.py

@@ -263,6 +263,12 @@ pdn_variables = [
         default=False,
         pdk=True,
     ),
+    Variable(
+        "PDN_CORE_RING_CONNECT_TO_PAD_LAYERS",
+        Optional[List[str]],
+        "Restrict the pad pins layers to this list.",
+        pdk=True,
+    ),
     Variable(
         "PDN_CORE_RING_ALLOW_OUT_OF_DIE",
         bool,
@@ -280,7 +286,7 @@ pdn_variables = [
     Variable(
         "PDN_RAIL_WIDTH",
         Decimal,
-        "Defines the width of PDN rails on the `PDN_RAIL_LAYER` layer.",
+        "Defines the width of PDN rails on the `FP_PDN_RAILS_LAYER` layer.",
         units="µm",
         pdk=True,
         deprecated_names=["FP_PDN_RAIL_WIDTH"],

{librelane-3.0.3 → librelane-3.1.0.dev1}/librelane/steps/odb.py

@@ -972,7 +972,8 @@ class CellFrequencyTables(OdbpyStep):
         kwargs, env = self.extract_env(kwargs)
 
         env_copy = env.copy()
-        lib_list = self.toolbox.filter_views(self.config, self.config["LIB"])
+        lib_list = self.toolbox.filter_views(self.config, self.config["CELL_LIBS"])
+        lib_list += self.toolbox.filter_views(self.config, self.config["PAD_LIBS"])
         env_copy["_PNR_LIBS"] = TclStep.value_to_tcl(lib_list)
         super().run_subprocess(
             [

{librelane-3.0.3 → librelane-3.1.0.dev1}/librelane/steps/openroad.py

@@ -317,7 +317,8 @@ class OpenROADStep(TclStep):
     def prepare_env(self, env: dict, state: State) -> dict:
         env = super().prepare_env(env, state)
 
-        lib_list = self.toolbox.filter_views(self.config, self.config["LIB"])
+        lib_list = self.toolbox.filter_views(self.config, self.config["CELL_LIBS"])
+        lib_list += self.toolbox.filter_views(self.config, self.config["PAD_LIBS"])
         lib_list += self.toolbox.get_macro_views(self.config, DesignFormat.LIB)
 
         env["_SDC_IN"] = self.config["PNR_SDC_FILE"] or self.config["FALLBACK_SDC"]
@@ -2239,7 +2240,8 @@ class IRDropReport(OpenROADStep):
         elif len(spefs_in) < 1:
             raise StepException("No SPEF file found for the default corner.")
 
-        libs_in = self.toolbox.filter_views(self.config, self.config["LIB"])
+        libs_in = self.toolbox.filter_views(self.config, self.config["CELL_LIBS"])
+        libs_in += self.toolbox.filter_views(self.config, self.config["PAD_LIBS"])
 
         if self.config["VSRC_LOC_FILES"] is None:
             self.warn(

{librelane-3.0.3 → librelane-3.1.0.dev1}/librelane/steps/pyosys.py

@@ -294,9 +294,13 @@ class VerilogStep(PyosysStep):
 
         blackbox_models = []
         scl_lib_list = self.toolbox.filter_views(
-            self.config, self.config["LIB"], self.config.get("SYNTH_CORNER")
+            self.config, self.config["CELL_LIBS"], self.config.get("SYNTH_CORNER")
+        )
+        pad_lib_list = self.toolbox.filter_views(
+            self.config, self.config["PAD_LIBS"], self.config.get("SYNTH_CORNER")
         )
 
+        # Try your best to use powered blackbox models if power_defines is true
         if self.power_defines:
             if self.config["CELL_VERILOG_MODELS"] is not None:
                 blackbox_models.extend(
@@ -317,7 +321,8 @@ class VerilogStep(PyosysStep):
                     ]
                 )
         else:
-            blackbox_models.extend(str(f) for f in scl_lib_list)
+            # Fall back to scl_lib_list and pad_lib_list if you cant
+            blackbox_models.extend(str(f) for f in scl_lib_list + pad_lib_list)
 
         # Priorities from higher to lower
         format_list = (
@@ -352,7 +357,7 @@ class VerilogStep(PyosysStep):
         excluded_cells.update(process_list_file(self.config["PNR_EXCLUDED_CELL_FILE"]))
 
         libs_synth = self.toolbox.remove_cells_from_lib(
-            frozenset([str(lib) for lib in scl_lib_list]),
+            frozenset([str(lib) for lib in scl_lib_list + pad_lib_list]),
             excluded_cells=frozenset(excluded_cells),
         )
         extra_path = os.path.join(self.step_dir, "extra.json")

{librelane-3.0.3 → librelane-3.1.0.dev1}/librelane/steps/verilator.py

@@ -77,12 +77,6 @@ class Lint(Step):
             "When a latch is inferred by an `always` block that is not explicitly marked as `always_latch`, report this as a linter error.",
             default=True,
         ),
-        Variable(
-            "LINTER_ERROR_ON_MULTIDRIVEN",
-            bool,
-            "When a net has multiple drivers, report this as a linter error.",
-            default=True,
-        ),
         Variable(
             "VERILOG_DEFINES",
             Optional[List[str]],
@@ -203,10 +197,6 @@ class Lint(Step):
         if self.config["LINTER_ERROR_ON_LATCH"]:
             extra_args.append("--Werror-LATCH")
 
-        # It's more user-friendly to catch multiple-driver conflicts here in Verilator (if possible) than later in Yosys.
-        if self.config["LINTER_ERROR_ON_MULTIDRIVEN"]:
-            extra_args.append("--Werror-MULTIDRIVEN")
-
         if include_dirs := self.config["VERILOG_INCLUDE_DIRS"]:
             extra_args.extend([f"-I{dir}" for dir in include_dirs])
 

{librelane-3.0.3 → librelane-3.1.0.dev1}/librelane/steps/yosys.py

@@ -69,7 +69,8 @@ def _generate_read_deps(
                 f"lappend ::_synlig_defines {TclUtils.escape(f'+define+{define}')}\n"
             )
 
-    scl_lib_list = toolbox.filter_views(config, config["LIB"])
+    scl_lib_list = toolbox.filter_views(config, config["CELL_LIBS"])
+    pad_lib_list = toolbox.filter_views(config, config["PAD_LIBS"])
 
     if power_defines:
         if power_define := config.get(
@@ -94,8 +95,8 @@ def _generate_read_deps(
             )
             commands += f"read_verilog -sv -lib {pad_blackbox_models}\n"
     else:
-        # Fall back to scl_lib_list if you cant
-        for lib in scl_lib_list:
+        # Fall back to scl_lib_list and pad_lib_list if you cant
+        for lib in scl_lib_list + pad_lib_list:
             lib_str = TclUtils.escape(str(lib))
             commands += (
                 f"read_liberty -lib -ignore_miss_dir -setattr blackbox {lib_str}\n"
@@ -106,7 +107,7 @@ def _generate_read_deps(
     excluded_cells.update(process_list_file(config["PNR_EXCLUDED_CELL_FILE"]))
 
     lib_synth = toolbox.remove_cells_from_lib(
-        frozenset([str(lib) for lib in scl_lib_list]),
+        frozenset([str(lib) for lib in scl_lib_list + pad_lib_list]),
         excluded_cells=frozenset(excluded_cells),
     )
     if tcl:

{librelane-3.0.3 → librelane-3.1.0.dev1}/pyproject.toml

@@ -1,6 +1,6 @@
 [project]
 name = "librelane"
-version = "3.0.3"
+version = "3.1.0.dev1"
 description = "An infrastructure for implementing chip design flows"
 maintainers = [
     {name = "Mohamed Gaber", email = "donn@fossi-foundation.org"},

librelane-3.0.3/librelane/pdk_hashes.yaml

@@ -1,3 +0,0 @@
-sky130: 8afc8346a57fe1ab7934ba5a6056ea8b43078e71
-gf180mcu: 54435919abffb937387ec956209f9cf5fd2dfbee
-ihp-sg13g2: c4b8b4e5e7a05f375cca3815d51b3a37721fbf5c