librelane 3.0.2__tar.gz → 3.0.3__tar.gz

{librelane-3.0.2 → librelane-3.0.3}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: librelane
-Version: 3.0.2
+Version: 3.0.3
 Summary: An infrastructure for implementing chip design flows
 License-Expression: Apache-2.0
 Maintainer: Mohamed Gaber

{librelane-3.0.2 → librelane-3.0.3}/librelane/config/config.py

@@ -833,6 +833,11 @@ class Config(GenericImmutableDict[str, Any]):
         if scl is not None:
             pdk_config[SpecialKeys.scl] = scl
 
+            # HACK: Prevent loading default SCL cfg vars for old openlane PDK
+            # configs
+            # For more info: https://github.com/librelane/librelane/issues/932
+            pdk_config["STD_CELL_LIBRARY_OPT"] = scl
+
         if pad is not None:
             pdk_config[SpecialKeys.pad] = pad
 

{librelane-3.0.2 → librelane-3.0.3}/librelane/scripts/openroad/common/io.tcl

@@ -602,7 +602,11 @@ proc write_libs {} {
         foreach corner_name [lln::get_corner_names] {
             set target $::env(_LIB_SAVE_DIR)/$::env(DESIGN_NAME)__$corner_name.lib
             puts "Writing timing models for the $corner_name corner to $target…"
-            write_timing_model -corner $corner_name $target
+            if {[string length [namespace which sta::scenes]] != 0} {
+                write_timing_model -scene $corner_name $target
+            } else {
+                write_timing_model -corner $corner_name $target
+            }
         }
     }
 }

{librelane-3.0.2 → librelane-3.0.3}/librelane/steps/common_variables.py

@@ -280,7 +280,7 @@ pdn_variables = [
     Variable(
         "PDN_RAIL_WIDTH",
         Decimal,
-        "Defines the width of PDN rails on the `FP_PDN_RAILS_LAYER` layer.",
+        "Defines the width of PDN rails on the `PDN_RAIL_LAYER` layer.",
         units="µm",
         pdk=True,
         deprecated_names=["FP_PDN_RAIL_WIDTH"],

{librelane-3.0.2 → librelane-3.0.3}/librelane/steps/verilator.py

@@ -77,6 +77,12 @@ class Lint(Step):
             "When a latch is inferred by an `always` block that is not explicitly marked as `always_latch`, report this as a linter error.",
             default=True,
         ),
+        Variable(
+            "LINTER_ERROR_ON_MULTIDRIVEN",
+            bool,
+            "When a net has multiple drivers, report this as a linter error.",
+            default=True,
+        ),
         Variable(
             "VERILOG_DEFINES",
             Optional[List[str]],
@@ -197,6 +203,10 @@ class Lint(Step):
         if self.config["LINTER_ERROR_ON_LATCH"]:
             extra_args.append("--Werror-LATCH")
 
+        # It's more user-friendly to catch multiple-driver conflicts here in Verilator (if possible) than later in Yosys.
+        if self.config["LINTER_ERROR_ON_MULTIDRIVEN"]:
+            extra_args.append("--Werror-MULTIDRIVEN")
+
         if include_dirs := self.config["VERILOG_INCLUDE_DIRS"]:
             extra_args.extend([f"-I{dir}" for dir in include_dirs])
 

{librelane-3.0.2 → librelane-3.0.3}/pyproject.toml

@@ -1,6 +1,6 @@
 [project]
 name = "librelane"
-version = "3.0.2"
+version = "3.0.3"
 description = "An infrastructure for implementing chip design flows"
 maintainers = [
     {name = "Mohamed Gaber", email = "donn@fossi-foundation.org"},