librelane 3.0.0.dev49__tar.gz → 3.0.0.dev51__tar.gz

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: librelane
-Version: 3.0.0.dev49
+Version: 3.0.0.dev51
 Summary: An infrastructure for implementing chip design flows
 License-Expression: Apache-2.0
 Maintainer: Mohamed Gaber

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/__main__.py

@@ -122,13 +122,13 @@ def run(
                     err(f"Invalid initial state element override: '{element}'.")
                     ctx.exit(1)
                 df_id, path = element_split
-                design_format = DesignFormat.by_id(df_id)
+                design_format = DesignFormat.factory.get(df_id)
                 if design_format is None:
                     err(f"Invalid design format ID: '{df_id}'.")
                     ctx.exit(1)
                 overrides[design_format] = common.Path(path)
 
-            with_initial_state = with_initial_state.__class__(
+            with_initial_state = type(with_initial_state)(
                 with_initial_state,
                 overrides=overrides,
             )

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/__version__.py

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane 2
+#
 # Copyright 2023 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -11,32 +15,33 @@
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 # See the License for the specific language governing permissions and
 # limitations under the License.
-import os
-import importlib.metadata
 import sys
+from pathlib import Path
+import importlib.metadata
+
+__file_dir__ = Path(__file__).absolute().parent
 
 
-def __get_version():
+def __get_version(pkg_name: str):
     try:
         return importlib.metadata.version(__package__ or __name__)
     except importlib.metadata.PackageNotFoundError:
         import re
 
         rx = re.compile(r"version\s*=\s*\"([^\"]+)\"")
-        librelane_directory = os.path.dirname(
-            os.path.dirname(os.path.abspath(__file__))
-        )
-        pyproject_path = os.path.join(librelane_directory, "pyproject.toml")
+        pyproject_toml_dir = __file_dir__.parent
+        pyproject_path = pyproject_toml_dir / "pyproject.toml"
         try:
-            match = rx.search(open(pyproject_path, encoding="utf8").read())
+            with open(pyproject_path, encoding="utf8") as f:
+                match = rx.search(f.read())
             assert match is not None, "pyproject.toml found, but without a version"
             return match[1]
         except FileNotFoundError:
-            print("Warning: Failed to extract LibreLane version.", file=sys.stderr)
+            print(f"Warning: Failed to extract {pkg_name} version.", file=sys.stderr)
             return "UNKNOWN"
 
 
-__version__ = __get_version()
+__version__ = __get_version("librelane")
 
 
 if __name__ == "__main__":

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/common/drc.py

@@ -225,6 +225,7 @@ class DRC:
         violations: Dict[str, Violation] = {}
         last_bounding_box: Optional[BoundingBox] = None
         lex = shlex.shlex(feedback.read(), posix=True)
+        lex.wordchars = lex.wordchars + "-"
         components = list(lex)
         while len(components):
             instruction = components.pop(0)

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/config/flow.py

@@ -297,7 +297,7 @@ scl_variables = [
     Variable(
         "DIODE_CELL",
         Optional[str],
-        "Defines a diode cell used to fix antenna violations, in the format {name}/{port}. If not defined, steps should not attempt to repair the antenna effect by inserting diode cells.",
+        "Defines a diode cell used to fix antenna violations, in the format `{cell}/{port}`. If not defined, steps should not attempt to repair the antenna effect by inserting diode cells.",
         pdk=True,
     ),
     Variable(

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/config/removals.py

@@ -44,4 +44,5 @@ removed_variables: Dict[str, str] = {
     "FP_CONTEXT_LEF": "To be implemented.",
     "SYNLIG_DEFER": "Synlig replaced with Slang.",
     "VDD_PIN_VOLTAGE": "Information should be obtained from dotlib files.",
+    "LIGHTER_DFF_MAP": "Lighter has been replaced with Yosys' built-in clock gate functionality.",
 }

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/flows/cli.py

@@ -17,9 +17,10 @@
 # limitations under the License.
 import os
 import sys
+import json
 from functools import partial, wraps
 from concurrent.futures import ThreadPoolExecutor
-from typing import Optional, Union
+from typing import Optional, Union, Tuple
 
 from click import (
     Context,
@@ -146,18 +147,27 @@ def set_worker_count_cb(
 def initial_state_cb(
     ctx: Context,
     param: Parameter,
-    value: Optional[str],
+    value: Tuple[str],
 ):
-    if value is None:
+    if len(value) == 0:
         return None
 
+    raw = {}
+    for state_json in value:
+        try:
+            with open(state_json, encoding="utf8") as f:
+                state_dict = json.load(f)
+                if not isinstance(state_dict, dict):
+                    raise ValueError(f"JSON data {value} is not a dictionary")
+                raw.update(state_dict)
+        except json.JSONDecodeError as e:
+            err(f"Invalid JSON file: {e}")
+            ctx.exit(-1)
+        except Exception as e:
+            err(f"Failed to read initial state: {e}")
+            ctx.exit(-1)
     try:
-        initial_state_str = open(value, encoding="utf8").read()
-    except Exception as e:
-        err(f"Failed to read initial state: {e}")
-        ctx.exit(-1)
-    try:
-        initial_state = State.loads(initial_state_str, validate_path=True)
+        initial_state = State.load(raw, validate_path=True)
     except InvalidState as e:
         err(e)
         ctx.exit(-1)
@@ -289,9 +299,9 @@ def cloup_flow_opts(
                     file_okay=True,
                     dir_okay=False,
                 ),
-                default=None,
+                multiple=True,
                 callback=initial_state_cb,
-                help="Use this JSON file as an initial state. If this is not specified, the latest `state_out.json` of the run directory will be used. If none exist, an empty initial state is created.",
+                help="Use these JSON files as an initial state. If multiple are provided, they are merged with keys in later files overriding keys in prior files. If none are specified, the latest `state_out.json` of the run directory will be used. If none exist, an empty initial state is created.",
             )(f)
             f = o(
                 "--design-dir",

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/scripts/klayout/stream_out.py

@@ -1,4 +1,8 @@
 #!/usr/bin/env python3
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane
+#
 # Copyright (c) 2021-2022 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -116,6 +120,10 @@ def stream_out(
         layout_options.lefdef_config.read_lef_with_def = False
         layout_options.lefdef_config.lef_files = list(input_lefs)
         layout_options.lefdef_config.map_file = lym
+        # Don't produce user properties
+        layout_options.lefdef_config.net_property_name = None
+        layout_options.lefdef_config.instance_property_name = None
+        layout_options.lefdef_config.pin_property_name = None
 
         cell_conflict_resolution = {
             "AddToCell": pya.LoadLayoutOptions.CellConflictResolution.AddToCell,

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/scripts/magic/def/mag_gds.tcl

@@ -98,5 +98,9 @@ if { $::env(MAGIC_GDS_POLYGON_SUBCELLS) } {
 	gds polygon subcells true
 }
 
+if { $::env(MAGIC_GDS_MERGE) } {
+	gds merge yes
+}
+
 gds write $::env(SAVE_MAG_GDS)
 puts "\[INFO\] GDS Write Complete"

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/scripts/openroad/antenna_repair.tcl

@@ -13,14 +13,18 @@
 # limitations under the License.
 source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
 read_current_odb
-source $::env(SCRIPTS_DIR)/openroad/common/dpl_cell_pad.tcl
 
-set_propagated_clock [all_clocks]
+set diode_cell [lindex [split $::env(DIODE_CELL) "/"] 0]
 
-source $::env(SCRIPTS_DIR)/openroad/common/grt.tcl
+set arg_list [list]
+lappend arg_list $diode_cell
+lappend arg_list -iterations $::env(GRT_ANTENNA_REPAIR_ITERS)
+lappend arg_list -ratio_margin $::env(GRT_ANTENNA_REPAIR_MARGIN)
+append_if_flag arg_list GRT_ALLOW_CONGESTION -allow_congestion
+append_if_flag arg_list GRT_ANTENNA_REPAIR_JUMPER_ONLY -jumper_only
+append_if_flag arg_list GRT_ANTENNA_REPAIR_DIODE_ONLY -diode_only
 
-set diode_split [split $::env(DIODE_CELL) "/"]
-repair_antennas "[lindex $diode_split 0]" -iterations $::env(GRT_ANTENNA_REPAIR_ITERS) -ratio_margin $::env(GRT_ANTENNA_REPAIR_MARGIN)
+log_cmd repair_antennas {*}$arg_list
 
 source $::env(SCRIPTS_DIR)/openroad/common/set_rc.tcl
 estimate_parasitics -global_routing

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/scripts/openroad/common/grt.tcl

@@ -23,9 +23,7 @@ if { ![info exists ::grt_preamble] } {
 set arg_list [list]
 lappend arg_list -congestion_iterations $::env(GRT_OVERFLOW_ITERS)
 lappend arg_list -verbose
-if { $::env(GRT_ALLOW_CONGESTION) == 1 } {
-    lappend arg_list -allow_congestion
-}
+append_if_flag arg_list GRT_ALLOW_CONGESTION -allow_congestion
 
 log_cmd global_route {*}$arg_list
 

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/scripts/openroad/drt.tcl

@@ -30,11 +30,6 @@ proc drt_run {i args} {
 source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
 read_current_odb
 
-# We need to call grt once, so that options like allow_congestion can be set for repair_antennas.
-# This needs to be done before drt. If grt is called after drt, repair_antennas only uses the
-# routing information from grt for fixing the antennas = useless.
-source $::env(SCRIPTS_DIR)/openroad/common/grt.tcl
-
 set_thread_count $::env(DRT_THREADS)
 
 set drc_report_iter_step_arg ""
@@ -65,10 +60,18 @@ if { ![info exists ::env(DIODE_CELL)] } {
 } else {
     set diode_cell [lindex [split $::env(DIODE_CELL) "/"] 0]
 
+    set arg_list [list]
+    lappend arg_list $diode_cell
+    lappend arg_list -ratio_margin $::env(GRT_ANTENNA_REPAIR_MARGIN)
+    append_if_flag arg_list GRT_ALLOW_CONGESTION -allow_congestion
+    append_if_flag arg_list DRT_ANTENNA_REPAIR_JUMPER_ONLY -jumper_only
+    append_if_flag arg_list DRT_ANTENNA_REPAIR_DIODE_ONLY -diode_only
+
     while {$i <= $::env(DRT_ANTENNA_REPAIR_ITERS) && [log_cmd check_antennas]} {
         puts "\[INFO\] Running antenna repair iteration $i…"
-        set diodes_inserted [log_cmd repair_antennas $diode_cell -ratio_margin $::env(DRT_ANTENNA_REPAIR_MARGIN)]
-        if {$diodes_inserted} {
+        set diodes_inserted [log_cmd repair_antennas {*}$arg_list]
+        
+        if {$diodes_inserted || $::env(DRT_ANTENNA_REPAIR_JUMPER_ONLY)} {
             drt_run $i {*}$drt_args
         } else {
             puts "\[INFO\] No diodes inserted. Ending antenna repair iterations."

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/scripts/pyosys/synthesize.py

@@ -240,13 +240,11 @@ def librelane_synth(
 @click.option("--output", type=click.Path(exists=False, dir_okay=False), required=True)
 @click.option("--config-in", type=click.Path(exists=True), required=True)
 @click.option("--extra-in", type=click.Path(exists=True), required=True)
-@click.option("--lighter-dff-map", type=click.Path(exists=True), required=False)
 @click.argument("inputs", nargs=-1)
 def synthesize(
     output,
     config_in,
     extra_in,
-    lighter_dff_map,
     inputs,
 ):
     config = json.load(open(config_in))
@@ -304,7 +302,8 @@ def synthesize(
         )
     elif vhdl_files := config.get("VHDL_FILES"):
         d.run_pass("plugin", "-i", "ghdl")
-        d.run_pass("ghdl", *vhdl_files, "-e", config["DESIGN_NAME"])
+        ghdl_arguments = config["GHDL_ARGUMENTS"] or []
+        d.run_pass("ghdl", *ghdl_arguments, *vhdl_files, "-e", config["DESIGN_NAME"])
     else:
         ys.log_error(
             "Script called inappropriately: config must include either VERILOG_FILES or VHDL_FILES.",
@@ -335,7 +334,7 @@ def synthesize(
 
     if config["SYNTH_ELABORATE_ONLY"]:
         librelane_proc(d, report_dir)
-        if config["SYNTH_ELABORATE_FLATTEN"]:
+        if config["SYNTH_HIERARCHY_MODE"] in ["deferred_flatten", "flatten"]:
             d.run_pass("flatten", "-noscopeinfo")
         d.run_pass("setattr", "-set", "keep", "1")
         d.run_pass("splitnets")
@@ -368,11 +367,6 @@ def synthesize(
             ys.log(f"[INFO] Applying {adder_type} mapping from '{mapping}'…")
             d.run_pass("techmap", "-map", mapping)
 
-    if mapping := lighter_dff_map:
-        ys.log(f"[INFO] Using Lighter with mapping '{mapping}'…")
-        d.run_pass("plugin", "-i", "lighter")
-        d.run_pass("reg_clock_gating", "-map", mapping)
-
     librelane_synth(
         d,
         config["DESIGN_NAME"],
@@ -422,6 +416,28 @@ def synthesize(
         ys.log(f"[INFO] Applying extra mappings from '{extra_mapping}'…")
         d.run_pass("techmap", "-map", extra_mapping)
 
+    if config["SYNTH_CLOCKGATE_MIN_WIDTH"] is not None:  # 0 is a valid value and falsey
+        cg_min_width = config["SYNTH_CLOCKGATE_MIN_WIDTH"]
+        posedge = ()
+        negedge = ()
+        if posedge_raw := config["SYNTH_CLOCKGATE_POSEDGE_ICG"]:
+            cell, ce, clk, gclk = posedge_raw.rsplit("/", maxsplit=4)
+            posedge = ("-pos", cell, f"{ce}:{clk}:{gclk}")
+        if negedge_raw := config["SYNTH_CLOCKGATE_NEGEDGE_ICG"]:
+            cell, ce, clk, gclk = negedge_raw.rsplit("/", maxsplit=4)
+            negedge = ("-neg", cell, f"{ce}:{clk}:{gclk}")
+        if len(posedge) == 0 and len(negedge) == 0:
+            ys.log(
+                "[WARNING] A minimum width for clock gating is set; but no ICGs are configured."
+            )
+        d.run_pass(
+            "clockgate",
+            "-min_net_size",
+            str(cg_min_width),
+            *posedge,
+            *negedge,
+        )
+
     dfflibmap_args = []
     for lib in libs:
         dfflibmap_args.extend(["-liberty", lib])

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/state/state.py

@@ -253,7 +253,7 @@ class State(GenericImmutableDict[str, StateElement]):
         self._walk(self.to_raw_dict(metrics=False), "", visit=visitor)
 
     @classmethod
-    def __loads_recursive(
+    def __load_recursive(
         Self,
         views: Dict,
         validate_path: bool = True,
@@ -267,7 +267,7 @@ class State(GenericImmutableDict[str, StateElement]):
                 continue
 
             if isinstance(value, dict):
-                target[key] = Self.__loads_recursive(
+                target[key] = Self.__load_recursive(
                     value,
                     validate_path,
                     key_path=current_key_path,
@@ -280,6 +280,15 @@ class State(GenericImmutableDict[str, StateElement]):
                 target[key] = Path(value)
         return target
 
+    @classmethod
+    def load(Self, dict_in: dict, validate_path: bool = True) -> "State":
+        metrics = dict_in.get("metrics")
+        if metrics is not None:
+            del dict_in["metrics"]
+
+        views = Self.__load_recursive(dict_in, validate_path)
+        return Self(views, metrics=metrics)
+
     @classmethod
     def loads(Self, json_in: str, validate_path: bool = True) -> "State":
         try:
@@ -290,14 +299,7 @@ class State(GenericImmutableDict[str, StateElement]):
         if not isinstance(raw, dict):
             raise InvalidState("Failed to load state: JSON result is not a dictionary")
 
-        metrics = raw.get("metrics")
-        if metrics is not None:
-            del raw["metrics"]
-
-        views = Self.__loads_recursive(raw, validate_path)
-        state = Self(views, metrics=metrics)
-
-        return state
+        return Self.load(raw, validate_path=validate_path)
 
     def __mapping_to_html_rec(
         self,

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/steps/common_variables.py

@@ -423,6 +423,18 @@ grt_variables = routing_layer_variables + [
         units="%",
         deprecated_names=["GRT_ANT_MARGIN", "GRT_ANTENNA_MARGIN"],
     ),
+    Variable(
+        "GRT_ANTENNA_REPAIR_JUMPER_ONLY",
+        bool,
+        "Only use jumpers to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_DIODE_ONLY.",
+        default=False,
+    ),
+    Variable(
+        "GRT_ANTENNA_REPAIR_DIODE_ONLY",
+        bool,
+        "Only use antenna diodes to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_JUMPER_ONLY.",
+        default=False,
+    ),
 ]
 
 rsz_variables = dpl_variables + [

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/steps/klayout.py

@@ -413,7 +413,7 @@ class DRC(KLayoutStep):
             metrics_updates = self.run_sky130(state_in, **kwargs)
         elif self.config["PDK"] in ["gf180mcuA", "gf180mcuB", "gf180mcuC", "gf180mcuD"]:
             metrics_updates = self.run_gf180mcu(state_in, **kwargs)
-        elif self.config["PDK"] in ["ihp-sg13g2"]:
+        elif self.config["PDK"] in ["ihp-sg13g2", "ihp-sg13cmos5l"]:
             metrics_updates = self.run_ihp_sg13g2(state_in, **kwargs)
         else:
             metrics_updates = self.run_generic(state_in, **kwargs)
@@ -821,7 +821,7 @@ class LVS(KLayoutStep):
     def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
         metrics_updates: MetricsUpdate = {}
         views_updates: ViewsUpdate = {}
-        if self.config["PDK"] in ["ihp-sg13g2"]:
+        if self.config["PDK"] in ["ihp-sg13g2", "ihp-sg13cmos5l"]:
             views_updates, metrics_updates = self.run_ihp_sg13g2(state_in, **kwargs)
         else:
             self.warn(
@@ -855,7 +855,7 @@ class SealRing(KLayoutStep):
     def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
         metrics_updates: MetricsUpdate = {}
         views_updates: ViewsUpdate = {}
-        if self.config["PDK"] in ["ihp-sg13g2"]:
+        if self.config["PDK"] in ["ihp-sg13g2", "ihp-sg13cmos5l"]:
             views_updates, metrics_updates = self.run_ihp_sg13g2(state_in, **kwargs)
         else:
             views_updates, metrics_updates = self.run_generic(state_in, **kwargs)
@@ -983,7 +983,14 @@ class Filler(KLayoutStep):
     def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
         metrics_updates: MetricsUpdate = {}
         views_updates: ViewsUpdate = {}
-        if self.config["PDK"] in ["ihp-sg13g2"]:
+
+        if not self.config["KLAYOUT_FILLER_SCRIPT"]:
+            self.warn(
+                f"KLAYOUT_FILLER_SCRIPT is unset. KLayout.Filler may not be supported for the {self.config['PDK']} PDK. This step will be skipped."
+            )
+            return views_updates, metrics_updates
+
+        if self.config["PDK"] in ["ihp-sg13g2", "ihp-sg13cmos5l"]:
             views_updates, metrics_updates = self.run_ihp_sg13g2(state_in, **kwargs)
         else:
             views_updates, metrics_updates = self.run_generic(state_in, **kwargs)
@@ -996,12 +1003,6 @@ class Filler(KLayoutStep):
         views_updates: ViewsUpdate = {}
         kwargs, env = self.extract_env(kwargs)
 
-        if not self.config["KLAYOUT_FILLER_SCRIPT"]:
-            self.warn(
-                f"KLAYOUT_FILLER_SCRIPT is unset. KLayout.Filler may not be supported for the {self.config['PDK']} PDK. This step will be skipped."
-            )
-            return views_updates, {}
-
         input_gds = state_in[DesignFormat.GDS]
         assert isinstance(input_gds, Path)
         output_gds = os.path.join(

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/steps/magic.py

@@ -98,7 +98,7 @@ class MagicStep(TclStep):
             "MAGIC_DEF_LABELS",
             bool,
             "A flag to choose whether labels are read with DEF files or not. From magic docs: \"The '-labels' option to the 'def read' command causes each net in the NETS and SPECIALNETS sections of the DEF file to be annotated with a label having the net name as the label text.\" If LVS fails, try disabling this option.",
-            default=True,
+            default=False,
         ),
         Variable(
             "MAGIC_GDS_POLYGON_SUBCELLS",
@@ -106,6 +106,12 @@ class MagicStep(TclStep):
             'A flag to enable polygon subcells in magic for gds read potentially speeding up magic. From magic docs: "Put non-Manhattan polygons. This prevents interations with other polygons on the same plane and so reduces tile splitting."',
             default=False,
         ),
+        Variable(
+            "MAGIC_GDS_MERGE",
+            bool,
+            'A flag to enable merging of connected tiles into polygons during gds write. From magic docs: "Depending on the tile geometry, this may make the output file up to four times smaller, at the cost of speed in generating the output file."',
+            default=True,
+        ),
         Variable(
             "MAGIC_DEF_NO_BLOCKAGES",
             bool,

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/steps/odb.py

@@ -93,8 +93,8 @@ class OdbpyStep(Step):
             str(state_in[DesignFormat.ODB]),
         ]
 
-        env["PYTHONPATH"] = (
-            f'{os.path.join(get_script_dir(), "odbpy")}:{env.get("PYTHONPATH")}'
+        env["PYTHONPATH"] = ":".join(
+            (env.get("PYTHONPATH", ""), os.path.join(get_script_dir(), "odbpy"))
         )
         check = False
         if "check" in kwargs:

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/steps/openroad.py

@@ -1934,6 +1934,18 @@ class DetailedRouting(OpenROADStep):
                 units="%",
                 deprecated_names=["DRT_ANTENNA_MARGIN"],
             ),
+            Variable(
+                "DRT_ANTENNA_REPAIR_JUMPER_ONLY",
+                bool,
+                "Only use jumpers to fix antenna violations. Cannot be used in conjunction with DRT_ANTENNA_REPAIR_DIODE_ONLY.",
+                default=False,
+            ),
+            Variable(
+                "DRT_ANTENNA_REPAIR_DIODE_ONLY",
+                bool,
+                "Only use antenna diodes to fix antenna violations. Cannot be used in conjunction with DRT_ANTENNA_REPAIR_JUMPER_ONLY.",
+                default=False,
+            ),
             Variable(
                 "DRT_SAVE_DRC_REPORT_ITERS",
                 Optional[int],

{librelane-3.0.0.dev49 → librelane-3.0.0.dev51}/librelane/steps/pyosys.py

@@ -22,7 +22,6 @@ import sys
 import json
 import fnmatch
 import shutil
-import subprocess
 from decimal import Decimal
 from abc import abstractmethod
 from typing import List, Literal, Optional, Set, Tuple
@@ -147,6 +146,18 @@ DesignFormat(
 ).register()
 
 
+def _validate_icg(
+    variable: Variable, input: Optional[str], warning_list_ref: List[str]
+):
+    if input is not None:
+        components = input.split("/")
+        if len(components) != 4:
+            raise ValueError(
+                f"{variable.name} must be in the form '<cell>/<ce>/<clk>/<gclk>'"
+            )
+    return input
+
+
 class PyosysStep(Step):
     config_vars = [
         Variable(
@@ -196,15 +207,24 @@ class PyosysStep(Step):
             pdk=True,
         ),
         Variable(
-            "USE_LIGHTER",
-            bool,
-            "Activates Lighter, an experimental plugin that attempts to optimize clock-gated flip-flops.",
-            default=False,
+            "SYNTH_CLOCKGATE_MIN_WIDTH",
+            Optional[int],
+            "If set to a value, a group of flip-flops with size >= SYNTH_CLOCKGATE_MIN_WIDTH and an enable signal are clock-gated instead.",
+            deprecated_names=[("USE_LIGHTER", lambda x: 1 if x else None)],
         ),
         Variable(
-            "LIGHTER_DFF_MAP",
-            Optional[Path],
-            "An override to the custom DFF map file provided for the given SCL by Lighter.",
+            "SYNTH_CLOCKGATE_POSEDGE_ICG",
+            Optional[str],
+            "The integrated clock gate cell used for positive-edge flip-flops, in the format `<cell>/<active-high clock enable port>/<clk port>/<gated clk port>`.",
+            pdk=True,
+            validator=_validate_icg,
+        ),
+        Variable(
+            "SYNTH_CLOCKGATE_NEGEDGE_ICG",
+            Optional[str],
+            "The integrated clock gate cell used for positive-edge flip-flops, in the format `<cell>/<active-high clock enable port>/<clk port>/<gated clk port>`.",
+            pdk=True,
+            validator=_validate_icg,
         ),
         Variable(
             "YOSYS_LOG_LEVEL",
@@ -253,12 +273,14 @@ class PyosysStep(Step):
 
     def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
         cmd = self.get_command(state_in)
+        kwargs, env = self.extract_env(kwargs)
         # HACK: Get Colab working
         if "google.colab" in sys.modules:
-            kwargs, env = self.extract_env(kwargs)
             env.pop("PATH", "")
-            kwargs["env"] = env
-        subprocess_result = super().run_subprocess(cmd, **kwargs)
+        env["PYTHONPATH"] = ":".join(
+            (env.get("PYTHONPATH", ""), os.path.join(get_script_dir(), "pyosys"))
+        )
+        subprocess_result = super().run_subprocess(cmd, env=env, **kwargs)
         return {}, subprocess_result["generated_metrics"]
 
 
@@ -477,7 +499,9 @@ class SynthesisCommon(VerilogStep):
                 (
                     "SYNTH_NO_FLAT",
                     lambda x: "deferred_flatten" if x else "flatten",
-                )
+                ),
+                ("SYNTH_ELABORATE_FLATTEN", lambda x: "flatten" if x else "keep"),
+                ("SYNTH_FLAT_TOP", lambda x: "flatten" if x else "keep"),
             ],
         ),
         Variable(
@@ -518,13 +542,6 @@ class SynthesisCommon(VerilogStep):
             '"Elaborate" the design only without attempting any logic mapping. Useful when dealing with structural Verilog netlists.',
             default=False,
         ),
-        Variable(
-            "SYNTH_ELABORATE_FLATTEN",
-            bool,
-            "If `SYNTH_ELABORATE_ONLY` is specified, this variable controls whether or not the top level should be flattened.",
-            default=True,
-            deprecated_names=["SYNTH_FLAT_TOP"],
-        ),
         Variable(
             "SYNTH_MUL_BOOTH",
             bool,
@@ -564,25 +581,7 @@ class SynthesisCommon(VerilogStep):
             self.step_dir,
             f"{self.config['DESIGN_NAME']}.{DesignFormat.NETLIST.extension}",
         )
-        cmd = super().get_command(state_in)
-        if self.config["USE_LIGHTER"]:
-            lighter_dff_map = self.config["LIGHTER_DFF_MAP"]
-            if lighter_dff_map is None:
-                scl = self.config["STD_CELL_LIBRARY"]
-                try:
-                    raw = subprocess.check_output(
-                        ["lighter_files", scl], encoding="utf8"
-                    )
-                    files = raw.strip().splitlines()
-                    lighter_dff_map = Path(files[0])
-                except FileNotFoundError:
-                    self.warn(
-                        "Lighter not found or not set up with LibreLane: If you're using a manual Lighter install, try setting LIGHTER_DFF_MAP explicitly."
-                    )
-                except subprocess.CalledProcessError:
-                    self.warn(f"{scl} not supported by Lighter.")
-            cmd.extend(["--lighter-dff-map", lighter_dff_map])
-        return cmd + ["--output", out_file]
+        return super().get_command(state_in) + ["--output", out_file]
 
     def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
         out_file = os.path.join(
@@ -704,4 +703,9 @@ class VHDLSynthesis(SynthesisCommon):
             List[Path],
             "The paths of the design's VHDL files.",
         ),
+        Variable(
+            "GHDL_ARGUMENTS",
+            Optional[List[str]],
+            "Pass arguments to the ghdl frontend.",
+        ),
     ]