librelane 3.0.0.dev48__tar.gz → 3.0.0.dev49__tar.gz

{librelane-3.0.0.dev48 → librelane-3.0.0.dev49}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: librelane
-Version: 3.0.0.dev48
+Version: 3.0.0.dev49
 Summary: An infrastructure for implementing chip design flows
 License-Expression: Apache-2.0
 Maintainer: Mohamed Gaber
@@ -48,10 +48,8 @@ Description-Content-Type: text/markdown
 
 LibreLane is an ASIC infrastructure library based on several components including
 OpenROAD, Yosys, Magic, Netgen, CVC, KLayout and a number of custom scripts for
-design exploration and optimization, currently developed and maintained by
-members and affiliates of the
-[American University in Cairo Open Hardware Lab](https://github.com/aucohl)
-under the stewardship of the [FOSSi Foundation](https://fossi-foundation.org).
+design exploration and optimization, currently developed and maintained under
+the stewardship of the [FOSSi Foundation](https://fossi-foundation.org).
 
 A reference flow, "Classic", performs all ASIC implementation steps from RTL all
 the way down to GDSII.

{librelane-3.0.0.dev48 → librelane-3.0.0.dev49}/Readme.md

@@ -14,10 +14,8 @@
 
 LibreLane is an ASIC infrastructure library based on several components including
 OpenROAD, Yosys, Magic, Netgen, CVC, KLayout and a number of custom scripts for
-design exploration and optimization, currently developed and maintained by
-members and affiliates of the
-[American University in Cairo Open Hardware Lab](https://github.com/aucohl)
-under the stewardship of the [FOSSi Foundation](https://fossi-foundation.org).
+design exploration and optimization, currently developed and maintained under
+the stewardship of the [FOSSi Foundation](https://fossi-foundation.org).
 
 A reference flow, "Classic", performs all ASIC implementation steps from RTL all
 the way down to GDSII.

{librelane-3.0.0.dev48 → librelane-3.0.0.dev49}/librelane/__main__.py

@@ -204,8 +204,10 @@ def print_version(ctx: click.Context, param: click.Parameter, value: bool):
         f"""
         LibreLane v{__version__}
 
-        Copyright ©2020-2025 Efabless Corporation, The American University in
-        Cairo, and other contributors.
+        Copyright ©2025-2026 LibreLane Contributors
+
+        Adapted from OpenLane 2.0
+        Copyright ©2020-2025 Efabless Corporation
 
         Available under the Apache License, version 2. Included with the source code,
         but you can also get a copy at https://www.apache.org/licenses/LICENSE-2.0

{librelane-3.0.0.dev48 → librelane-3.0.0.dev49}/librelane/flows/sequential.py

@@ -395,11 +395,6 @@ class SequentialFlow(Flow):
 
             if to_resolved and to_resolved == step.id:
                 executing = False
-        if len(deferred_errors) != 0:
-            raise FlowError(
-                "One or more deferred errors were encountered:\n"
-                + "\n".join(deferred_errors)
-            )
 
         assert self.run_dir is not None
         debug(f"Run concluded ▶ '{self.run_dir}'")
@@ -408,5 +403,12 @@ class SequentialFlow(Flow):
             current_state.save_snapshot(final_views_path)
         except Exception as e:
             raise FlowException(f"Failed to save final views: {e}")
+
+        if len(deferred_errors) != 0:
+            raise FlowError(
+                "One or more deferred errors were encountered:\n"
+                + "\n".join(deferred_errors)
+            )
+
         success("Flow complete.")
         return (current_state, step_list)

{librelane-3.0.0.dev48 → librelane-3.0.0.dev49}/librelane/scripts/klayout/open_design.py

@@ -27,6 +27,13 @@ def open_design(input_lefs: Tuple[str, ...], lyt: str, lyp: str, lym: str, input
 
         tech = pya.Technology()
         tech.load(lyt)
+        # Register the technology.
+        # Throws an exception if a technology
+        # with the same name already exists.
+        try:
+            pya.Technology().register_technology(tech)
+        except Exception:
+            print(f"Could not register the technology: {tech.name}.")
 
         layout_options = tech.load_layout_options
         layout_options.keep_other_cells = True
@@ -35,7 +42,7 @@ def open_design(input_lefs: Tuple[str, ...], lyt: str, lyp: str, lym: str, input
         layout_options.lefdef_config.lef_files = list(input_lefs)
         layout_options.lefdef_config.map_file = lym
 
-        cell_view = main_window.load_layout(input, layout_options, 0)
+        cell_view = main_window.load_layout(input, layout_options, tech.name, False)
         layout_view = cell_view.view()
         layout_view.load_layer_props(lyp)
     except Exception as e:

{librelane-3.0.0.dev48 → librelane-3.0.0.dev49}/librelane/scripts/pyosys/construct_abc_script.py

@@ -18,6 +18,8 @@ import re
 class ABCScriptCreator:
     def __init__(self, config):
         self.config = config
+        D = config["CLOCK_PERIOD"] * 1000  # ns -> ps
+        self.D = D
 
         self.rs_K = "resub -K "
         self.rs = "resub"
@@ -55,8 +57,8 @@ class ABCScriptCreator:
 
         self.map_old_area = "map -p -a -B 0.2 -A 0.9 -M 0"
         self.map_old_dly = "map -p -B 0.2 -A 0.9 -M 0"
-        self.retime_area = "retime {D} -M 5"
-        self.retime_dly = "retime {D} -M 6"
+        self.retime_area = "retime -M 5"
+        self.retime_dly = "retime -M 6"
         self.map_new_area = "amap -m -Q 0.1 -F 20 -A 20 -C 5000"
 
         if config["SYNTH_ABC_AREA_USE_NF"]:
@@ -71,11 +73,9 @@ class ABCScriptCreator:
             max_tr_arg = ""
             if self.max_transition != 0:
                 max_tr_arg = f" -S {self.max_transition}"
-            self.fine_tune = (
-                f"buffer -N {self.max_fanout}{max_tr_arg};upsize {{D}};dnsize {{D}}"
-            )
+            self.fine_tune = f"buffer -N {self.max_fanout}{max_tr_arg};upsize;dnsize"
         elif config["SYNTH_SIZING"]:
-            self.fine_tune = "upsize {D};dnsize {D}"
+            self.fine_tune = "upsize;dnsize"
 
     def generate_abc_script(self, step_dir, strategy):
         strategy_clean = re.sub(r"\s+", "_", strategy)
@@ -160,7 +160,7 @@ class ABCScriptCreator:
             else:
                 print(self.delay_mfs3, file=f)
 
-            print("retime {D}", file=f)
+            print("retime", file=f)
 
             # & space
             print("&get -n", file=f)

{librelane-3.0.0.dev48 → librelane-3.0.0.dev49}/pyproject.toml

@@ -1,6 +1,6 @@
 [project]
 name = "librelane"
-version = "3.0.0.dev48"
+version = "3.0.0.dev49"
 description = "An infrastructure for implementing chip design flows"
 maintainers = [
     {name = "Mohamed Gaber", email = "me@donn.website"}