librelane 3.0.0.dev38__tar.gz → 3.0.0.dev40__tar.gz

{librelane-3.0.0.dev38 → librelane-3.0.0.dev40}/PKG-INFO

@@ -1,41 +1,41 @@
-Metadata-Version: 2.1
+Metadata-Version: 2.4
 Name: librelane
-Version: 3.0.0.dev38
+Version: 3.0.0.dev40
 Summary: An infrastructure for implementing chip design flows
-Home-page: https://github.com/librelane/librelane
-License: Apache-2.0
-Author: Mohamed Gaber
-Author-email: me@donn.website
-Requires-Python: >=3.8.1,<4
-Classifier: License :: OSI Approved :: Apache Software License
+License-Expression: Apache-2.0
+Maintainer: Mohamed Gaber
+Maintainer-email: me@donn.website
+Requires-Python: >=3.10
 Classifier: Programming Language :: Python :: 3
-Classifier: Programming Language :: Python :: 3.9
 Classifier: Programming Language :: Python :: 3.10
 Classifier: Programming Language :: Python :: 3.11
 Classifier: Programming Language :: Python :: 3.12
 Classifier: Programming Language :: Python :: 3.13
-Requires-Dist: ciel (>=2.0.3,<3)
+Classifier: Programming Language :: Python :: 3.14
+Requires-Dist: ciel (>=2.3.1,<3)
 Requires-Dist: click (>=8,<8.2)
 Requires-Dist: cloup (>=3.0.5,<4)
 Requires-Dist: deprecated (>=1.2.10,<2)
 Requires-Dist: httpx (>=0.22.0,<0.29)
-Requires-Dist: klayout (>=0.29.0,<0.31.0)
-Requires-Dist: libparse (>=0.3.1,<1)
+Requires-Dist: klayout (>=0.29.0,<0.32.0)
+Requires-Dist: lln-libparse (==0.56.*)
 Requires-Dist: lxml (>=4.9.0)
 Requires-Dist: psutil (>=5.9.0)
 Requires-Dist: pyyaml (>=5,<7)
 Requires-Dist: rapidfuzz (>=3.9.0,<4)
 Requires-Dist: rich (>=12,<15)
-Requires-Dist: semver (>=3.0.2,<4.0.0)
-Requires-Dist: yamlcore (>=0.0.2,<0.0.3)
+Requires-Dist: semver (>=3.0.2,<4)
+Requires-Dist: yamlcore (>=0.0.2,<0.1.0)
+Project-URL: Bug Tracker, https://github.com/librelane/librelane/issues
 Project-URL: Documentation, https://librelane.readthedocs.io
+Project-URL: Homepage, https://librelane.org/
 Project-URL: Repository, https://github.com/librelane/librelane
 Description-Content-Type: text/markdown
 
 <h1 align="center">LibreLane</h1>
 <p align="center">
     <a href="https://opensource.org/licenses/Apache-2.0"><img src="https://img.shields.io/badge/License-Apache%202.0-blue.svg" alt="License: Apache 2.0"/></a>
-    <a href="https://www.python.org"><img src="https://img.shields.io/badge/Python-3.8-3776AB.svg?style=flat&logo=python&logoColor=white" alt="Python 3.8.1 or higher" /></a>
+    <a href="https://www.python.org"><img src="https://img.shields.io/badge/Python-3.10-3776AB.svg?style=flat&logo=python&logoColor=white" alt="Python ≥3.10" /></a>
     <a href="https://github.com/psf/black"><img src="https://img.shields.io/badge/code%20style-black-000000.svg" alt="Code Style: black"/></a>
     <a href="https://mypy-lang.org/"><img src="https://www.mypy-lang.org/static/mypy_badge.svg" alt="Checked with mypy"/></a>
     <a href="https://nixos.org/"><img src="https://img.shields.io/static/v1?logo=nixos&logoColor=white&label=&message=Built%20with%20Nix&color=41439a" alt="Built with Nix"/></a>
@@ -72,7 +72,7 @@ Colaboratory by following
 
 You'll need the following:
 
-* Python **3.8.1** or higher with PIP, Venv and Tkinter
+* Python **3.10** or higher with PIP, Venv and Tkinter
 
 ### Nix (Recommended)
 

{librelane-3.0.0.dev38 → librelane-3.0.0.dev40}/Readme.md

@@ -1,7 +1,7 @@
 <h1 align="center">LibreLane</h1>
 <p align="center">
     <a href="https://opensource.org/licenses/Apache-2.0"><img src="https://img.shields.io/badge/License-Apache%202.0-blue.svg" alt="License: Apache 2.0"/></a>
-    <a href="https://www.python.org"><img src="https://img.shields.io/badge/Python-3.8-3776AB.svg?style=flat&logo=python&logoColor=white" alt="Python 3.8.1 or higher" /></a>
+    <a href="https://www.python.org"><img src="https://img.shields.io/badge/Python-3.10-3776AB.svg?style=flat&logo=python&logoColor=white" alt="Python ≥3.10" /></a>
     <a href="https://github.com/psf/black"><img src="https://img.shields.io/badge/code%20style-black-000000.svg" alt="Code Style: black"/></a>
     <a href="https://mypy-lang.org/"><img src="https://www.mypy-lang.org/static/mypy_badge.svg" alt="Checked with mypy"/></a>
     <a href="https://nixos.org/"><img src="https://img.shields.io/static/v1?logo=nixos&logoColor=white&label=&message=Built%20with%20Nix&color=41439a" alt="Built with Nix"/></a>
@@ -38,7 +38,7 @@ Colaboratory by following
 
 You'll need the following:
 
-* Python **3.8.1** or higher with PIP, Venv and Tkinter
+* Python **3.10** or higher with PIP, Venv and Tkinter
 
 ### Nix (Recommended)
 

{librelane-3.0.0.dev38 → librelane-3.0.0.dev40}/librelane/common/metrics/__main__.py

@@ -358,9 +358,10 @@ def compare_remote(
                 for chunk in r.iter_bytes(chunk_size=8192):
                     bio_gz.write(chunk)
             bio_gz.seek(0)
-            with gzip.GzipFile(fileobj=bio_gz) as bio, tarfile.TarFile(
-                fileobj=bio, mode="r"
-            ) as tf:
+            with (
+                gzip.GzipFile(fileobj=bio_gz) as bio,
+                tarfile.TarFile(fileobj=bio, mode="r") as tf,
+            ):
                 for file in tf:
                     if file.isdir():
                         continue

{librelane-3.0.0.dev38 → librelane-3.0.0.dev40}/librelane/config/flow.py

@@ -107,13 +107,13 @@ pdk_variables = [
     Variable(
         "FP_IO_HLAYER",
         str,
-        "The metal layer on which to place horizontal IO pins, i.e., the top and bottom of the die.",
+        "The metal layer on which to place horizontally-aligned (long side parallel with the horizon) pins alongside the east and west edges of the die.",
         pdk=True,
     ),
     Variable(
         "FP_IO_VLAYER",
         str,
-        "The metal layer on which to place vertical IO pins, i.e., the top and bottom of the die.",
+        "The metal layer on which to place vertically-aligned (long side perpendicular to the horizon) pins alongside the north and south edges of the die.",
         pdk=True,
     ),
     Variable("RT_MIN_LAYER", str, "The lowest metal layer to route on.", pdk=True),

{librelane-3.0.0.dev38 → librelane-3.0.0.dev40}/librelane/config/variable.py

@@ -440,7 +440,7 @@ class Variable:
             return_value = list()
             raw = value
             if isinstance(raw, list) or isinstance(raw, tuple):
-                if validating_type == List[Path]:
+                if type_origin == list and type_args == (str,):
                     if any(isinstance(item, List) for item in raw):
                         Variable.__flatten_list(value)
                 pass

{librelane-3.0.0.dev38 → librelane-3.0.0.dev40}/librelane/flows/cli.py

@@ -218,27 +218,30 @@ def cloup_flow_opts(
     function decorated with @cloup.command (https://cloup.readthedocs.io/en/stable/autoapi/cloup/index.html#cloup.command).
 
     The following keyword arguments will be passed to the decorated function.
+
     * Those postfixed ‡ are compatible with the constructor for :class:`Flow`.
     * Those postfixed § are compatible with the :meth:`Flow.start`.
 
+    ---
+
     * Flow configuration options (if parameter ``config_options`` is ``True``):
         * ``flow_name``: ``Optional[str]``: A valid flow ID to be used with :meth:`Flow.factory.get`
-        * ``config_override_strings``‡: ``Optional[Iterable[str]]``
+        * ``config_override_strings`` ‡: ``Optional[Iterable[str]]``
     * Sequential flow controls (if parameter ``sequential_flow_controls`` is ``True``)
-        * ``frm``§: ``Optional[str]``: Start from a step with this ID. Supported by sequential flows.
-        * ``to``§: ``Optional[str]``: Stop at a step with this id. Supported by sequential flows.
-        * ``skip``§: ``Iterable[str]``: Skip these steps. Supported by sequential flows.
+        * ``frm`` §: ``Optional[str]``: Start from a step with this ID. Supported by sequential flows.
+        * ``to`` §: ``Optional[str]``: Stop at a step with this id. Supported by sequential flows.
+        * ``skip`` §: ``Iterable[str]``: Skip these steps. Supported by sequential flows.
     * Sequential flow reproducible (if parameter ``sequential_flow_reproducible`` is ``True``)
-        * ``reproducible``§: ``str``: Create a reproducible for a step with is ID, aborting the flow afterwards. Supported by sequential flows.
+        * ``reproducible`` §: ``str``: Create a reproducible for a step with is ID, aborting the flow afterwards. Supported by sequential flows.
     * Flow run options (if parameter ``run_options`` is ``True``):
-        * ``tag``§: ``Optional[str]``
-        * ``last_run``§: ``bool``: If ``True``, ``tag`` is guaranteed to be None.
-        * ``with_initial_state``§: ``Optional[State]``
+        * ``tag`` §: ``Optional[str]``
+        * ``last_run`` §: ``bool``: If ``True``, ``tag`` is guaranteed to be None.
+        * ``with_initial_state`` §: ``Optional[State]``
     * PDK options
-        * ``use_volare``: ``bool``
-        * ``pdk_root``‡: ``Optional[str]``
-        * ``pdk``‡: ``str``
-        * ``scl``‡: ``Optional[str]``
+        * ``use_volare`` : ``bool``
+        * ``pdk_root`` ‡: ``Optional[str]``
+        * ``pdk`` ‡: ``str``
+        * ``scl`` ‡: ``Optional[str]``
     * ``config_files``: ``Iterable[str]``: Paths to configuration files (if
       parameter  ``accept_config_files`` is ``True``)
 

{librelane-3.0.0.dev38 → librelane-3.0.0.dev40}/librelane/flows/flow.py

@@ -534,8 +534,11 @@ class Flow(ABC):
 
         :param with_initial_state: An optional initial state object to use.
             If not provided:
+
             * If resuming a previous run, the latest ``state_out.json`` (by filesystem modification date)
+
             * If not, an empty state object is created.
+
         :param tag: A name for this invocation of the flow. If not provided,
             one based on a date string will be created.
 
@@ -913,9 +916,10 @@ class Flow(ABC):
                     # Despite the name, this is the Magic DRC report simply
                     # converted into a KLayout-compatible format. Confusing!
                     drc_xml_out = os.path.join(openlane_signoff_dir, "drc.klayout.xml")
-                    with open(drc_xml, encoding="utf8") as i, open(
-                        drc_xml_out, "w", encoding="utf8"
-                    ) as o:
+                    with (
+                        open(drc_xml, encoding="utf8") as i,
+                        open(drc_xml_out, "w", encoding="utf8") as o,
+                    ):
                         o.write(
                             "<!-- Despite the name, this is the Magic DRC report in KLayout format. -->\n"
                         )
@@ -999,8 +1003,9 @@ class Flow(ABC):
         A factory singleton for Flows, allowing Flow types to be registered and then
         retrieved by name.
 
-        See https://en.wikipedia.org/wiki/Factory_(object-oriented_programming) for
-        a primer.
+        See
+        `Factory (object-oriented programming) on Wikipedia <https://en.wikipedia.org/wiki/Factory_(object-oriented_programming)>`_
+        for a primer.
         """
 
         __registry: ClassVar[Dict[str, Type[Flow]]] = {}

{librelane-3.0.0.dev38 → librelane-3.0.0.dev40}/librelane/scripts/magic/drc.tcl

@@ -12,6 +12,13 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
+# Flatten cells
+if { [info exists ::env(MAGIC_GDS_FLATGLOB)] } {
+    foreach {gds_flatglob} $::env(MAGIC_GDS_FLATGLOB) {
+        gds flatglob $gds_flatglob
+    }
+}
+
 if { $::env(MAGIC_DRC_USE_GDS) } {
     gds read $::env(CURRENT_GDS)
 } else {

{librelane-3.0.0.dev38 → librelane-3.0.0.dev40}/librelane/scripts/openroad/common/io.tcl

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane
+#
 # Copyright 2022-2025 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -641,6 +645,13 @@ proc append_if_not_flag {list_arg glob_variable_name flag} {
     }
 }
 
+proc append_if_equals {list_arg glob_variable_name value flag} {
+    upvar $list_arg local_array
+    if { [info exists ::env($glob_variable_name)] && $::env($glob_variable_name) == $value } {
+        lappend local_array $flag
+    }
+}
+
 # Code below adapted from OpenROAD Flow Scripts under the following license:
 #
 # BSD 3-Clause License

{librelane-3.0.0.dev38 → librelane-3.0.0.dev40}/librelane/scripts/openroad/common/pdn_cfg.tcl

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane
+#
 # Copyright 2020-2022 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -12,6 +16,7 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
+source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
 source $::env(SCRIPTS_DIR)/openroad/common/set_global_connections.tcl
 set_global_connections
 
@@ -43,12 +48,24 @@ foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
 set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
     -secondary_power $secondary
 
+
+
 if { $::env(PDN_MULTILAYER) == 1 } {
+
+    set arg_list [list]
+    if { $::env(PDN_ENABLE_PINS) } {
+        lappend arg_list -pins "$::env(PDN_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)"
+    }
+
     define_pdn_grid \
         -name stdcell_grid \
         -starts_with POWER \
         -voltage_domain CORE \
-        -pins "$::env(PDN_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)"
+        {*}$arg_list
+
+    set arg_list [list]
+    append_if_equals arg_list PDN_EXTEND_TO "core_ring" -extend_to_core_ring
+    append_if_equals arg_list PDN_EXTEND_TO "boundary" -extend_to_boundary
 
     add_pdn_stripe \
         -grid stdcell_grid \
@@ -57,7 +74,8 @@ if { $::env(PDN_MULTILAYER) == 1 } {
         -pitch $::env(PDN_VPITCH) \
         -offset $::env(PDN_VOFFSET) \
         -spacing $::env(PDN_VSPACING) \
-        -starts_with POWER -extend_to_core_ring
+        -starts_with POWER \
+        {*}$arg_list
 
     add_pdn_stripe \
         -grid stdcell_grid \
@@ -66,17 +84,28 @@ if { $::env(PDN_MULTILAYER) == 1 } {
         -pitch $::env(PDN_HPITCH) \
         -offset $::env(PDN_HOFFSET) \
         -spacing $::env(PDN_HSPACING) \
-        -starts_with POWER -extend_to_core_ring
+        -starts_with POWER \
+        {*}$arg_list
 
     add_pdn_connect \
         -grid stdcell_grid \
         -layers "$::env(PDN_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)"
 } else {
+
+    set arg_list [list]
+    if { $::env(PDN_ENABLE_PINS) } {
+        lappend arg_list -pins "$::env(PDN_VERTICAL_LAYER)"
+    }
+
     define_pdn_grid \
         -name stdcell_grid \
         -starts_with POWER \
         -voltage_domain CORE \
-        -pins $::env(PDN_VERTICAL_LAYER)
+        {*}$arg_list
+
+    set arg_list [list]
+    append_if_equals arg_list PDN_EXTEND_TO "core_ring" -extend_to_core_ring
+    append_if_equals arg_list PDN_EXTEND_TO "boundary" -extend_to_boundary
 
     add_pdn_stripe \
         -grid stdcell_grid \
@@ -85,7 +114,8 @@ if { $::env(PDN_MULTILAYER) == 1 } {
         -pitch $::env(PDN_VPITCH) \
         -offset $::env(PDN_VOFFSET) \
         -spacing $::env(PDN_VSPACING) \
-        -starts_with POWER -extend_to_core_ring
+        -starts_with POWER \
+        {*}$arg_list
 }
 
 # Adds the standard cell rails if enabled.
@@ -105,21 +135,50 @@ if { $::env(PDN_ENABLE_RAILS) == 1 } {
 # Adds the core ring if enabled.
 if { $::env(PDN_CORE_RING) == 1 } {
     if { $::env(PDN_MULTILAYER) == 1 } {
+        set arg_list [list]
+        append_if_flag arg_list PDN_CORE_RING_ALLOW_OUT_OF_DIE -allow_out_of_die
+        append_if_flag arg_list PDN_CORE_RING_CONNECT_TO_PADS -connect_to_pads
+        append_if_equals arg_list PDN_EXTEND_TO "boundary" -extend_to_boundary
+
+        set pdn_core_vertical_layer $::env(PDN_VERTICAL_LAYER)
+        set pdn_core_horizontal_layer $::env(PDN_HORIZONTAL_LAYER)
+
+        if { [info exists ::env(PDN_CORE_VERTICAL_LAYER)] } {
+            set pdn_core_vertical_layer $::env(PDN_CORE_VERTICAL_LAYER)
+        }
+
+        if { [info exists ::env(PDN_CORE_HORIZONTAL_LAYER)] } {
+            set pdn_core_horizontal_layer $::env(PDN_CORE_HORIZONTAL_LAYER)
+        }
+
         add_pdn_ring \
-            -allow_out_of_die \
             -grid stdcell_grid \
-            -layers "$::env(PDN_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)" \
+            -layers "$pdn_core_vertical_layer $pdn_core_horizontal_layer" \
             -widths "$::env(PDN_CORE_RING_VWIDTH) $::env(PDN_CORE_RING_HWIDTH)" \
             -spacings "$::env(PDN_CORE_RING_VSPACING) $::env(PDN_CORE_RING_HSPACING)" \
-            -core_offset "$::env(PDN_CORE_RING_VOFFSET) $::env(PDN_CORE_RING_HOFFSET)"
+            -core_offset "$::env(PDN_CORE_RING_VOFFSET) $::env(PDN_CORE_RING_HOFFSET)" \
+            {*}$arg_list
+
+        if { [info exists ::env(PDN_CORE_VERTICAL_LAYER)] } {
+            add_pdn_connect \
+                -grid stdcell_grid \
+                -layers "$::env(PDN_CORE_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)"
+        }
+
+        if { [info exists ::env(PDN_CORE_HORIZONTAL_LAYER)] } {
+            add_pdn_connect \
+                -grid stdcell_grid \
+                -layers "$::env(PDN_CORE_HORIZONTAL_LAYER) $::env(PDN_VERTICAL_LAYER)"
+        }
+
+        if { [info exists ::env(PDN_CORE_VERTICAL_LAYER)] && [info exists ::env(PDN_CORE_HORIZONTAL_LAYER)] } {
+            add_pdn_connect \
+                -grid stdcell_grid \
+                -layers "$::env(PDN_CORE_VERTICAL_LAYER) $::env(PDN_CORE_HORIZONTAL_LAYER)"
+        }
+
     } else {
         throw APPLICATION "PDN_CORE_RING cannot be used when PDN_MULTILAYER is set to false."
-        # add_pdn_ring \
-        #     -grid stdcell_grid \
-        #     -layers "$::env(PDN_VERTICAL_LAYER)" \
-        #     -widths "$::env(PDN_CORE_RING_VWIDTH)" \
-        #     -spacings "$::env(PDN_CORE_RING_VSPACING)" \
-        #     -core_offset "$::env(PDN_CORE_RING_VOFFSET)"
     }
 }
 

{librelane-3.0.0.dev38 → librelane-3.0.0.dev40}/librelane/scripts/openroad/ioplacer.tcl

@@ -53,6 +53,12 @@ if { $::env(IO_PIN_PLACEMENT_MODE) == "annealing" } {
     lappend arg_list -annealing
 }
 
+if { [info exists ::env(IO_EXCLUDE_PIN_REGION)] } {
+    foreach exclude $::env(IO_EXCLUDE_PIN_REGION) {
+        lappend arg_list -exclude $exclude
+    }
+}
+
 set HMETAL $::env(FP_IO_HLAYER)
 set VMETAL $::env(FP_IO_VLAYER)
 

{librelane-3.0.0.dev38 → librelane-3.0.0.dev40}/librelane/scripts/openroad/sta/check_macro_instances.tcl

@@ -27,7 +27,7 @@ read_timing_info
 
 set error_count 0
 foreach {instance_name macro_name} $::env(_check_macro_instances) {
-    set instances [get_cells -hierarchical $instance_name]
+    set instances [get_cells $instance_name]
     set instance_count [llength $instances]
     if { $instance_count < 1 } {
         puts stderr "\[ERROR\] No macro instance $instance_name found."

{librelane-3.0.0.dev38 → librelane-3.0.0.dev40}/librelane/scripts/pyosys/synthesize.py

@@ -34,6 +34,7 @@
 import os
 import json
 import shutil
+from typing import List, Optional
 
 import click
 
@@ -142,11 +143,37 @@ def librelane_opt(
 
 
 def librelane_synth(
-    d, top, flatten, report_dir, *, booth=False, abc_dff=False, undriven=True
+    d,
+    top,
+    flatten,
+    report_dir,
+    *,
+    booth=False,
+    abc_dff=False,
+    undriven=True,
+    keep_hierarchy_min_cost: Optional[int],
+    keep_hierarchy_instances: List[str],
+    keep_hierarchy_modules: List[str],
 ):
+
     d.run_pass("hierarchy", "-check", "-top", top, "-nokeep_prints", "-nokeep_asserts")
     librelane_proc(d, report_dir)
 
+    if keep_hierarchy_min_cost:
+        d.run_pass("keep_hierarchy", "-min_cost", str(keep_hierarchy_min_cost))
+
+    if keep_hierarchy_instances:
+        for keep_hierarchy_instance in keep_hierarchy_instances:
+            d.run_pass(
+                "setattr", "-set", "keep_hierarchy", "1", keep_hierarchy_instance
+            )
+
+    if keep_hierarchy_modules:
+        for keep_hierarchy_module in keep_hierarchy_modules:
+            d.run_pass(
+                "setattr", "-mod", "-set", "keep_hierarchy", "1", keep_hierarchy_module
+            )
+
     if flatten:
         d.run_pass("flatten")  # Flatten the design hierarchy
 
@@ -294,12 +321,10 @@ def synthesize(
     )
     d.run_pass("rename", "-top", config["DESIGN_NAME"])
     d.run_pass("select", "-module", config["DESIGN_NAME"])
-    try:
+    if config["SYNTH_SHOW"]:
         d.run_pass(
             "show", "-format", "dot", "-prefix", os.path.join(step_dir, "hierarchy")
         )
-    except Exception:
-        pass
     if config["SYNTH_NORMALIZE_SINGLE_BIT_VECTORS"]:
         d.run_pass("attrmap", "-remove", "single_bit_vector")
     d.run_pass("select", "-clear")
@@ -356,12 +381,15 @@ def synthesize(
         booth=config["SYNTH_MUL_BOOTH"],
         abc_dff=config["SYNTH_ABC_DFF"],
         undriven=config.get("SYNTH_TIE_UNDEFINED") is not None,
+        keep_hierarchy_min_cost=config["SYNTH_KEEP_HIERARCHY_MIN_COST"],
+        keep_hierarchy_instances=config["SYNTH_KEEP_HIERARCHY_INSTANCES"],
+        keep_hierarchy_modules=config["SYNTH_KEEP_HIERARCHY_MODULES"],
     )
 
     d.run_pass("delete", "t:$print")
     d.run_pass("delete", "t:$assert")
 
-    try:
+    if config["SYNTH_SHOW"]:
         d.run_pass(
             "show",
             "-format",
@@ -369,8 +397,6 @@ def synthesize(
             "-prefix",
             os.path.join(step_dir, "primitive_techmap"),
         )
-    except Exception:
-        pass
 
     d.run_pass("opt")
     d.run_pass("opt_clean", "-purge")

{librelane-3.0.0.dev38 → librelane-3.0.0.dev40}/librelane/scripts/pyosys/ys_common.py

@@ -112,7 +112,14 @@ def _Design_add_blackbox_models(
 
         if ext in [".v", ".sv", ".vh"]:
             self.run_pass(
-                "read_verilog", "-sv", "-lib", *include_args, *define_args, model
+                "read_verilog",
+                "-sv",
+                "-setattr",
+                "keep_hierarchy",
+                "-lib",
+                *include_args,
+                *define_args,
+                model,
             )
         elif ext in [".lib"]:
             self.run_pass(
@@ -121,6 +128,8 @@ def _Design_add_blackbox_models(
                 "-ignore_miss_dir",
                 "-setattr",
                 "blackbox",
+                "-setattr",
+                "keep_hierarchy",
                 model,
             )
         else:

{librelane-3.0.0.dev38 → librelane-3.0.0.dev40}/librelane/steps/common_variables.py

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane
+#
 # Copyright 2023 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -12,7 +16,7 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 from decimal import Decimal
-from typing import Optional, List
+from typing import Optional, List, Literal
 
 from ..config import Variable
 
@@ -238,6 +242,20 @@ pdn_variables = [
         pdk=True,
         deprecated_names=["FP_PDN_CORE_RING_HOFFSET"],
     ),
+    Variable(
+        "PDN_CORE_RING_CONNECT_TO_PADS",
+        bool,
+        "If specified, the core side of the pad pins will be connected to the ring.",
+        default=False,
+        pdk=True,
+    ),
+    Variable(
+        "PDN_CORE_RING_ALLOW_OUT_OF_DIE",
+        bool,
+        "If specified, the ring shapes are allowed to be outside the die boundary.",
+        default=True,
+        pdk=True,
+    ),
     Variable(
         "PDN_RAIL_LAYER",
         str,
@@ -267,6 +285,32 @@ pdn_variables = [
         deprecated_names=["FP_PDN_VERTICAL_LAYER", "FP_PDN_LOWER_LAYER"],
         pdk=True,
     ),
+    Variable(
+        "PDN_CORE_HORIZONTAL_LAYER",
+        Optional[str],
+        "Defines the horizontal PDN layer for the core ring. Falls back to `PDN_HORIZONTAL_LAYER` if undefined.",
+        pdk=True,
+    ),
+    Variable(
+        "PDN_CORE_VERTICAL_LAYER",
+        Optional[str],
+        "Defines the vertical PDN layer for the core ring. Falls back to `PDN_VERTICAL_LAYER` if undefined.",
+        pdk=True,
+    ),
+    Variable(
+        "PDN_EXTEND_TO",
+        Literal["core_ring", "boundary"],
+        "Defines how far the stripes and rings extend.",
+        default="core_ring",
+        pdk=True,
+    ),
+    Variable(
+        "PDN_ENABLE_PINS",
+        bool,
+        "If specified, the power straps will be promoted to block pins.",
+        default=True,
+        pdk=True,
+    ),
 ]
 
 routing_layer_variables = [

{librelane-3.0.0.dev38 → librelane-3.0.0.dev40}/librelane/steps/magic.py

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane
+#
 # Copyright 2023 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -389,7 +393,7 @@ class DRC(MagicStep):
     name = "DRC"
     long_name = "Design Rule Checks"
 
-    inputs = [DesignFormat.DEF, DesignFormat.GDS]
+    inputs = [DesignFormat.DEF.mkOptional(), DesignFormat.GDS]
     outputs = []
 
     config_vars = MagicStep.config_vars + [
@@ -399,6 +403,11 @@ class DRC(MagicStep):
             "A flag to choose whether to run the Magic DRC checks on GDS or not. If not, then the checks will be done on the DEF view of the design, which is a bit faster, but may be less accurate as some DEF/LEF elements are abstract.",
             default=True,
         ),
+        Variable(
+            "MAGIC_GDS_FLATGLOB",
+            Optional[List[str]],
+            "Flatten cells by name pattern on input. May be used to avoid false positive DRC errors. The strings may use standard shell-type glob patterns, with * for any length string match, ? for any single character match, \\ for special characters, and [] for matching character sets or ranges.",
+        ),
     ]
 
     def get_script_path(self):
@@ -408,6 +417,10 @@ class DRC(MagicStep):
         reports_dir = os.path.join(self.step_dir, "reports")
         mkdirp(reports_dir)
 
+        # Check that the DEF exists if needed
+        if not self.config["MAGIC_DRC_USE_GDS"]:
+            assert state_in.get(DesignFormat.DEF)
+
         views_updates, metrics_updates = super().run(state_in, **kwargs)
 
         report_path = os.path.join(reports_dir, "drc_violations.magic.rpt")

{librelane-3.0.0.dev38 → librelane-3.0.0.dev40}/librelane/steps/openroad.py

@@ -1213,6 +1213,12 @@ class IOPlacement(OpenROADStep):
                 Optional[Path],
                 "Points to the DEF file to be used as a template.",
             ),
+            Variable(
+                "IO_EXCLUDE_PIN_REGION",
+                Optional[List[str]],
+                "List of regions where pins cannot be placed. The regions are strings in the format `{edge}:{interval}` where edge is `top|bottom|left|right` and the interval is either `*` to exclude the entire edge or `{begin}-{end}` to exclude a part of the edge, where `begin` and `end` are either absolute distance values or themselves `*` to denote the very start or end of an edge.",
+                units="µm",
+            ),
         ]
     )
 
@@ -2394,7 +2400,7 @@ class RepairDesignPostGPL(ResizerStep):
         Variable(
             "DESIGN_REPAIR_BUFFER_OUTPUT_PORTS",
             bool,
-            "Specifies whether or not to insert buffers on input ports when design repairs are run.",
+            "Specifies whether or not to insert buffers on output ports when design repairs are run.",
             default=True,
             deprecated_names=["PL_RESIZER_BUFFER_OUTPUT_PORTS"],
         ),