librelane 3.0.0.dev38__tar.gz → 3.0.0.dev39__tar.gz

{librelane-3.0.0.dev38 → librelane-3.0.0.dev39}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: librelane
-Version: 3.0.0.dev38
+Version: 3.0.0.dev39
 Summary: An infrastructure for implementing chip design flows
 Home-page: https://github.com/librelane/librelane
 License: Apache-2.0
@@ -20,7 +20,7 @@ Requires-Dist: cloup (>=3.0.5,<4)
 Requires-Dist: deprecated (>=1.2.10,<2)
 Requires-Dist: httpx (>=0.22.0,<0.29)
 Requires-Dist: klayout (>=0.29.0,<0.31.0)
-Requires-Dist: libparse (>=0.3.1,<1)
+Requires-Dist: lln-libparse (==0.56.*)
 Requires-Dist: lxml (>=4.9.0)
 Requires-Dist: psutil (>=5.9.0)
 Requires-Dist: pyyaml (>=5,<7)

{librelane-3.0.0.dev38 → librelane-3.0.0.dev39}/librelane/config/flow.py

@@ -107,13 +107,13 @@ pdk_variables = [
     Variable(
         "FP_IO_HLAYER",
         str,
-        "The metal layer on which to place horizontal IO pins, i.e., the top and bottom of the die.",
+        "The metal layer on which to place horizontally-aligned (long side parallel with the horizon) pins alongside the east and west edges of the die.",
         pdk=True,
     ),
     Variable(
         "FP_IO_VLAYER",
         str,
-        "The metal layer on which to place vertical IO pins, i.e., the top and bottom of the die.",
+        "The metal layer on which to place vertically-aligned (long side perpendicular to the horizon) pins alongside the north and south edges of the die.",
         pdk=True,
     ),
     Variable("RT_MIN_LAYER", str, "The lowest metal layer to route on.", pdk=True),

{librelane-3.0.0.dev38 → librelane-3.0.0.dev39}/librelane/flows/cli.py

@@ -218,27 +218,30 @@ def cloup_flow_opts(
     function decorated with @cloup.command (https://cloup.readthedocs.io/en/stable/autoapi/cloup/index.html#cloup.command).
 
     The following keyword arguments will be passed to the decorated function.
+
     * Those postfixed ‡ are compatible with the constructor for :class:`Flow`.
     * Those postfixed § are compatible with the :meth:`Flow.start`.
 
+    ---
+
     * Flow configuration options (if parameter ``config_options`` is ``True``):
         * ``flow_name``: ``Optional[str]``: A valid flow ID to be used with :meth:`Flow.factory.get`
-        * ``config_override_strings``‡: ``Optional[Iterable[str]]``
+        * ``config_override_strings`` ‡: ``Optional[Iterable[str]]``
     * Sequential flow controls (if parameter ``sequential_flow_controls`` is ``True``)
-        * ``frm``§: ``Optional[str]``: Start from a step with this ID. Supported by sequential flows.
-        * ``to``§: ``Optional[str]``: Stop at a step with this id. Supported by sequential flows.
-        * ``skip``§: ``Iterable[str]``: Skip these steps. Supported by sequential flows.
+        * ``frm`` §: ``Optional[str]``: Start from a step with this ID. Supported by sequential flows.
+        * ``to`` §: ``Optional[str]``: Stop at a step with this id. Supported by sequential flows.
+        * ``skip`` §: ``Iterable[str]``: Skip these steps. Supported by sequential flows.
     * Sequential flow reproducible (if parameter ``sequential_flow_reproducible`` is ``True``)
-        * ``reproducible``§: ``str``: Create a reproducible for a step with is ID, aborting the flow afterwards. Supported by sequential flows.
+        * ``reproducible`` §: ``str``: Create a reproducible for a step with is ID, aborting the flow afterwards. Supported by sequential flows.
     * Flow run options (if parameter ``run_options`` is ``True``):
-        * ``tag``§: ``Optional[str]``
-        * ``last_run``§: ``bool``: If ``True``, ``tag`` is guaranteed to be None.
-        * ``with_initial_state``§: ``Optional[State]``
+        * ``tag`` §: ``Optional[str]``
+        * ``last_run`` §: ``bool``: If ``True``, ``tag`` is guaranteed to be None.
+        * ``with_initial_state`` §: ``Optional[State]``
     * PDK options
-        * ``use_volare``: ``bool``
-        * ``pdk_root``‡: ``Optional[str]``
-        * ``pdk``‡: ``str``
-        * ``scl``‡: ``Optional[str]``
+        * ``use_volare`` : ``bool``
+        * ``pdk_root`` ‡: ``Optional[str]``
+        * ``pdk`` ‡: ``str``
+        * ``scl`` ‡: ``Optional[str]``
     * ``config_files``: ``Iterable[str]``: Paths to configuration files (if
       parameter  ``accept_config_files`` is ``True``)
 

{librelane-3.0.0.dev38 → librelane-3.0.0.dev39}/librelane/flows/flow.py

@@ -534,8 +534,11 @@ class Flow(ABC):
 
         :param with_initial_state: An optional initial state object to use.
             If not provided:
+
             * If resuming a previous run, the latest ``state_out.json`` (by filesystem modification date)
+
             * If not, an empty state object is created.
+
         :param tag: A name for this invocation of the flow. If not provided,
             one based on a date string will be created.
 
@@ -999,8 +1002,9 @@ class Flow(ABC):
         A factory singleton for Flows, allowing Flow types to be registered and then
         retrieved by name.
 
-        See https://en.wikipedia.org/wiki/Factory_(object-oriented_programming) for
-        a primer.
+        See
+        `Factory (object-oriented programming) on Wikipedia <https://en.wikipedia.org/wiki/Factory_(object-oriented_programming)>`_
+        for a primer.
         """
 
         __registry: ClassVar[Dict[str, Type[Flow]]] = {}

{librelane-3.0.0.dev38 → librelane-3.0.0.dev39}/librelane/scripts/openroad/common/io.tcl

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane
+#
 # Copyright 2022-2025 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -641,6 +645,13 @@ proc append_if_not_flag {list_arg glob_variable_name flag} {
     }
 }
 
+proc append_if_equals {list_arg glob_variable_name value flag} {
+    upvar $list_arg local_array
+    if { [info exists ::env($glob_variable_name)] && $::env($glob_variable_name) == $value } {
+        lappend local_array $flag
+    }
+}
+
 # Code below adapted from OpenROAD Flow Scripts under the following license:
 #
 # BSD 3-Clause License

{librelane-3.0.0.dev38 → librelane-3.0.0.dev39}/librelane/scripts/openroad/common/pdn_cfg.tcl

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane
+#
 # Copyright 2020-2022 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -12,6 +16,7 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
+source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
 source $::env(SCRIPTS_DIR)/openroad/common/set_global_connections.tcl
 set_global_connections
 
@@ -43,12 +48,24 @@ foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
 set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
     -secondary_power $secondary
 
+
+
 if { $::env(PDN_MULTILAYER) == 1 } {
+
+    set arg_list [list]
+    if { $::env(PDN_ENABLE_PINS) } {
+        lappend arg_list -pins "$::env(PDN_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)"
+    }
+
     define_pdn_grid \
         -name stdcell_grid \
         -starts_with POWER \
         -voltage_domain CORE \
-        -pins "$::env(PDN_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)"
+        {*}$arg_list
+
+    set arg_list [list]
+    append_if_equals arg_list PDN_EXTEND_TO "core_ring" -extend_to_core_ring
+    append_if_equals arg_list PDN_EXTEND_TO "boundary" -extend_to_boundary
 
     add_pdn_stripe \
         -grid stdcell_grid \
@@ -57,7 +74,8 @@ if { $::env(PDN_MULTILAYER) == 1 } {
         -pitch $::env(PDN_VPITCH) \
         -offset $::env(PDN_VOFFSET) \
         -spacing $::env(PDN_VSPACING) \
-        -starts_with POWER -extend_to_core_ring
+        -starts_with POWER \
+        {*}$arg_list
 
     add_pdn_stripe \
         -grid stdcell_grid \
@@ -66,17 +84,28 @@ if { $::env(PDN_MULTILAYER) == 1 } {
         -pitch $::env(PDN_HPITCH) \
         -offset $::env(PDN_HOFFSET) \
         -spacing $::env(PDN_HSPACING) \
-        -starts_with POWER -extend_to_core_ring
+        -starts_with POWER \
+        {*}$arg_list
 
     add_pdn_connect \
         -grid stdcell_grid \
         -layers "$::env(PDN_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)"
 } else {
+
+    set arg_list [list]
+    if { $::env(PDN_ENABLE_PINS) } {
+        lappend arg_list -pins "$::env(PDN_VERTICAL_LAYER)"
+    }
+
     define_pdn_grid \
         -name stdcell_grid \
         -starts_with POWER \
         -voltage_domain CORE \
-        -pins $::env(PDN_VERTICAL_LAYER)
+        {*}$arg_list
+
+    set arg_list [list]
+    append_if_equals arg_list PDN_EXTEND_TO "core_ring" -extend_to_core_ring
+    append_if_equals arg_list PDN_EXTEND_TO "boundary" -extend_to_boundary
 
     add_pdn_stripe \
         -grid stdcell_grid \
@@ -85,7 +114,8 @@ if { $::env(PDN_MULTILAYER) == 1 } {
         -pitch $::env(PDN_VPITCH) \
         -offset $::env(PDN_VOFFSET) \
         -spacing $::env(PDN_VSPACING) \
-        -starts_with POWER -extend_to_core_ring
+        -starts_with POWER \
+        {*}$arg_list
 }
 
 # Adds the standard cell rails if enabled.
@@ -105,21 +135,50 @@ if { $::env(PDN_ENABLE_RAILS) == 1 } {
 # Adds the core ring if enabled.
 if { $::env(PDN_CORE_RING) == 1 } {
     if { $::env(PDN_MULTILAYER) == 1 } {
+        set arg_list [list]
+        append_if_flag arg_list PDN_CORE_RING_ALLOW_OUT_OF_DIE -allow_out_of_die
+        append_if_flag arg_list PDN_CORE_RING_CONNECT_TO_PADS -connect_to_pads
+        append_if_equals arg_list PDN_EXTEND_TO "boundary" -extend_to_boundary
+
+        set pdn_core_vertical_layer $::env(PDN_VERTICAL_LAYER)
+        set pdn_core_horizontal_layer $::env(PDN_HORIZONTAL_LAYER)
+
+        if { [info exists ::env(PDN_CORE_VERTICAL_LAYER)] } {
+            set pdn_core_vertical_layer $::env(PDN_CORE_VERTICAL_LAYER)
+        }
+
+        if { [info exists ::env(PDN_CORE_HORIZONTAL_LAYER)] } {
+            set pdn_core_horizontal_layer $::env(PDN_CORE_HORIZONTAL_LAYER)
+        }
+
         add_pdn_ring \
-            -allow_out_of_die \
             -grid stdcell_grid \
-            -layers "$::env(PDN_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)" \
+            -layers "$pdn_core_vertical_layer $pdn_core_horizontal_layer" \
             -widths "$::env(PDN_CORE_RING_VWIDTH) $::env(PDN_CORE_RING_HWIDTH)" \
             -spacings "$::env(PDN_CORE_RING_VSPACING) $::env(PDN_CORE_RING_HSPACING)" \
-            -core_offset "$::env(PDN_CORE_RING_VOFFSET) $::env(PDN_CORE_RING_HOFFSET)"
+            -core_offset "$::env(PDN_CORE_RING_VOFFSET) $::env(PDN_CORE_RING_HOFFSET)" \
+            {*}$arg_list
+
+        if { [info exists ::env(PDN_CORE_VERTICAL_LAYER)] } {
+            add_pdn_connect \
+                -grid stdcell_grid \
+                -layers "$::env(PDN_CORE_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)"
+        }
+
+        if { [info exists ::env(PDN_CORE_HORIZONTAL_LAYER)] } {
+            add_pdn_connect \
+                -grid stdcell_grid \
+                -layers "$::env(PDN_CORE_HORIZONTAL_LAYER) $::env(PDN_VERTICAL_LAYER)"
+        }
+
+        if { [info exists ::env(PDN_CORE_VERTICAL_LAYER)] && [info exists ::env(PDN_CORE_HORIZONTAL_LAYER)] } {
+            add_pdn_connect \
+                -grid stdcell_grid \
+                -layers "$::env(PDN_CORE_VERTICAL_LAYER) $::env(PDN_CORE_HORIZONTAL_LAYER)"
+        }
+
     } else {
         throw APPLICATION "PDN_CORE_RING cannot be used when PDN_MULTILAYER is set to false."
-        # add_pdn_ring \
-        #     -grid stdcell_grid \
-        #     -layers "$::env(PDN_VERTICAL_LAYER)" \
-        #     -widths "$::env(PDN_CORE_RING_VWIDTH)" \
-        #     -spacings "$::env(PDN_CORE_RING_VSPACING)" \
-        #     -core_offset "$::env(PDN_CORE_RING_VOFFSET)"
     }
 }
 

{librelane-3.0.0.dev38 → librelane-3.0.0.dev39}/librelane/steps/common_variables.py

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane
+#
 # Copyright 2023 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -12,7 +16,7 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 from decimal import Decimal
-from typing import Optional, List
+from typing import Optional, List, Literal
 
 from ..config import Variable
 
@@ -238,6 +242,20 @@ pdn_variables = [
         pdk=True,
         deprecated_names=["FP_PDN_CORE_RING_HOFFSET"],
     ),
+    Variable(
+        "PDN_CORE_RING_CONNECT_TO_PADS",
+        bool,
+        "If specified, the core side of the pad pins will be connected to the ring.",
+        default=False,
+        pdk=True,
+    ),
+    Variable(
+        "PDN_CORE_RING_ALLOW_OUT_OF_DIE",
+        bool,
+        "If specified, the ring shapes are allowed to be outside the die boundary.",
+        default=True,
+        pdk=True,
+    ),
     Variable(
         "PDN_RAIL_LAYER",
         str,
@@ -267,6 +285,32 @@ pdn_variables = [
         deprecated_names=["FP_PDN_VERTICAL_LAYER", "FP_PDN_LOWER_LAYER"],
         pdk=True,
     ),
+    Variable(
+        "PDN_CORE_HORIZONTAL_LAYER",
+        Optional[str],
+        "Defines the horizontal PDN layer for the core ring. Falls back to `PDN_HORIZONTAL_LAYER` if undefined.",
+        pdk=True,
+    ),
+    Variable(
+        "PDN_CORE_VERTICAL_LAYER",
+        Optional[str],
+        "Defines the vertical PDN layer for the core ring. Falls back to `PDN_VERTICAL_LAYER` if undefined.",
+        pdk=True,
+    ),
+    Variable(
+        "PDN_EXTEND_TO",
+        Literal["core_ring", "boundary"],
+        "Defines how far the stripes and rings extend.",
+        default="core_ring",
+        pdk=True,
+    ),
+    Variable(
+        "PDN_ENABLE_PINS",
+        bool,
+        "If specified, the power straps will be promoted to block pins.",
+        default=True,
+        pdk=True,
+    ),
 ]
 
 routing_layer_variables = [

{librelane-3.0.0.dev38 → librelane-3.0.0.dev39}/librelane/steps/openroad.py

@@ -2394,7 +2394,7 @@ class RepairDesignPostGPL(ResizerStep):
         Variable(
             "DESIGN_REPAIR_BUFFER_OUTPUT_PORTS",
             bool,
-            "Specifies whether or not to insert buffers on input ports when design repairs are run.",
+            "Specifies whether or not to insert buffers on output ports when design repairs are run.",
             default=True,
             deprecated_names=["PL_RESIZER_BUFFER_OUTPUT_PORTS"],
         ),

{librelane-3.0.0.dev38 → librelane-3.0.0.dev39}/librelane/steps/step.py

@@ -1437,7 +1437,8 @@ class Step(ABC):
         A factory singleton for Steps, allowing steps types to be registered and then
         retrieved by name.
 
-        See https://en.wikipedia.org/wiki/Factory_(object-oriented_programming) for
+        See
+        `Factory (object-oriented programming) on Wikipedia <https://en.wikipedia.org/wiki/Factory_(object-oriented_programming)>`_
         a primer.
         """
 

{librelane-3.0.0.dev38 → librelane-3.0.0.dev39}/pyproject.toml

@@ -1,6 +1,6 @@
 [tool.poetry]
 name = "librelane"
-version = "3.0.0.dev38"
+version = "3.0.0.dev39"
 description = "An infrastructure for implementing chip design flows"
 # Technically, maintainer. We cannot use the maintainers field until
 # poetry-core>=2.0.0 which requires Python version 3.9+. This field does
@@ -21,7 +21,7 @@ rich = ">=12,<15"
 ciel = ">=2.0.3,<3"
 lxml = ">=4.9.0"
 deprecated = ">=1.2.10,<2"
-libparse = ">=0.3.1,<1"
+lln-libparse = "0.56.*"
 psutil = ">=5.9.0"
 httpx = ">=0.22.0,<0.29"
 klayout = ">=0.29.0,<0.31.0"