librelane 3.0.0.dev32__tar.gz → 3.0.0.dev33__tar.gz

{librelane-3.0.0.dev32 → librelane-3.0.0.dev33}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: librelane
-Version: 3.0.0.dev32
+Version: 3.0.0.dev33
 Summary: An infrastructure for implementing chip design flows
 Home-page: https://github.com/librelane/librelane
 License: Apache-2.0

{librelane-3.0.0.dev32 → librelane-3.0.0.dev33}/librelane/scripts/pyosys/json_header.py

@@ -63,6 +63,7 @@ def json_header(
         includes=includes,
         defines=defines,
         use_slang=config["USE_SLANG"],
+        slang_arguments=config["SLANG_ARGUMENTS"] or [],
     )
     d.run_pass(
         "hierarchy",

{librelane-3.0.0.dev32 → librelane-3.0.0.dev33}/librelane/scripts/pyosys/synthesize.py

@@ -263,6 +263,7 @@ def synthesize(
             includes=includes,
             defines=defines,
             use_slang=False,
+            slang_arguments=[],
         )
     elif verilog_files := config.get("VERILOG_FILES"):
         d.read_verilog_files(
@@ -272,6 +273,7 @@ def synthesize(
             includes=includes,
             defines=defines,
             use_slang=config["USE_SLANG"],
+            slang_arguments=config["SLANG_ARGUMENTS"] or [],
         )
     elif vhdl_files := config.get("VHDL_FILES"):
         d.run_pass("plugin", "-i", "ghdl")

{librelane-3.0.0.dev32 → librelane-3.0.0.dev33}/librelane/scripts/pyosys/ys_common.py

@@ -51,6 +51,7 @@ def _Design_read_verilog_files(
     includes: Iterable[str],
     defines: Iterable[str],
     use_slang: bool = False,
+    slang_arguments: Iterable[str],
 ):
     files = list(files)  # for easier concatenation
     include_args = [f"-I{dir}" for dir in includes]
@@ -72,6 +73,7 @@ def _Design_read_verilog_files(
             *define_args,
             *include_args,
             *slang_chparam_args,
+            *slang_arguments,
             *files,
         )
     else:

{librelane-3.0.0.dev32 → librelane-3.0.0.dev33}/librelane/steps/pyosys.py

@@ -128,6 +128,11 @@ verilog_rtl_cfg_vars = [
         default=False,
         deprecated_names=["USE_SYNLIG"],
     ),
+    Variable(
+        "SLANG_ARGUMENTS",
+        Optional[List[str]],
+        "Pass arguments to the Slang frontend.",
+    ),
 ]
 
 DesignFormat(
@@ -439,7 +444,7 @@ class SynthesisCommon(VerilogStep):
         Variable(
             "SYNTH_HIERARCHY_MODE",
             Literal["flatten", "deferred_flatten", "keep"],
-            "Affects how hierarchy is maintained throughout and after synthesis. 'flatten' flattens it during and after synthesis. 'deferred_flatten' flattens it after synthesis. 'keep' never flattens it.",
+            "Affects how hierarchy is maintained throughout and after synthesis. 'flatten' flattens it during and after synthesis. 'deferred_flatten' flattens it after synthesis. 'keep' never flattens it. Please note that when using the Slang plugin, you need to pass '--keep-hierarchy' to `SLANG_ARGUMENTS` separately.",
             default="flatten",
             deprecated_names=[
                 (

{librelane-3.0.0.dev32 → librelane-3.0.0.dev33}/pyproject.toml

@@ -1,6 +1,6 @@
 [tool.poetry]
 name = "librelane"
-version = "3.0.0.dev32"
+version = "3.0.0.dev33"
 description = "An infrastructure for implementing chip design flows"
 # Technically, maintainer. We cannot use the maintainers field until
 # poetry-core>=2.0.0 which requires Python version 3.9+. This field does