librelane 3.0.0.dev26__tar.gz → 3.0.0.dev28__tar.gz

{librelane-3.0.0.dev26 → librelane-3.0.0.dev28}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: librelane
-Version: 3.0.0.dev26
+Version: 3.0.0.dev28
 Summary: An infrastructure for implementing chip design flows
 Home-page: https://github.com/librelane/librelane
 License: Apache-2.0

{librelane-3.0.0.dev26 → librelane-3.0.0.dev28}/librelane/common/__init__.py

@@ -32,7 +32,7 @@ from .misc import (
     idem,
     get_librelane_root,
     get_script_dir,
-    get_opdks_rev,
+    get_pdk_hash,
     slugify,
     protected,
     final,

{librelane-3.0.0.dev26 → librelane-3.0.0.dev28}/librelane/common/metrics/__main__.py

@@ -158,7 +158,8 @@ def _compare_metric_folders(
                 continue
             basename = basename[: -len(".metrics.json")]
 
-            parts = basename.split("-", maxsplit=2)
+            # We have to rsplit, since ihp-sg13g2 contains a "-"
+            parts = basename.rsplit("-", maxsplit=2)
             if len(parts) != 3:
                 raise ValueError(
                     f"Invalid filename {basename}: not in the format {{pdk}}-{{scl}}-{{design_name}}"

{librelane-3.0.0.dev26 → librelane-3.0.0.dev28}/librelane/common/misc.py

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane
+#
 # Copyright 2023 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -16,6 +20,7 @@ import os
 import re
 import glob
 import gzip
+import yaml
 import typing
 import pathlib
 import fnmatch
@@ -37,6 +42,7 @@ import httpx
 
 from ..__version__ import __version__
 from .types import AnyPath, Path
+from ..logging import err
 
 T = TypeVar("T")
 
@@ -68,15 +74,21 @@ def get_script_dir() -> str:
     )
 
 
-def get_opdks_rev() -> str:
+def get_pdk_hash(pdk_variant) -> str:
     """
-    Gets the Open_PDKs revision confirmed compatible with this version of LibreLane.
+    Gets the PDK version hash confirmed compatible with this version of LibreLane.
     """
-    return (
-        open(os.path.join(get_librelane_root(), "open_pdks_rev"), encoding="utf8")
-        .read()
-        .strip()
+
+    with open(os.path.join(get_librelane_root(), "pdk_hashes.yaml"), "r") as file:
+        pdk_hashes = yaml.safe_load(file)
+        for pdk_family in pdk_hashes:
+            if pdk_family in pdk_variant:
+                return pdk_hashes[pdk_family]
+
+    err(
+        f"Could not find a PDK family for '{pdk_variant}'. Please specify a PDK manually with '--manual-pdk'."
     )
+    exit(1)
 
 
 # The following code snippet has been adapted under the following license:

{librelane-3.0.0.dev26 → librelane-3.0.0.dev28}/librelane/common/tcl.py

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane
+#
 # Copyright 2023 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -68,12 +72,50 @@ class TclUtils(object):
                 if value is not None:
                     env_out[match.group(1)] = value
 
+        def py_dict(command, target=None, *args):
+            if command == "set":
+                if match := _env_rx.fullmatch(target):
+
+                    if len(args) > 1:
+                        value = args[-1]
+                        keys = args[:-1]
+
+                        # Create new dict if it does not exist
+                        if not match.group(1) in env_out:
+                            env_out[match.group(1)] = {}
+
+                        # set ::env(...) [dict create]
+                        # will create an empty string ""
+                        # convert into an empty dictionary
+                        if env_out[match.group(1)] == "":
+                            env_out[match.group(1)] = {}
+
+                        # Set key value pair
+                        cur_dict = env_out[match.group(1)]
+
+                        # Create all nested dicts
+                        for key in keys[:-1]:
+                            if key in cur_dict:
+                                cur_dict = cur_dict[key]
+                            else:
+                                cur_dict[key] = {}
+                                cur_dict = cur_dict[key]
+
+                        # Finally set the value
+                        cur_dict[keys[-1]] = value
+
         py_set_name = interpreter.register(py_set)
+        py_dict_name = interpreter.register(py_dict)
         interpreter.call("rename", py_set_name, "_py_set")
         interpreter.call("rename", "set", "_orig_set")
+        interpreter.call("rename", py_dict_name, "_py_dict")
+        interpreter.call("rename", "dict", "_orig_dict")
         interpreter.eval(
             "proc set args { _py_set {*}$args; tailcall _orig_set {*}$args; }"
         )
+        interpreter.eval(
+            "proc dict args { _py_dict {*}$args; tailcall _orig_dict {*}$args; }"
+        )
 
         interpreter.eval(tcl_in)
 

{librelane-3.0.0.dev26 → librelane-3.0.0.dev28}/librelane/config/flow.py

@@ -195,6 +195,13 @@ scl_variables = [
         "Path(s) to cells' SPICE model(s)",
         pdk=True,
     ),
+    Variable(
+        "CELL_CDLS",
+        Optional[List[Path]],
+        description="A circuit-design language view of the standard cell library.",
+        pdk=True,
+        deprecated_names=["STD_CELL_LIBRARY_CDL"],
+    ),
     Variable(
         "SYNTH_EXCLUDED_CELL_FILE",
         Path,
@@ -424,6 +431,11 @@ option_variables = [
         Optional[List[Path]],
         "Specifies miscellaneous SPICE models to be loaded indiscriminately whenever SPICE models are loaded.",
     ),
+    Variable(
+        "EXTRA_CDLS",
+        Optional[List[Path]],
+        "Specifies miscellaneous CDL netlists to be loaded indiscriminately whenever CDL netlists are loaded.",
+    ),
     Variable(
         "EXTRA_LIBS",
         Optional[List[Path]],

{librelane-3.0.0.dev26 → librelane-3.0.0.dev28}/librelane/flows/cli.py

@@ -34,7 +34,7 @@ from cloup.constraints import (
 from cloup.typing import Decorator
 
 from .flow import Flow
-from ..common import set_tpe, cli, get_opdks_rev, _get_process_limit
+from ..common import set_tpe, cli, get_pdk_hash, _get_process_limit
 from ..logging import set_log_level, verbose, err, options, LogLevels
 from ..state import State, InvalidState
 
@@ -421,7 +421,7 @@ def cloup_flow_opts(
                     import ciel
                     from ciel.source import StaticWebDataSource
 
-                    opdks_rev = volare_pdk_override or get_opdks_rev()
+                    opdks_rev = volare_pdk_override or get_pdk_hash(pdk)
                     ciel_home = ciel.get_ciel_home(pdk_root)
 
                     include_libraries = ["default"]

librelane-3.0.0.dev28/librelane/pdk_hashes.yaml

@@ -0,0 +1,3 @@
+sky130: 8afc8346a57fe1ab7934ba5a6056ea8b43078e71
+gf180mcu: 8afc8346a57fe1ab7934ba5a6056ea8b43078e71
+ihp-sg13g2: cb7daaa8901016cf7c5d272dfa322c41f024931f

{librelane-3.0.0.dev26 → librelane-3.0.0.dev28}/librelane/scripts/klayout/stream_out.py

@@ -90,6 +90,13 @@ import click
     "input",
     type=click.Path(exists=True, file_okay=True, dir_okay=False),
 )
+@click.option(
+    "--conflict-resolution",
+    "conflict_resolution",
+    type=str,
+    default="RenameCell",
+    help="Cell conflict resolution handling.",
+)
 def stream_out(
     output: str,
     input_lefs: Tuple[str, ...],
@@ -100,6 +107,7 @@ def stream_out(
     seal_gds: Optional[str],
     design_name: str,
     input: str,
+    conflict_resolution: str,
 ):  # Load technology file
     try:
         tech = pya.Technology()
@@ -109,6 +117,22 @@ def stream_out(
         layout_options.lefdef_config.lef_files = list(input_lefs)
         layout_options.lefdef_config.map_file = lym
 
+        cell_conflict_resolution = {
+            "AddToCell": pya.LoadLayoutOptions.CellConflictResolution.AddToCell,
+            "OverwriteCell": pya.LoadLayoutOptions.CellConflictResolution.OverwriteCell,
+            "RenameCell": pya.LoadLayoutOptions.CellConflictResolution.RenameCell,
+            "SkipNewCell": pya.LoadLayoutOptions.CellConflictResolution.SkipNewCell,
+        }.get(conflict_resolution)
+
+        if cell_conflict_resolution is None:
+            print(
+                f"[ERROR] Unknown conflict resolution: '{conflict_resolution}'.",
+                file=sys.stderr,
+            )
+            exit(1)
+        else:
+            layout_options.cell_conflict_resolution = cell_conflict_resolution
+
         # Load def file
         main_layout = pya.Layout()
         # main_layout.load_layer_props(props_file)
@@ -126,7 +150,7 @@ def stream_out(
         # Load in the gds to merge
         print("[INFO] Merging GDS files…")
         for gds in input_gds_files:
-            main_layout.read(gds)
+            main_layout.read(gds, layout_options)
 
         # Copy the top level only to a new layout
         print(f"[INFO] Copying top level cell '{design_name}'…")
@@ -138,7 +162,7 @@ def stream_out(
         print("[INFO] Checking for missing GDS…")
         missing_gds = False
         for i in top_only_layout.each_cell():
-            if i.is_empty():
+            if i.is_ghost_cell():
                 missing_gds = True
                 print(
                     f"[ERROR] LEF Cell '{i.name}' has no matching GDS cell.",

{librelane-3.0.0.dev26 → librelane-3.0.0.dev28}/librelane/scripts/magic/extract_spice.tcl

@@ -12,7 +12,7 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 set f [open $::env(STEP_DIR)/cif_scale.txt "w"]
-puts $f "[magic::i2u 1]"
+puts $f [expr {((round([magic::cif scale output] * 10000)) / 10000.0) * 1}]
 close $f
 
 if { $::env(MAGIC_EXT_USE_GDS) } {

librelane-3.0.0.dev28/librelane/scripts/openroad/write_cdl.tcl

@@ -0,0 +1,23 @@
+#
+# Write CDL netlist of the current design
+#
+
+# Load design database
+source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
+read_current_odb
+
+# Collect masters CDL
+set masters {}
+
+foreach cdl $::env(CELL_CDLS) {
+    lappend masters $cdl
+}
+
+if { [info exist ::env(EXTRA_CDLS)] } {
+    foreach cdl $::env(EXTRA_CDLS) {
+        lappend masters $cdl
+    }
+}
+
+# Write only the CDL
+write_cdl -include_fillers -masters "$masters" $::env(STEP_DIR)/$::env(DESIGN_NAME).cdl

{librelane-3.0.0.dev26 → librelane-3.0.0.dev28}/librelane/scripts/pyosys/json_header.py

@@ -38,7 +38,7 @@ def json_header(
     defines = (
         (config["VERILOG_DEFINES"] or [])
         + [
-            f"PDK_{config['PDK']}",
+            f"PDK_{config['PDK'].replace('-','_')}",
             f"SCL_{config['STD_CELL_LIBRARY']}",
             "__librelane__",
             "__pnr__",

{librelane-3.0.0.dev26 → librelane-3.0.0.dev28}/librelane/scripts/pyosys/synthesize.py

@@ -227,7 +227,7 @@ def synthesize(
 
     includes = config.get("VERILOG_INCLUDE_DIRS") or []
     defines = (config.get("VERILOG_DEFINES") or []) + [
-        f"PDK_{config['PDK']}",
+        f"PDK_{config['PDK'].replace('-','_')}",
         f"SCL_{config['STD_CELL_LIBRARY']}",
         "__librelane__",
         "__pnr__",

{librelane-3.0.0.dev26 → librelane-3.0.0.dev28}/librelane/state/design_format.py

@@ -239,6 +239,13 @@ DesignFormat(
     alts=["SPICE"],
 ).register()
 
+DesignFormat(
+    "cdl",
+    "cdl",
+    "Circuit Design Language",
+    alts=["CDL"],
+).register()
+
 DesignFormat(
     "gds",
     "gds",

{librelane-3.0.0.dev26 → librelane-3.0.0.dev28}/librelane/steps/cvc_rv.py

@@ -16,7 +16,7 @@ import re
 import json
 from enum import Enum
 from io import StringIO, TextIOWrapper
-from typing import List, Optional, Tuple
+from typing import Optional, Tuple
 
 from .step import StepException, ViewsUpdate, MetricsUpdate, Step
 from ..common import Path
@@ -124,13 +124,6 @@ class ERC(Step):
             description="",
             pdk=True,
         ),
-        Variable(
-            "CELL_CDLS",
-            List[Path],
-            description="A circuit-design language view of the standard cell library.",
-            pdk=True,
-            deprecated_names=["STD_CELL_LIBRARY_CDL"],
-        ),
     ]
 
     def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:

{librelane-3.0.0.dev26 → librelane-3.0.0.dev28}/librelane/steps/klayout.py

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane
+#
 # Copyright 2023 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -19,7 +23,8 @@ import shutil
 import subprocess
 from os.path import abspath
 from base64 import b64encode
-from typing import Any, Dict, Optional, List, Sequence, Tuple, Union
+from tempfile import NamedTemporaryFile
+from typing import Any, Dict, Optional, List, Literal, Sequence, Tuple, Union
 
 from .step import ViewsUpdate, MetricsUpdate, Step, StepError, StepException
 
@@ -196,6 +201,17 @@ class StreamOut(KLayoutStep):
     inputs = [DesignFormat.DEF]
     outputs = [DesignFormat.GDS, DesignFormat.KLAYOUT_GDS]
 
+    config_vars = KLayoutStep.config_vars + [
+        Variable(
+            "KLAYOUT_CONFLICT_RESOLUTION",
+            Optional[
+                Literal["AddToCell", "OverwriteCell", "RenameCell", "SkipNewCell"]
+            ],
+            "Specifies the conflict resolution if a cell name conflict arises.",
+            default="RenameCell",
+        ),
+    ]
+
     def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
         views_updates: ViewsUpdate = {}
 
@@ -218,6 +234,8 @@ class StreamOut(KLayoutStep):
                 abspath(klayout_gds_out),
                 "--top",
                 self.config["DESIGN_NAME"],
+                "--conflict-resolution",
+                self.config["KLAYOUT_CONFLICT_RESOLUTION"],
             ]
             + self.get_cli_args(include_lefs=True, include_gds=True),
             env=env,
@@ -431,10 +449,77 @@ class DRC(KLayoutStep):
         )
         return subprocess_result["generated_metrics"]
 
+    def run_ihp_sg13g2(self, state_in: State, **kwargs) -> MetricsUpdate:
+        kwargs, env = self.extract_env(kwargs)
+
+        drc_script_path = self.config["KLAYOUT_DRC_RUNSET"]
+
+        reports_dir = os.path.join(self.step_dir, "reports")
+        mkdirp(reports_dir)
+        xml_report = os.path.join(reports_dir, "drc_violations.klayout.xml")
+        json_report = os.path.join(reports_dir, "drc_violations.klayout.json")
+
+        input_view = state_in[DesignFormat.GDS]
+        assert isinstance(input_view, Path)
+
+        opts = []
+        for k, v in self.config["KLAYOUT_DRC_OPTIONS"].items():
+            opts.extend(
+                [
+                    "-rd",
+                    f"{k}={v}",
+                ]
+            )
+
+        threads = self.config["KLAYOUT_DRC_THREADS"] or str(_get_process_limit())
+        if threads != "1":
+            opts.extend(
+                [
+                    "-rd",
+                    f"threads={threads}",
+                ]
+            )
+
+        info(f"Running KLayout DRC with {threads} threads…")
+
+        # Not pya script - DRC script is not part of OpenLane
+        self.run_subprocess(
+            [
+                "klayout",
+                "-b",
+                "-zz",
+                "-r",
+                drc_script_path,
+                "-rd",
+                f"in_gds={abspath(input_view)}",
+                "-rd",
+                f"report_file={abspath(xml_report)}",
+                *opts,
+            ]
+        )
+
+        subprocess_result = self.run_pya_script(
+            [
+                "python3",
+                os.path.join(
+                    get_script_dir(),
+                    "klayout",
+                    "xml_drc_report_to_json.py",
+                ),
+                f"--xml-file={abspath(xml_report)}",
+                f"--json-file={abspath(json_report)}",
+            ],
+            env=env,
+            log_to=os.path.join(self.step_dir, "xml_drc_report_to_json.log"),
+        )
+        return subprocess_result["generated_metrics"]
+
     def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
         metrics_updates: MetricsUpdate = {}
         if self.config["PDK"] in ["sky130A", "sky130B"]:
             metrics_updates = self.run_sky130(state_in, **kwargs)
+        elif self.config["PDK"] in ["ihp-sg13g2"]:
+            metrics_updates = self.run_ihp_sg13g2(state_in, **kwargs)
         else:
             self.warn(
                 f"KLayout DRC is not supported for the {self.config['PDK']} PDK. This step will be skipped."
@@ -443,6 +528,126 @@ class DRC(KLayoutStep):
         return {}, metrics_updates
 
 
+@Step.factory.register()
+class LVS(KLayoutStep):
+    id = "KLayout.LVS"
+    name = "Layout Versus Schematic (KLayout)"
+
+    inputs = [
+        DesignFormat.CDL,
+        DesignFormat.GDS,
+    ]
+    outputs = [DesignFormat.SPICE]
+
+    config_vars = KLayoutStep.config_vars + [
+        Variable(
+            "KLAYOUT_LVS_SCRIPT",
+            Optional[Path],
+            "A path to KLayout LVS script.",
+            pdk=True,
+        ),
+        Variable(
+            "KLAYOUT_LVS_OPTIONS",
+            Optional[Dict[str, Union[bool, int, str]]],
+            "Options passed directly to the KLayout LVS script. They vary from one PDK to another.",
+            pdk=True,
+        ),
+    ]
+
+    def run_ihp_sg13g2(
+        self, state_in: State, **kwargs
+    ) -> Tuple[ViewsUpdate, MetricsUpdate]:
+        kwargs, env = self.extract_env(kwargs)
+
+        lvs_script_path = self.config["KLAYOUT_LVS_SCRIPT"]
+
+        reports_dir = os.path.join(self.step_dir, "reports")
+        mkdirp(reports_dir)
+        lvsdb_report = os.path.join(reports_dir, "lvs.klayout.lvsdb")
+
+        input_view_gds = state_in[DesignFormat.GDS]
+        input_view_cdl = state_in[DesignFormat.CDL]
+        assert isinstance(input_view_gds, Path)
+        assert isinstance(input_view_cdl, Path)
+
+        output_spice = os.path.join(
+            self.step_dir,
+            f"{self.config['DESIGN_NAME']}.{DesignFormat.SPICE.value.extension}",
+        )
+
+        with NamedTemporaryFile("w") as f:
+            # Merge all CDL inputs
+            cdl_lst = [input_view_cdl]
+            cdl_lst.extend(self.config["CELL_CDLS"] or [])
+            cdl_lst.extend(self.config["EXTRA_CDLS"] or [])
+
+            for fn in cdl_lst:
+                with open(fn, "r") as cdl_fh:
+                    f.write(cdl_fh.read())
+
+            opts = []
+            for k, v in self.config["KLAYOUT_LVS_OPTIONS"].items():
+                opts.extend(
+                    [
+                        "-rd",
+                        f"{k}={v}",
+                    ]
+                )
+
+            # Not pya script - LVS script is not part of LibreLane
+            subprocess_result = self.run_subprocess(
+                [
+                    "klayout",
+                    "-b",
+                    "-zz",
+                    "-r",
+                    lvs_script_path,
+                    "-rd",
+                    f"input={abspath(input_view_gds)}",
+                    "-rd",
+                    f"schematic={abspath(f.name)}",
+                    "-rd",
+                    f"report={abspath(lvsdb_report)}",
+                    "-rd",
+                    f"target_netlist={abspath(output_spice)}",
+                ]
+                + opts,
+                env=env,
+            )
+
+            with open(subprocess_result["log_path"]) as fh:
+                for line in fh:
+                    if "INFO : Congratulations! Netlists match" in line:
+                        ok = True
+                        break
+                    elif "ERROR : Netlists don't match" in line:
+                        ok = False
+                        break
+                else:
+                    ok = False
+
+        views_updates: ViewsUpdate = {
+            DesignFormat.SPICE: Path(output_spice),
+        }
+        metrics_updates: MetricsUpdate = {
+            "design__lvs_error__count": 0 if ok else 1,
+        }
+
+        return views_updates, metrics_updates
+
+    def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
+        metrics_updates: MetricsUpdate = {}
+        views_updates: ViewsUpdate = {}
+        if self.config["PDK"] in ["ihp-sg13g2"]:
+            views_updates, metrics_updates = self.run_ihp_sg13g2(state_in, **kwargs)
+        else:
+            self.warn(
+                f"KLayout LVS is not supported for the {self.config['PDK']} PDK. This step will be skipped."
+            )
+
+        return views_updates, metrics_updates
+
+
 @Step.factory.register()
 class OpenGUI(KLayoutStep):
     """
@@ -480,7 +685,7 @@ class OpenGUI(KLayoutStep):
 
         layout = state_in[DesignFormat.DEF]
         if self.config["KLAYOUT_GUI_USE_GDS"]:
-            if gds := state_in[DesignFormat.GDS]:
+            if gds := state_in.get(DesignFormat.GDS):
                 layout = gds
         assert isinstance(layout, Path)
 

{librelane-3.0.0.dev26 → librelane-3.0.0.dev28}/librelane/steps/openroad.py

@@ -2188,6 +2188,20 @@ class WriteViews(OpenROADStep):
         return os.path.join(get_script_dir(), "openroad", "write_views.tcl")
 
 
+@Step.factory.register()
+class WriteCDL(OpenROADStep):
+    """
+    Write CDL view of an ODB design
+    """
+
+    id = "OpenROAD.WriteCDL"
+    name = "Write CDL"
+    outputs = [DesignFormat.CDL]
+
+    def get_script_path(self):
+        return os.path.join(get_script_dir(), "openroad", "write_cdl.tcl")
+
+
 # Resizer Steps
 
 

{librelane-3.0.0.dev26 → librelane-3.0.0.dev28}/librelane/steps/yosys.py

@@ -48,7 +48,7 @@ def _generate_read_deps(
     commands = ""
 
     synth_defines = [
-        f"PDK_{config['PDK']}",
+        f"PDK_{config['PDK'].replace('-','_')}",
         f"SCL_{config['STD_CELL_LIBRARY']}",
         "__librelane__",
         "__pnr__",

{librelane-3.0.0.dev26 → librelane-3.0.0.dev28}/pyproject.toml

@@ -1,6 +1,6 @@
 [tool.poetry]
 name = "librelane"
-version = "3.0.0.dev26"
+version = "3.0.0.dev28"
 description = "An infrastructure for implementing chip design flows"
 # Technically, maintainer. We cannot use the maintainers field until
 # poetry-core>=2.0.0 which requires Python version 3.9+. This field does

librelane-3.0.0.dev26/librelane/open_pdks_rev

@@ -1 +0,0 @@
-0fe599b2afb6708d281543108caf8310912f54af