librelane 3.0.0.dev23__tar.gz → 3.0.0.dev24__tar.gz

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: librelane
-Version: 3.0.0.dev23
+Version: 3.0.0.dev24
 Summary: An infrastructure for implementing chip design flows
 Home-page: https://github.com/librelane/librelane
 License: Apache-2.0

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/config/__main__.py

@@ -14,7 +14,6 @@
 import os
 import sys
 import json
-import functools
 from decimal import Decimal
 
 import click
@@ -111,9 +110,7 @@ def create_config(
                 print("At least one source RTL file is required.", file=sys.stderr)
                 exit(1)
     source_rtl_key = "VERILOG_FILES"
-    if not functools.reduce(
-        lambda acc, x: acc and (x.endswith(".sv") or x.endswith(".v")), source_rtl, True
-    ):
+    if not all((file.endswith(".sv") or file.endswith(".v")) for file in source_rtl):
         print(
             "Only Verilog/SystemVerilog files are supported by create-config.",
             file=sys.stderr,

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/config/removals.py

@@ -42,4 +42,5 @@ removed_variables: Dict[str, str] = {
     "FP_PADFRAME_CFG": "To be implemented.",
     "FP_CONTEXT_DEF": "To be implemented.",
     "FP_CONTEXT_LEF": "To be implemented.",
+    "SYNLIG_DEFER": "Synlig replaced with Slang.",
 }

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/config/variable.py

@@ -575,7 +575,7 @@ class Variable:
             kwargs_dict = {}
             for current_field in fields(validating_type):
                 key = current_field.name
-                subtype = current_field.type
+                subtype: Type[Any] = current_field.type  # type: ignore
                 explicitly_specified = False
                 if key in raw:
                     explicitly_specified = True

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/scripts/odbpy/reader.py

@@ -166,7 +166,7 @@ class OdbReader(object):
         grt.setMinLayerForClock(min_clk_idx)
         grt.setMaxLayerForClock(max_clk_idx)
         grt.setMacroExtension(self.config["GRT_MACRO_EXTENSION"])
-        grt.setOverflowIterations(self.config["GRT_OVERFLOW_ITERS"])
+        grt.setCongestionIterations(self.config["GRT_OVERFLOW_ITERS"])
         grt.setAllowCongestion(self.config["GRT_ALLOW_CONGESTION"])
         grt.setVerbose(True)
         grt.initFastRoute(min_layer_idx, max_layer_idx)

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/scripts/openroad/common/io.tcl

@@ -174,9 +174,9 @@ proc read_timing_info {args} {
     foreach nl $::env(_CURRENT_CORNER_NETLISTS) {
         puts "Reading macro netlist at '$nl'…"
         if { [catch {read_verilog $nl} err] } {
-            puts "Error while reading macro netlist '$nl':"
-            puts $err
-            puts "Make sure that this a gate-level netlist and not an RTL file."
+            puts stderr "Error while reading macro netlist '$nl':"
+            puts stderr $err
+            puts stderr "Make sure that this a gate-level netlist and not an RTL file."
             exit 1
         }
     }
@@ -185,9 +185,9 @@ proc read_timing_info {args} {
             if { [string_in_file $verilog_file $blackbox_wildcard] } {
                 puts "Found '$blackbox_wildcard' in '$verilog_file', skipping…"
             } elseif { [catch {puts "Reading Verilog model at '$verilog_file'…"; read_verilog $verilog_file} err] } {
-                puts "Error while reading $verilog_file:"
-                puts $err
-                puts "Make sure that this a gate-level netlist and not an RTL file, otherwise, you can add the following comment '$blackbox_wildcard' in the file to skip it and blackbox the modules inside if needed."
+                puts stderr "Error while reading $verilog_file:"
+                puts stderr $err
+                puts stderr "Make sure that this a gate-level netlist and not an RTL file, otherwise, you can add the following comment '$blackbox_wildcard' in the file to skip it and blackbox the modules inside if needed."
                 exit 1
             }
         }
@@ -411,6 +411,13 @@ proc write_views {args} {
         write_verilog $::env(SAVE_NL)
     }
 
+    if { [info exists ::env(SAVE_LOGICAL_NL)] } {
+        puts "Writing logic-only netlist to '$::env(SAVE_LOGICAL_NL)'…"
+        write_verilog\
+            -remove_cells "[get_physical_cells]"\
+            $::env(SAVE_LOGICAL_NL)
+    }
+
     if { [info exists ::env(SAVE_PNL)] } {
         puts "Writing powered netlist to '$::env(SAVE_PNL)'…"
         write_verilog -include_pwr_gnd $::env(SAVE_PNL)
@@ -575,7 +582,8 @@ proc get_layers {args} {
         flags {-constrained}
 
     if { ![info exists keys(-types)] } {
-        puts "\[ERROR\] Invalid usage of get_layers: -types is required."
+        puts stderr "\[ERROR\] Invalid usage of get_layers: -types is required."
+        return -code error
     }
 
     set layers [$::tech getLayers]

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/scripts/openroad/common/pdn_cfg.tcl

@@ -94,8 +94,7 @@ if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
         -grid stdcell_grid \
         -layer $::env(FP_PDN_RAIL_LAYER) \
         -width $::env(FP_PDN_RAIL_WIDTH) \
-        -followpins \
-        -starts_with POWER
+        -followpins
 
     add_pdn_connect \
         -grid stdcell_grid \
@@ -107,6 +106,7 @@ if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
 if { $::env(FP_PDN_CORE_RING) == 1 } {
     if { $::env(FP_PDN_MULTILAYER) == 1 } {
         add_pdn_ring \
+            -allow_out_of_die \
             -grid stdcell_grid \
             -layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)" \
             -widths "$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)" \

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/scripts/openroad/common/set_global_connections.tcl

@@ -56,7 +56,7 @@ proc set_global_connections {} {
                 }
             }
             if { $matched != 1 } {
-                puts "\[ERROR\] No match found for regular expression '$instance_name' defined in PDN_MACRO_CONNECTIONS."
+                puts stderr "\[ERROR\] No match found for regular expression '$instance_name' defined in PDN_MACRO_CONNECTIONS."
                 exit_unless_gui 1
             }
 

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/scripts/openroad/drt.tcl

@@ -17,8 +17,8 @@ proc drt_run {i args} {
     set output_drc "-output_drc $::env(STEP_DIR)/$directory/$::env(DESIGN_NAME).drc"
     log_cmd detailed_route {*}$args {*}$output_drc
     if { $::env(DRT_SAVE_SNAPSHOTS) } {
-        foreach snapshot [glob -nocomplain drt_iter*.odb] {
-            file rename -force $snapshot $directory/[file tail $snapshot]
+        foreach snapshot [glob -nocomplain $::env(STEP_DIR)/drt_iter*.odb] {
+            file rename -force $snapshot $::env(STEP_DIR)/$directory/[file tail $snapshot]
         }
     }
     foreach drc_file [glob -nocomplain $::env(STEP_DIR)/$directory/*.drc] {
@@ -41,13 +41,11 @@ set max_layer $::env(RT_MAX_LAYER)
 if { [info exists ::env(DRT_MAX_LAYER)] } {
     set max_layer $::env(DRT_MAX_LAYER)
 }
-if { $::env(DRT_SAVE_SNAPSHOTS) } {
-    set_debug_level DRT snapshot 1
-}
 set drc_report_iter_step_arg ""
 if { $::env(DRT_SAVE_SNAPSHOTS) } {
     set_debug_level DRT snapshot 1
     set drc_report_iter_step_arg "-drc_report_iter_step 1"
+    detailed_route_debug -snapshot_dir "$::env(STEP_DIR)/$directory"
 }
 if { [info exists ::env(DRT_SAVE_DRC_REPORT_ITERS)] } {
     set drc_report_iter_step_arg "-drc_report_iter_step $::env(DRT_SAVE_DRC_REPORT_ITERS)"

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/scripts/openroad/floorplan.tcl

@@ -33,10 +33,18 @@ puts "Using site height: $::default_site_height and site width: $::default_site_
 
 unset_propagated_clock [all_clocks]
 
-set bottom_margin  [expr $::default_site_height * $::env(BOTTOM_MARGIN_MULT)]
-set top_margin  [expr $::default_site_height * $::env(TOP_MARGIN_MULT)]
-set left_margin [expr $::default_site_width * $::env(LEFT_MARGIN_MULT)]
-set right_margin [expr $::default_site_width * $::env(RIGHT_MARGIN_MULT)]
+proc set_margin {var site_dimension mult} {
+    set value [expr $site_dimension * $mult]
+    if { $value < 0 } {
+        puts stderr "\[ERROR IFP-0013\] Negative values not allowed for margins."
+        exit_unless_gui 1
+    }
+    uplevel 1 set "$var $value"
+}
+set_margin bottom_margin $::default_site_height $::env(BOTTOM_MARGIN_MULT)
+set_margin top_margin $::default_site_height $::env(TOP_MARGIN_MULT)
+set_margin left_margin $::default_site_width $::env(LEFT_MARGIN_MULT)
+set_margin right_margin $::default_site_width $::env(RIGHT_MARGIN_MULT)
 
 set arg_list [list]
 

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/scripts/openroad/sta/check_macro_instances.tcl

@@ -30,10 +30,10 @@ foreach {instance_name macro_name} $::env(_check_macro_instances) {
     set instances [get_cells -hierarchical $instance_name]
     set instance_count [llength $instances]
     if { $instance_count < 1 } {
-        puts "\[ERROR\] No macro instance $instance_name found."
+        puts stderr "\[ERROR\] No macro instance $instance_name found."
         incr error_count
     } elseif { $instance_count > 1 } {
-        puts "\[ERROR\] Macro instance name $instance_name matches multiple cells."
+        puts stderr "\[ERROR\] Macro instance name $instance_name matches multiple cells."
         incr error_count
     } else {
         # The next line doesn't actually matter because this is Tcl but I'd feel
@@ -42,7 +42,7 @@ foreach {instance_name macro_name} $::env(_check_macro_instances) {
 
         set master_name [get_property $instance ref_name]
         if { $master_name != $macro_name } {
-            puts "\[ERROR\] Instance $instance_name is configured as an instance of macro $macro_name, but is an instance of $master_name."
+            puts stderr "\[ERROR\] Instance $instance_name is configured as an instance of macro $macro_name, but is an instance of $master_name."
             incr error_count
         }
     }

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/scripts/openroad/sta/corner.tcl

@@ -54,7 +54,7 @@ puts "\n========================================================================
 puts "report_checks -path_delay min (Hold)"
 puts "============================================================================"
 puts "======================= [$corner name] Corner ===================================\n"
-report_checks -sort_by_slack -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 1000 -corner [$corner name]
+report_checks -sort_by_slack -path_delay min -fields {slew cap input net fanout} -format full_clock_expanded -group_path_count 1000 -corner [$corner name]
 puts ""
 puts "%OL_END_REPORT"
 
@@ -64,7 +64,7 @@ puts "\n========================================================================
 puts "report_checks -path_delay max (Setup)"
 puts "============================================================================"
 puts "======================= [$corner name] Corner ===================================\n"
-report_checks -sort_by_slack -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 1000 -corner [$corner name]
+report_checks -sort_by_slack -path_delay max -fields {slew cap input net fanout} -format full_clock_expanded -group_path_count 1000 -corner [$corner name]
 puts ""
 puts "%OL_END_REPORT"
 
@@ -74,7 +74,7 @@ puts "\n========================================================================
 puts "report_checks -unconstrained"
 puts "==========================================================================="
 puts "======================= [$corner name] Corner ===================================\n"
-report_checks -unconstrained -fields {slew cap input nets fanout} -format full_clock_expanded -corner [$corner name]
+report_checks -unconstrained -fields {slew cap input net fanout} -format full_clock_expanded -corner [$corner name]
 puts ""
 
 
@@ -82,7 +82,7 @@ puts "\n========================================================================
 puts "report_checks --slack_max -0.01"
 puts "============================================================================"
 puts "======================= [$corner name] Corner ===================================\n"
-report_checks -slack_max -0.01 -fields {slew cap input nets fanout} -format full_clock_expanded -corner [$corner name]
+report_checks -slack_max -0.01 -fields {slew cap input net fanout} -format full_clock_expanded -corner [$corner name]
 puts ""
 
 puts "\n==========================================================================="
@@ -260,7 +260,7 @@ if { [info exists ::env(STA_MAX_VIOLATOR_COUNT)] } {
     set max_violator_count $::env(STA_MAX_VIOLATOR_COUNT)
 }
 
-set hold_violating_paths [find_timing_paths -unique_paths_to_endpoint -path_delay min -sort_by_slack -group_count $max_violator_count -slack_max 0]
+set hold_violating_paths [find_timing_paths -unique_paths_to_endpoint -path_delay min -sort_by_slack -group_path_count $max_violator_count -slack_max 0]
 foreach path $hold_violating_paths {
     set start_pin [get_property $path startpoint]
     set end_pin [get_property $path endpoint]
@@ -279,7 +279,7 @@ foreach path $hold_violating_paths {
 }
 
 set worst_r2r_hold_slack 1e30
-set hold_paths [find_timing_paths -unique_paths_to_endpoint -path_delay min -sort_by_slack -group_count $max_violator_count -slack_max $worst_r2r_hold_slack]
+set hold_paths [find_timing_paths -unique_paths_to_endpoint -path_delay min -sort_by_slack -group_path_count $max_violator_count -slack_max $worst_r2r_hold_slack]
 foreach path $hold_paths {
     set start_pin [get_property $path startpoint]
     set end_pin [get_property $path endpoint]
@@ -295,7 +295,7 @@ foreach path $hold_paths {
     }
 }
 
-set setup_violating_paths [find_timing_paths -unique_paths_to_endpoint -path_delay max -sort_by_slack -group_count $max_violator_count -slack_max 0]
+set setup_violating_paths [find_timing_paths -unique_paths_to_endpoint -path_delay max -sort_by_slack -group_path_count $max_violator_count -slack_max 0]
 foreach path $setup_violating_paths {
     set start_pin [get_property $path startpoint]
     set end_pin [get_property $path endpoint]
@@ -314,7 +314,7 @@ foreach path $setup_violating_paths {
 }
 
 set worst_r2r_setup_slack 1e30
-set setup_paths [find_timing_paths -unique_paths_to_endpoint -path_delay max -sort_by_slack -group_count $max_violator_count -slack_max $worst_r2r_setup_slack]
+set setup_paths [find_timing_paths -unique_paths_to_endpoint -path_delay max -sort_by_slack -group_path_count $max_violator_count -slack_max $worst_r2r_setup_slack]
 foreach path $setup_paths {
     set start_pin [get_property $path startpoint]
     set end_pin [get_property $path endpoint]

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/scripts/pyosys/json_header.py

@@ -62,8 +62,7 @@ def json_header(
         synth_parameters=config["SYNTH_PARAMETERS"] or [],
         includes=includes,
         defines=defines,
-        use_synlig=config["USE_SYNLIG"],
-        synlig_defer=config["SYNLIG_DEFER"],
+        use_slang=config["USE_SLANG"],
     )
     d.run_pass(
         "hierarchy",

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/scripts/pyosys/synthesize.py

@@ -262,8 +262,7 @@ def synthesize(
             synth_parameters=[],
             includes=includes,
             defines=defines,
-            use_synlig=False,
-            synlig_defer=False,
+            use_slang=False,
         )
     elif verilog_files := config.get("VERILOG_FILES"):
         d.read_verilog_files(
@@ -272,8 +271,7 @@ def synthesize(
             synth_parameters=config["SYNTH_PARAMETERS"] or [],
             includes=includes,
             defines=defines,
-            use_synlig=config["USE_SYNLIG"],
-            synlig_defer=config["SYNLIG_DEFER"],
+            use_slang=config["USE_SLANG"],
         )
     elif vhdl_files := config.get("VHDL_FILES"):
         d.run_pass("plugin", "-i", "ghdl")
@@ -300,6 +298,8 @@ def synthesize(
         )
     except Exception:
         pass
+    if config["SYNTH_NORMALIZE_SINGLE_BIT_VECTORS"]:
+        d.run_pass("attrmap", "-remove", "single_bit_vector")
     d.run_pass("select", "-clear")
 
     lib_arguments = []

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/scripts/pyosys/ys_common.py

@@ -50,48 +50,28 @@ def _Design_read_verilog_files(
     synth_parameters: Iterable[str],
     includes: Iterable[str],
     defines: Iterable[str],
-    use_synlig: bool = False,
-    synlig_defer: bool = False,
+    use_slang: bool = False,
 ):
     files = list(files)  # for easier concatenation
     include_args = [f"-I{dir}" for dir in includes]
     define_args = [f"-D{define}" for define in defines]
     chparams = {}
-    synlig_chparam_args = []
+    slang_chparam_args = []
     for chparam in synth_parameters:
         param, value = chparam.split("=", maxsplit=1)  # validate
         chparams[param] = value
-        synlig_chparam_args.append(f"-P{param}={value}")
+        slang_chparam_args.append(f"-G{param}={value}")
 
-    if use_synlig and synlig_defer:
-        self.run_pass("plugin", "-i", "synlig-sv")
-        for file in files:
-            self.run_pass(
-                "read_systemverilog",
-                "-defer",
-                "-sverilog",
-                *define_args,
-                *include_args,
-                file,
-            )
-        self.run_pass(
-            "read_systemverilog",
-            "-link",
-            "-sverilog",
-            "-top",
-            top,
-            *synlig_chparam_args,
-        )
-    elif use_synlig:
-        self.run_pass("plugin", "-i", "synlig-sv")
+    ys.log("use_slang" if use_slang else "wtaf")
+    if use_slang:
+        self.run_pass("plugin", "-i", "slang")
         self.run_pass(
-            "read_systemverilog",
-            "-sverilog",
-            "-top",
+            "read_slang",
+            "--top",
             top,
             *define_args,
             *include_args,
-            *synlig_chparam_args,
+            *slang_chparam_args,
             *files,
         )
     else:

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/state/design_format.py

@@ -157,6 +157,13 @@ DesignFormat(
     alts=["NETLIST"],
 ).register()
 
+DesignFormat(
+    "logical_nl",
+    "logical_nl.v",
+    "Logical cell-only Verilog Netlist",
+    folder_override="nl",
+).register()
+
 DesignFormat(
     "pnl",
     "pnl.v",

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/steps/odb.py

@@ -27,7 +27,7 @@ from ..config import Instance, Macro, Variable
 from ..logging import info, verbose
 from ..state import DesignFormat, State
 
-from .openroad import DetailedPlacement, GlobalRouting
+from .openroad import DetailedPlacement, GlobalRouting, OpenROADStep
 from .openroad_alerts import OpenROADAlert, OpenROADOutputProcessor
 from .common_variables import io_layer_variables, dpl_variables, grt_variables
 from .step import (
@@ -52,6 +52,10 @@ class OdbpyStep(Step):
 
     alerts: Optional[List[OpenROADAlert]] = None
 
+    @classmethod
+    def get_openroad_path(Self) -> str:
+        return OpenROADStep.get_openroad_path()
+
     def on_alert(self, alert: OpenROADAlert) -> OpenROADAlert:
         if alert.code in [
             "ORD-0039",  # .openroad ignored with -python
@@ -155,7 +159,7 @@ class OdbpyStep(Step):
             lefs.append(str(design_lef))
         return (
             [
-                "openroad",
+                self.get_openroad_path(),
                 "-exit",
                 "-no_splash",
                 "-metrics",
@@ -946,7 +950,12 @@ class CellFrequencyTables(OdbpyStep):
         lib_list = self.toolbox.filter_views(self.config, self.config["LIB"])
         env_copy["_PNR_LIBS"] = TclStep.value_to_tcl(lib_list)
         super().run_subprocess(
-            ["openroad", "-no_splash", "-exit", self.get_buffer_list_script()],
+            [
+                self.get_openroad_path(),
+                "-no_splash",
+                "-exit",
+                self.get_buffer_list_script(),
+            ],
             env=env_copy,
             log_to=self.get_buffer_list_file(),
         )

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/steps/openroad.py

@@ -267,6 +267,10 @@ class OpenROADStep(TclStep):
         ),
     ]
 
+    @classmethod
+    def get_openroad_path(Self) -> str:
+        return os.getenv("_LLN_OVERRIDE_OPENROAD", "openroad")
+
     @abstractmethod
     def get_script_path(self) -> str:
         pass
@@ -469,7 +473,7 @@ class OpenROADStep(TclStep):
     def get_command(self) -> List[str]:
         metrics_path = os.path.join(self.step_dir, "or_metrics_out.json")
         return [
-            "openroad",
+            self.get_openroad_path(),
             ("-gui" if os.getenv("_OPENROAD_GUI", "0") == "1" else "-exit"),
             "-no_splash",
             "-metrics",
@@ -956,7 +960,7 @@ class STAPostPNR(STAPrePNR):
                 lefs.append(lef)
         metrics_path = os.path.join(corner_dir, "filter_unannotated_metrics.json")
         filter_unannotated_cmd = [
-            "openroad",
+            self.get_openroad_path(),
             "-exit",
             "-no_splash",
             "-metrics",
@@ -1369,10 +1373,18 @@ class GeneratePDN(OpenROADStep):
             info(f"'FP_PDN_CFG' not explicitly set, setting it to {env['FP_PDN_CFG']}…")
         views_updates, metrics_updates = super().run(state_in, env=env, **kwargs)
 
+        alerts = self.alerts or []
         error_reports = glob(os.path.join(self.step_dir, "*-grid-errors.rpt"))
         for report in error_reports:
             net = os.path.basename(report).split("-", maxsplit=1)[0]
-            count = get_psm_error_count(open(report, encoding="utf8"))
+            no_terminals = any(
+                alert.code == "PSM-0025" and alert.message.startswith(net)
+                for alert in alerts
+            )
+            if no_terminals:
+                count = 1
+            else:
+                count = get_psm_error_count(open(report, encoding="utf8"))
             metrics_updates[f"design__power_grid_violation__count__net:{net}"] = count
 
         metric_updates_with_aggregates = aggregate_metrics(

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/steps/pyosys.py

@@ -122,16 +122,11 @@ verilog_rtl_cfg_vars = [
         "Key-value pairs to be `chparam`ed in Yosys, in the format `key1=value1`.",
     ),
     Variable(
-        "USE_SYNLIG",
+        "USE_SLANG",
         bool,
-        "Use the Synlig plugin to process files, which has better SystemVerilog parsing capabilities but may not be compatible with all Yosys commands and attributes.",
-        default=False,
-    ),
-    Variable(
-        "SYNLIG_DEFER",
-        bool,
-        "Uses -defer flag when reading files the Synlig plugin, which may improve performance by reading each file separately, but is experimental.",
+        "Use the Slang frontend to process files, which has better SystemVerilog parsing capabilities but is not as battle-tested as the default Yosys friend.",
         default=False,
+        deprecated_names=["USE_SYNLIG"],
     ),
 ]
 
@@ -216,6 +211,10 @@ class PyosysStep(Step):
         ),
     ]
 
+    @classmethod
+    def get_yosys_path(Self) -> str:
+        return os.getenv("_LLN_OVERRIDE_YOSYS", "yosys")
+
     @abstractmethod
     def get_script_path(self) -> str:
         pass
@@ -223,7 +222,7 @@ class PyosysStep(Step):
     def get_command(self, state_in: State) -> List[str]:
         script_path = self.get_script_path()
         # HACK: Get Colab working
-        yosys_bin = "yosys"
+        yosys_bin = self.get_yosys_path()
         if "google.colab" in sys.modules:
             yosys_bin = shutil.which("yosys") or "yosys"
         cmd = [yosys_bin, "-y", script_path]
@@ -497,6 +496,12 @@ class SynthesisCommon(VerilogStep):
             "If true, Verilog-2001 attributes are omitted from output netlists. Some utilities do not support attributes.",
             default=True,
         ),
+        Variable(
+            "SYNTH_NORMALIZE_SINGLE_BIT_VECTORS",
+            bool,
+            "If true, vectors with the shape [0:0] are converted to normal wires in the netlist. If disabled, even one-width pins will be suffixed [0] in the layout when imported by most PnR tools.",
+            default=True,
+        ),
         # Variable(
         #     "SYNTH_SDC_FILE",
         #     Optional[Path],

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/librelane/steps/yosys.py

@@ -19,7 +19,13 @@ from typing import List, Literal, Optional, Set, Tuple
 
 from .tclstep import TclStep
 from .step import ViewsUpdate, MetricsUpdate, Step
-from .pyosys import JsonHeader, verilog_rtl_cfg_vars, Synthesis, VHDLSynthesis
+from .pyosys import (
+    PyosysStep,
+    JsonHeader,
+    verilog_rtl_cfg_vars,
+    Synthesis,
+    VHDLSynthesis,
+)
 
 from ..config import Variable, Config
 from ..state import State, DesignFormat
@@ -210,9 +216,17 @@ class YosysStep(TclStep):
         ),
     ]
 
+    @classmethod
+    def get_yosys_path(Self) -> str:
+        return PyosysStep.get_yosys_path()
+
+    @abstractmethod
+    def get_script_path(self) -> str:
+        pass
+
     def get_command(self) -> List[str]:
         script_path = self.get_script_path()
-        cmd = ["yosys", "-c", script_path]
+        cmd = [self.get_yosys_path(), "-c", script_path]
         if self.config["YOSYS_LOG_LEVEL"] != "ALL":
             cmd += ["-Q"]
         if self.config["YOSYS_LOG_LEVEL"] == "WARNING":
@@ -221,10 +235,6 @@ class YosysStep(TclStep):
             cmd += ["-qq"]
         return cmd
 
-    @abstractmethod
-    def get_script_path(self) -> str:
-        pass
-
     def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
         power_defines = False
         if "power_defines" in kwargs:

{librelane-3.0.0.dev23 → librelane-3.0.0.dev24}/pyproject.toml

@@ -1,6 +1,6 @@
 [tool.poetry]
 name = "librelane"
-version = "3.0.0.dev23"
+version = "3.0.0.dev24"
 description = "An infrastructure for implementing chip design flows"
 # Technically, maintainer. We cannot use the maintainers field until
 # poetry-core>=2.0.0 which requires Python version 3.9+. This field does