librelane 2.4.0.dev0__tar.gz → 2.4.0.dev2__tar.gz

{librelane-2.4.0.dev0 → librelane-2.4.0.dev2}/PKG-INFO

@@ -1,7 +1,8 @@
-Metadata-Version: 2.3
+Metadata-Version: 2.1
 Name: librelane
-Version: 2.4.0.dev0
+Version: 2.4.0.dev2
 Summary: An infrastructure for implementing chip design flows
+Home-page: https://github.com/librelane/librelane
 License: Apache-2.0
 Author: Mohamed Gaber
 Author-email: me@donn.website
@@ -19,8 +20,7 @@ Requires-Dist: click (>=8,<9)
 Requires-Dist: cloup (>=3.0.5,<4)
 Requires-Dist: deprecated (>=1.2.10,<2)
 Requires-Dist: httpx (>=0.22.0,<0.29)
-Requires-Dist: ioplace-parser (>=0.3.0,<0.5.0)
-Requires-Dist: klayout (>=0.29.0,<0.30.0)
+Requires-Dist: klayout (>=0.29.0,<0.31.0)
 Requires-Dist: libparse (>=0.3.1,<1)
 Requires-Dist: lxml (>=4.9.0)
 Requires-Dist: psutil (>=5.9.0)
@@ -49,8 +49,10 @@ Description-Content-Type: text/markdown
 
 LibreLane is an ASIC infrastructure library based on several components including
 OpenROAD, Yosys, Magic, Netgen, CVC, KLayout and a number of custom scripts for
-design exploration and optimization, currently developed and maintained by the
-American University in Cairo Open Hardware Lab (AUCOHL.)
+design exploration and optimization, currently developed and maintained by
+members and affiliates of the
+[American University in Cairo Open Hardware Lab](https://github.com/aucohl)
+under the stewardship of the [FOSSi Foundation](https://fossi-foundation.org).
 
 A reference flow, "Classic", performs all ASIC implementation steps from RTL all
 the way down to GDSII.
@@ -142,10 +144,27 @@ If you use LibreLane in your research, please cite the following paper.
 
 ## License and Legal Info
 
-LibreLane is a trademark of the FOSSi Foundation.
+LibreLane is a trademark of the [FOSSi Foundation](https://fossi-foundation.org).
 
+LibreLane code and binaries are available under
 [The Apache License, version 2.0](https://www.apache.org/licenses/LICENSE-2.0.txt).
 
-LibreLane is based on OpenLane 2.0 by Efabless Corporation
-(https://github.com/efabless/openlane2) under the same license. 
+LibreLane is based on [OpenLane 2](https://github.com/efabless/openlane2)
+by Efabless Corporation:
+
+```
+Copyright 2022-2025 Efabless Corporation
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+     http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+``` 
 

{librelane-2.4.0.dev0 → librelane-2.4.0.dev2}/Readme.md

@@ -14,8 +14,10 @@
 
 LibreLane is an ASIC infrastructure library based on several components including
 OpenROAD, Yosys, Magic, Netgen, CVC, KLayout and a number of custom scripts for
-design exploration and optimization, currently developed and maintained by the
-American University in Cairo Open Hardware Lab (AUCOHL.)
+design exploration and optimization, currently developed and maintained by
+members and affiliates of the
+[American University in Cairo Open Hardware Lab](https://github.com/aucohl)
+under the stewardship of the [FOSSi Foundation](https://fossi-foundation.org).
 
 A reference flow, "Classic", performs all ASIC implementation steps from RTL all
 the way down to GDSII.
@@ -107,9 +109,26 @@ If you use LibreLane in your research, please cite the following paper.
 
 ## License and Legal Info
 
-LibreLane is a trademark of the FOSSi Foundation.
+LibreLane is a trademark of the [FOSSi Foundation](https://fossi-foundation.org).
 
+LibreLane code and binaries are available under
 [The Apache License, version 2.0](https://www.apache.org/licenses/LICENSE-2.0.txt).
 
-LibreLane is based on OpenLane 2.0 by Efabless Corporation
-(https://github.com/efabless/openlane2) under the same license. 
+LibreLane is based on [OpenLane 2](https://github.com/efabless/openlane2)
+by Efabless Corporation:
+
+```
+Copyright 2022-2025 Efabless Corporation
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+     http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+``` 

{librelane-2.4.0.dev0 → librelane-2.4.0.dev2}/librelane/__main__.py

@@ -1,3 +1,7 @@
+# Copyright 2025 The American University in Cairo
+#
+# Adapted from OpenLane
+#
 # Copyright 2023 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -202,7 +206,8 @@ def print_version(ctx: click.Context, param: click.Parameter, value: bool):
         f"""
         LibreLane v{__version__}
 
-        Copyright ©2020-2023 Efabless Corporation and other contributors.
+        Copyright ©2020-2025 Efabless Corporation, The American University in
+        Cairo, and other contributors.
 
         Available under the Apache License, version 2. Included with the source code,
         but you can also get a copy at https://www.apache.org/licenses/LICENSE-2.0

{librelane-2.4.0.dev0 → librelane-2.4.0.dev2}/librelane/config/config.py

@@ -102,7 +102,7 @@ class PassedDirectoryError(ValueError):
     def __init__(self, config: AnyPath) -> None:
         self.config = str(config)
         super().__init__(
-            "Passing design directories as arguments is unsupported in LibreLane 2 or higher: please pass the configuration file(s) directly."
+            "Passing design directories as arguments is unsupported in LibreLane: please pass the configuration file(s) directly."
         )
 
 
@@ -960,7 +960,7 @@ class Config(GenericImmutableDict[str, Any]):
                 pass
             if not isinstance(dis, int) or dis in [1, 2, 5] or dis > 6:
                 errors.append(
-                    f"DIODE_INSERTION_STRATEGY '{dis}' is not available in LibreLane 2 or higher. See 'Migrating DIODE_INSERTION_STRATEGY' in the docs for more info."
+                    f"DIODE_INSERTION_STRATEGY '{dis}' is not available in LibreLane 2.0 or higher. See 'Migrating DIODE_INSERTION_STRATEGY' in the docs for more info."
                 )
             else:
                 warnings.append(

{librelane-2.4.0.dev0 → librelane-2.4.0.dev2}/librelane/container.py

@@ -12,7 +12,7 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
-## This file is internal to LibreLane 2 and is not part of the API.
+## This file is internal to LibreLane and is not part of the API.
 import os
 import re
 import uuid

{librelane-2.4.0.dev0 → librelane-2.4.0.dev2}/librelane/env_info.py

@@ -18,7 +18,7 @@
 # environment surveys. Please ensure all code as compatible as possible
 # with ancient versions of Python.
 
-## This file is internal to LibreLane 2 and is not part of the API.
+## This file is internal to LibreLane and is not part of the API.
 import os
 import re
 import sys

{librelane-2.4.0.dev0 → librelane-2.4.0.dev2}/librelane/flows/classic.py

@@ -30,11 +30,8 @@ from ..steps import (
 @Flow.factory.register()
 class Classic(SequentialFlow):
     """
-    **Note: While LibreLane 2 has a stable release, the default flow is in beta
-    pending silicon validation. Use at your own risk.**
-
     A flow of type :class:`librelane.flows.SequentialFlow` that is the most
-    similar to the original LibreLane 1.0 flow, running the Verilog RTL through
+    similar to the original OpenLane flow, running the Verilog RTL through
     Yosys, OpenROAD, KLayout and Magic to produce a valid GDSII for simpler designs.
 
     This is the default when using LibreLane via the command-line.

{librelane-2.4.0.dev0 → librelane-2.4.0.dev2}/librelane/flows/optimizing.py

@@ -23,7 +23,7 @@ from ..steps import Step, Yosys, OpenROAD, StepError
 from ..logging import get_log_level, set_log_level, LogLevels, success, info
 
 
-#   "Optimizing" is a custom demo flow to show what's possible with non-sequential Flows in LibreLane 2+.
+#   "Optimizing" is a custom demo flow to show what's possible with non-sequential Flows in LibreLan
 #   It works across two steps:
 #   * The Synthesis Exploration - tries multiple synthesis strategies in *parallel*.
 #       The best-performing strategy in terms of minimizing the area makes it to the next stage.

librelane-2.4.0.dev2/librelane/scripts/odbpy/ioplace_parser/__init__.py

@@ -0,0 +1,23 @@
+# Copyright 2025 The American University in Cairo
+#
+# Adapted from ioplace_parser
+#
+# Copyright 2020-2023 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+"""
+This is a modified version of https://github.com/efabless/ioplace_parser that
+does NOT use Antlr4 and instead uses a custom parser that is faster and
+dependency-free.
+"""
+from .parse import Side, Order, parse

librelane-2.4.0.dev2/librelane/scripts/odbpy/ioplace_parser/parse.py

@@ -0,0 +1,147 @@
+# Copyright 2025 The American University in Cairo
+#
+# Adapted from ioplace_parser
+#
+# Copyright 2020-2023 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+import re
+from enum import IntEnum
+from typing import Literal, Optional, Dict, List, Union
+from decimal import Decimal
+import warnings
+
+from dataclasses import dataclass, field
+
+
+class Order(IntEnum):
+    busMajor = 0
+    bitMajor = 1
+
+
+@dataclass
+class Side:
+    min_distance: Optional[Decimal] = None
+    reverse_result: bool = False
+    pins: List[Union[str, int]] = field(default_factory=list)
+    sort_mode: Optional[Order] = Order.busMajor
+
+
+VALUE_ANNOTATIONS = ["min_distance"]
+STANDALONE_ANNOTATIONS = [
+    "bus_major",
+    "bit_major",
+]
+
+
+def parse(string: str) -> Dict[Literal["N", "E", "W", "S"], Side]:
+    """
+    Parses a pin configuration into a dictionary of the four cardinal sides.
+
+    :param string: The input configuration as a string (not a file path)
+    :returns: A dictionary where each cardinal direction points to a Side object.
+    :raises ValueError: On syntax or token recognition errors
+    """
+    sides = {}
+    current_side: Optional[Side] = None
+    global_sort_mode: Order = Order.busMajor
+    global_min_distance: Optional[Decimal] = None
+
+    string_mut = string
+
+    ws_rx = re.compile(r"^\s+")
+    annotation_rx = re.compile(r"^@\s*(\w+)(?:\s*=\s*([0-9]+(?:.[0-9]+)?))?")
+    direction_rx = re.compile(r"^#\s*([NEWS]R?|BUS_SORT)")
+    virtual_pin_rx = re.compile(r"^\$\s*([0-9]+)")
+    non_ws_rx = re.compile(r"^\S+")
+    while len(string_mut):
+        # annotation
+        if skip_match := ws_rx.search(string_mut):
+            string_mut = string_mut[skip_match.end() :]
+        elif anno_match := annotation_rx.search(string_mut):
+            annotation = anno_match[1]
+            if annotation in VALUE_ANNOTATIONS:
+                if anno_match[2] is None:
+                    raise ValueError(f"Annotation {annotation} requires a value")
+                value = anno_match[2]
+                if annotation == "min_distance":
+                    if current_side is None:
+                        global_min_distance = Decimal(value)
+                    else:
+                        current_side.min_distance = Decimal(value)
+            elif annotation in STANDALONE_ANNOTATIONS:
+                if anno_match[2] is not None:
+                    raise ValueError(
+                        f"Annotation {annotation} cannot be assigned a value"
+                    )
+                if annotation == "bus_major":
+                    if current_side is None:
+                        global_sort_mode = Order.busMajor
+                    else:
+                        current_side.sort_mode = Order.busMajor
+                elif annotation == "bit_major":
+                    if current_side is None:
+                        global_sort_mode = Order.bitMajor
+                    else:
+                        current_side.sort_mode = Order.bitMajor
+            else:
+                raise ValueError(f"Unknown annotation '{annotation}'")
+            string_mut = string_mut[anno_match.end() :]
+        elif dir_match := direction_rx.search(string_mut):
+            direction = dir_match[1]
+            if direction == "BUS_SORT":
+                warnings.warn(
+                    "Specifying bit-major using the direction token ('#BUS_SORT') is deprecated: use @bit_major."
+                )
+                global_sort_mode = Order.bitMajor
+            else:
+                current_side = Side(
+                    min_distance=global_min_distance,
+                    reverse_result=len(direction) == 2,
+                    sort_mode=global_sort_mode,
+                )
+                side: Literal["N", "E", "W", "S"] = direction[0]  # type: ignore
+                sides[side] = current_side
+            string_mut = string_mut[dir_match.end() :]
+        elif vp_match := virtual_pin_rx.search(string_mut):
+            count = int(vp_match[1])
+            if current_side is None:
+                raise ValueError(
+                    f"virtual pin declaration ${count} requires a direction to be set first"
+                )
+            current_side.pins.append(count)
+            string_mut = string_mut[vp_match.end() :]
+        elif nonws_match := non_ws_rx.match(string_mut):
+            # assume regex
+            if current_side is None:
+                raise ValueError(
+                    f"identifier/regex '{nonws_match[0]}' requires a direction to be set first"
+                )
+            current_side.pins.append(nonws_match[0])
+            string_mut = string_mut[nonws_match.end() :]
+        else:
+            raise ValueError(
+                f"Syntax Error: Unexpected character starting at {string_mut[:10]}…"
+            )
+
+    all_sides: List[Literal["N", "E", "W", "S"]] = ["N", "E", "W", "S"]
+    for side in all_sides:
+        if side in sides:
+            continue
+        sides[side] = Side(
+            min_distance=global_min_distance,
+            reverse_result=False,
+            sort_mode=global_sort_mode,
+        )
+
+    return sides

{librelane-2.4.0.dev0 → librelane-2.4.0.dev2}/librelane/steps/__main__.py

@@ -418,7 +418,7 @@ def create_reproducible(
         * The current working directory
 
     These reproducibles are filesystem-independent, i.e. they can be run
-    on any computer that has the appropriate version of LibreLane 2 installed
+    on any computer that has the appropriate version of LibreLane installed
     (as well as the underlying utility for that specific step.)
 
     The reproducible will report an error if LibreLane is not installed and will

{librelane-2.4.0.dev0 → librelane-2.4.0.dev2}/pyproject.toml

@@ -1,6 +1,6 @@
 [tool.poetry]
 name = "librelane"
-version = "2.4.0dev0"
+version = "2.4.0.dev2"
 description = "An infrastructure for implementing chip design flows"
 authors = ["Mohamed Gaber <me@donn.website>", "Efabless Corporation"]
 readme = "Readme.md"
@@ -21,9 +21,8 @@ deprecated = ">=1.2.10,<2"
 libparse = ">=0.3.1,<1"
 psutil = ">=5.9.0"
 httpx = ">=0.22.0,<0.29"
-klayout = ">=0.29.0,<0.30.0"
+klayout = ">=0.29.0,<0.31.0"
 rapidfuzz = ">=3.9.0,<4"
-ioplace-parser = ">=0.3.0,<0.5.0"
 yamlcore = "^0.0.2"
 semver = "^3.0.2"