leechcorepyc 2.22.0__tar.gz → 2.22.1__tar.gz

{leechcorepyc-2.22.0/leechcorepyc.egg-info → leechcorepyc-2.22.1}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 1.2
 Name: leechcorepyc
-Version: 2.22.0
+Version: 2.22.1
 Summary: LeechCore for Python
 Home-page: https://github.com/ufrisk/LeechCore
 Author: Ulf Frisk

{leechcorepyc-2.22.0 → leechcorepyc-2.22.1}/leechcore/device_fpga.c

@@ -3836,6 +3836,7 @@ BOOL DeviceFPGA_SetOption_DoLock(_In_ PLC_CONTEXT ctxLC, _In_ QWORD fOption, _In
 #define FPGA_PARAMETER_FT2232H         "ft2232h"
 #define FPGA_PARAMETER_PCIE            "pciegen"
 #define FPGA_PARAMETER_PCIE_NOCONNECT  "pcienotconnected"
+#define FPGA_PARAMETER_PCIE_NOCONNECT2 "nc"
 #define FPGA_PARAMETER_RESTART_DEVICE  "devreload"
 #define FPGA_PARAMETER_DELAY_READ      "tmread"
 #define FPGA_PARAMETER_DELAY_WRITE     "tmwrite"
@@ -3891,7 +3892,8 @@ BOOL DeviceFPGA_Open(_Inout_ PLC_CONTEXT ctxLC, _Out_opt_ PPLC_CONFIG_ERRORINFO
     }
     // verify parameters and set version&speed
     DeviceFPGA_SetSpeedPCIeGen(ctx, (DWORD)LcDeviceParameterGetNumeric(ctxLC, FPGA_PARAMETER_PCIE));
-    if(!ctx->wDeviceId && !LcDeviceParameterGetNumeric(ctxLC, FPGA_PARAMETER_PCIE_NOCONNECT)) {
+    if((v = LcDeviceParameterGetNumeric(ctxLC, FPGA_PARAMETER_DEVICE_ID))) { ctx->wDeviceId = (WORD)v; }
+    if(!ctx->wDeviceId && !(LcDeviceParameterGetNumeric(ctxLC, FPGA_PARAMETER_PCIE_NOCONNECT) || LcDeviceParameterGetNumeric(ctxLC, FPGA_PARAMETER_PCIE_NOCONNECT2))) {
         szDeviceError = "Unable to retrieve required Device PCIe ID";
         goto fail;
     }
@@ -3919,7 +3921,6 @@ BOOL DeviceFPGA_Open(_Inout_ PLC_CONTEXT ctxLC, _Out_opt_ PPLC_CONFIG_ERRORINFO
     if((v = LcDeviceParameterGetNumeric(ctxLC, FPGA_PARAMETER_DELAY_PROBE))) { ctx->perf.DELAY_PROBE_READ = (DWORD)v; }
     if((v = LcDeviceParameterGetNumeric(ctxLC, FPGA_PARAMETER_READ_RETRY)))  { ctx->perf.RETRY_ON_ERROR = (DWORD)v; }
     if((v = LcDeviceParameterGetNumeric(ctxLC, FPGA_PARAMETER_READ_SIZE)))   { ctx->perf.MAX_SIZE_RX = min(ctx->perf.MAX_SIZE_RX, (DWORD)v & ~0xfff); }
-    if((v = LcDeviceParameterGetNumeric(ctxLC, FPGA_PARAMETER_DEVICE_ID)))   { ctx->wDeviceId = (WORD)v; }
     v = LcDeviceParameterGetNumeric(ctxLC, FPGA_PARAMETER_READ_ALGORITHM);
     ctx->fAlgorithmReadTiny = ((v & FPGA_PARAMETER_ALGO_TINY) ? TRUE : FALSE) || ctx->perf.F_TINY;
     ctx->async2.fEnabled = ctx->async2.fEnabled && !(v & FPGA_PARAMETER_ALGO_SYNCHRONOUS) && !ctx->perf.RX_FLUSH_LIMIT;

{leechcorepyc-2.22.0 → leechcorepyc-2.22.1}/leechcore/version.h

@@ -3,8 +3,8 @@
 
 #define VERSION_MAJOR               2
 #define VERSION_MINOR               22
-#define VERSION_REVISION            0
-#define VERSION_BUILD               86
+#define VERSION_REVISION            1
+#define VERSION_BUILD               87
 
 #define VER_FILE_DESCRIPTION_STR    "LeechCore Memory Acquisition Library"
 #define VER_FILE_VERSION            VERSION_MAJOR, VERSION_MINOR, VERSION_REVISION, VERSION_BUILD

{leechcorepyc-2.22.0 → leechcorepyc-2.22.1}/leechcore_device_rawtcp/version.h

@@ -4,9 +4,9 @@
 #endif
 
 #define VERSION_MAJOR               2
-#define VERSION_MINOR               21
+#define VERSION_MINOR               22
 #define VERSION_REVISION            1
-#define VERSION_BUILD               85
+#define VERSION_BUILD               87
 
 #define VER_FILE_DESCRIPTION_STR    "LeechCorePlugin : RAWTCP"
 #define VER_FILE_VERSION            VERSION_MAJOR, VERSION_MINOR, VERSION_REVISION, VERSION_BUILD

{leechcorepyc-2.22.0 → leechcorepyc-2.22.1/leechcorepyc.egg-info}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 1.2
 Name: leechcorepyc
-Version: 2.22.0
+Version: 2.22.1
 Summary: LeechCore for Python
 Home-page: https://github.com/ufrisk/LeechCore
 Author: Ulf Frisk

{leechcorepyc-2.22.0 → leechcorepyc-2.22.1}/setup.py

@@ -19,7 +19,7 @@ leechcorepyc = Extension(
 
 setup(
     name='leechcorepyc',
-    version='2.22.0', # VERSION_END
+    version='2.22.1', # VERSION_END
     description='LeechCore for Python',
     long_description='LeechCore for Python : native extension for physical memory access',
     url='https://github.com/ufrisk/LeechCore',