leechcorepyc 2.19.0__tar.gz → 2.19.2__tar.gz

{leechcorepyc-2.19.0/leechcorepyc.egg-info → leechcorepyc-2.19.2}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 1.2
 Name: leechcorepyc
-Version: 2.19.0
+Version: 2.19.2
 Summary: LeechCore for Python
 Home-page: https://github.com/ufrisk/LeechCore
 Author: Ulf Frisk

{leechcorepyc-2.19.0 → leechcorepyc-2.19.2}/leechcore/device_fpga.c

@@ -1850,9 +1850,15 @@ VOID DeviceFPGA_GetDeviceID_FpgaVersion(_In_ PDEVICE_CONTEXT_FPGA ctx)
 VOID DeviceFPGA_SetPerformanceProfile(_Inout_ PDEVICE_CONTEXT_FPGA ctx)
 {
     if((ctx->wFpgaID >= DEVICE_ID_DRIVER_SUPPLIED_0) && (ctx->wFpgaID <= DEVICE_ID_DRIVER_SUPPLIED_7)) {
-        if(ctx->dev.pfnLcSetPerformanceProfile && (0 == ctx->dev.pfnLcSetPerformanceProfile(&ctx->perf, DEVICE_PERFORMANCE_VERSION, ctx->wFpgaID))) {
+        if(!ctx->dev.pfnLcSetPerformanceProfile) {
+            printf("DEVICE: FPGA: ERROR! Unable to locate performance profile export.\n");
             return;
         }
+        if((0 != ctx->dev.pfnLcSetPerformanceProfile(&ctx->perf, DEVICE_PERFORMANCE_VERSION, ctx->wFpgaID))) {
+            printf("DEVICE: FPGA: ERROR! Unable to load performance profile - ensure leechcore.dll/so and leechcore_driver.dll/so are compatible!\n");
+            return;
+        }
+        return;     // driver-supplied performance profile loaded successfully!
     }
     memcpy(&ctx->perf, &PERFORMANCE_PROFILES[(ctx->wFpgaID <= DEVICE_ID_MAX) ? ctx->wFpgaID : 0], sizeof(DEVICE_PERFORMANCE));
 }
@@ -2214,6 +2220,22 @@ VOID DeviceFPGA_RxTlp_UserCallback(_In_ PLC_CONTEXT ctxLC, _In_ PDEVICE_CONTEXT_
     if(szTlpText) { LocalFree(szTlpText); }
 }
 
+/*
+* Queue a received TLP for user callback by the user-callback thread.
+*/
+VOID DeviceFPGA_RxTlp_QueueUserCallback(_In_ PDEVICE_CONTEXT_FPGA ctx, _In_ SIZE_T cbTlp, _In_ PBYTE pbTlp)
+{
+    DWORD hdrDwBuf;
+    PTLP_HDR hdr = (PTLP_HDR)&hdrDwBuf;
+    if(ctx->tlp_callback.fNoCpl && (cbTlp >= 4)) {
+        hdrDwBuf = _byteswap_ulong(*(PDWORD)pbTlp);
+        if((hdr->TypeFmt == TLP_Cpl) || (hdr->TypeFmt == TLP_CplD) || (hdr->TypeFmt == TLP_CplLk) || (hdr->TypeFmt == TLP_CplDLk)) {
+            return;
+        }
+    }
+    ObByteQueue_Push(ctx->tlp_callback.pBqRx, 0, cbTlp, pbTlp);
+}
+
 VOID DeviceFPGA_Synch_RxTlpSynchronous(_In_ PLC_CONTEXT ctxLC, _In_ PDEVICE_CONTEXT_FPGA ctx, _In_opt_ DWORD dwBytesToRead)
 {
     DWORD status;
@@ -2267,7 +2289,7 @@ VOID DeviceFPGA_Synch_RxTlpSynchronous(_In_ PLC_CONTEXT ctxLC, _In_ PDEVICE_CONT
                             TLP_Print(ctxLC, pbTlp, cdwTlp << 2, FALSE);
                         }
                         if(ctx->tlp_callback.pBqRx) {
-                            ObByteQueue_Push(ctx->tlp_callback.pBqRx, 0, (SIZE_T)cdwTlp << 2, pbTlp);
+                            DeviceFPGA_RxTlp_QueueUserCallback(ctx, (SIZE_T)cdwTlp << 2, pbTlp);
                         }
                         if(ctx->hRxTlpCallbackFn) {
                             ctx->hRxTlpCallbackFn(ctx->pMRdBufferX, pbTlp, cdwTlp << 2);
@@ -2575,7 +2597,7 @@ DWORD DeviceFPGA_Async2_Read_RxTlpSingle(_In_ PLC_CONTEXT ctxLC, _In_ PDEVICE_CO
                     TLP_Print(ctxLC, pbTlp, cdwTlp << 2, FALSE);
                 }
                 if(ctx->tlp_callback.pBqRx) {
-                    ObByteQueue_Push(ctx->tlp_callback.pBqRx, 0, (SIZE_T)cdwTlp << 2, pbTlp);
+                    DeviceFPGA_RxTlp_QueueUserCallback(ctx, (SIZE_T)cdwTlp << 2, pbTlp);
                 }
                 DeviceFPGA_Async2_Read_RxTlpSingle_MRdCpl(ctxLC, ctx, pbTlp, cdwTlp << 2);
                 pdwData[iStartWord] = pdwData[iStartWord] | (0xffffffff >> (28 - (j << 2)));
@@ -3024,7 +3046,7 @@ DWORD DeviceFPGA_SynchOldAsync_Tlp(_In_ PLC_CONTEXT ctxLC, _In_ PDEVICE_CONTEXT_
                     TLP_Print(ctxLC, pbTlp, cdwTlp << 2, FALSE);
                 }
                 if(ctx->tlp_callback.pBqRx) {
-                    ObByteQueue_Push(ctx->tlp_callback.pBqRx, 0, (SIZE_T)cdwTlp << 2, pbTlp);
+                    DeviceFPGA_RxTlp_QueueUserCallback(ctx, (SIZE_T)cdwTlp << 2, pbTlp);
                 }
                 if(ctx->hRxTlpCallbackFn) {
                     ctx->hRxTlpCallbackFn(ctx->pMRdBufferX, pbTlp, cdwTlp << 2);
@@ -3133,8 +3155,8 @@ DWORD DeviceFPGA_Tlp_Callback_ThreadProc(_In_ PLC_CONTEXT ctxLC)
     if(ctx->tlp_callback.fThread) { return 1; }
     ctx->tlp_callback.fThread = TRUE;
     InterlockedIncrement(&ctxLC->dwHandleCount);    // increment device handle count
-    if(!(ctx->tlp_callback.pBqRx = ObByteQueue_New(NULL, 0x00100000))) { goto fail; }
-    if(!(ctx->tlp_callback.pBqTx = ObByteQueue_New(NULL, 0x00100000))) { goto fail; }
+    if(!(ctx->tlp_callback.pBqRx = ObByteQueue_New(NULL, 0x01000000))) { goto fail; }   // 16MB
+    if(!(ctx->tlp_callback.pBqTx = ObByteQueue_New(NULL, 0x00100000))) { goto fail; }   //  1MB
     while(TRUE) {
         fActiveRun = FALSE;
         // Exit criteria?:

{leechcorepyc-2.19.0 → leechcorepyc-2.19.2}/leechcore/ob/ob_bytequeue.c

@@ -110,24 +110,28 @@ _Success_(return)
 BOOL _ObByteQueue_Push(_In_ POB_BYTEQUEUE pq, _In_opt_ QWORD qwTag, _In_ SIZE_T cb, _In_reads_bytes_(cb) PBYTE pb)
 {
     PBYTEQUEUE_PACKET p;
-    if(cb >= 0x80000000) {
+    SIZE_T cboEoQ, cbEoQ, cbPkt = sizeof(BYTEQUEUE_PACKET) + cb;
+    if(pq->cb < cbPkt) {
         return FALSE;
     }
-    if(pq->cPackets) {
+    if(!pq->cPackets) {
+        // 1st packet to be inserted at start-of-queue.
+        p = (PBYTEQUEUE_PACKET)pq->pb;
+    } else {
+        // Nth packet to be inserted at end-of-queue.
         p = (PBYTEQUEUE_PACKET)(pq->pb + pq->cboTail);
-        if(pq->cb - sizeof(BYTEQUEUE_PACKET) - p->cb >= cb + sizeof(BYTEQUEUE_PACKET)) {
-            p->cboNext = (DWORD)((SIZE_T)p - (SIZE_T)pq->pb + sizeof(BYTEQUEUE_PACKET) + p->cb);
+        cboEoQ = pq->cboTail + sizeof(BYTEQUEUE_PACKET) + p->cb;
+        cbEoQ = ((pq->cboHead < cboEoQ) ? pq->cb : pq->cboHead) - cboEoQ;
+        if(cbEoQ >= cbPkt) {
+            // Insert packet at next position in the circular buffer.
+            p->cboNext = (DWORD)cboEoQ;
             p = (PBYTEQUEUE_PACKET)(pq->pb + p->cboNext);
-        } else if(pq->cboHead >= cb + sizeof(BYTEQUEUE_PACKET)) {
+        } else if((pq->cboTail > pq->cboHead) && (pq->cboHead >= cbPkt)) {
+            // Insert packet at start of the circular buffer.
             p->cboNext = 0;
-            p = (PBYTEQUEUE_PACKET)pq->pb;
-        } else {
-            return FALSE;
-        }
-    } else {
-        if(pq->cb >= cb + sizeof(BYTEQUEUE_PACKET)) {
-            p = (PBYTEQUEUE_PACKET)pq->pb;
+            p = (PBYTEQUEUE_PACKET)(pq->pb + p->cboNext);
         } else {
+            // Not enough space.
             return FALSE;
         }
     }

{leechcorepyc-2.19.0 → leechcorepyc-2.19.2}/leechcore/version.h

@@ -3,8 +3,8 @@
 
 #define VERSION_MAJOR               2
 #define VERSION_MINOR               19
-#define VERSION_REVISION            0
-#define VERSION_BUILD               79
+#define VERSION_REVISION            2
+#define VERSION_BUILD               81
 
 #define VER_FILE_DESCRIPTION_STR    "LeechCore Memory Acquisition Library"
 #define VER_FILE_VERSION            VERSION_MAJOR, VERSION_MINOR, VERSION_REVISION, VERSION_BUILD

{leechcorepyc-2.19.0 → leechcorepyc-2.19.2/leechcorepyc.egg-info}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 1.2
 Name: leechcorepyc
-Version: 2.19.0
+Version: 2.19.2
 Summary: LeechCore for Python
 Home-page: https://github.com/ufrisk/LeechCore
 Author: Ulf Frisk

{leechcorepyc-2.19.0 → leechcorepyc-2.19.2}/setup.py

@@ -19,7 +19,7 @@ leechcorepyc = Extension(
 
 setup(
     name='leechcorepyc',
-    version='2.19.0', # VERSION_END
+    version='2.19.2', # VERSION_END
     description='LeechCore for Python',
     long_description='LeechCore for Python : native extension for physical memory access',
     url='https://github.com/ufrisk/LeechCore',