lambdapdk 0.2.6__tar.gz → 0.2.7__tar.gz

{lambdapdk-0.2.6/lambdapdk.egg-info → lambdapdk-0.2.7}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: lambdapdk
-Version: 0.2.6
+Version: 0.2.7
 Summary: Library of open source Process Design Kits
 Author: Zero ASIC
 License:                                  Apache License
@@ -199,12 +199,12 @@ Requires-Python: >=3.8
 Description-Content-Type: text/markdown
 License-File: LICENSE
 Requires-Dist: siliconcompiler>=0.35.0
-Requires-Dist: lambdalib>=0.5.0
+Requires-Dist: lambdalib>=0.7.0
 Provides-Extra: test
 Requires-Dist: flake8==7.3.0; extra == "test"
-Requires-Dist: pytest==8.4.2; extra == "test"
+Requires-Dist: pytest==9.0.2; extra == "test"
 Requires-Dist: pytest-timeout==2.4.0; extra == "test"
-Requires-Dist: tclint==0.6.2; extra == "test"
+Requires-Dist: tclint==0.7.0; extra == "test"
 Requires-Dist: sc-leflib==0.5.1; extra == "test"
 Requires-Dist: Jinja2==3.1.6; extra == "test"
 Dynamic: license-file

{lambdapdk-0.2.6 → lambdapdk-0.2.7}/lambdapdk/__init__.py

@@ -11,7 +11,7 @@ from siliconcompiler.tools.openroad import OpenROADStdCellLibrary
 from siliconcompiler.tools.bambu import BambuStdCellLibrary
 from siliconcompiler.tools.klayout import KLayoutLibrary
 
-__version__ = "0.2.6"
+__version__ = "0.2.7"
 
 
 class _LambdaPath(PathSchema):

{lambdapdk-0.2.6 → lambdapdk-0.2.7}/lambdapdk/asap7/libs/fakeram7.py

@@ -1,12 +1,20 @@
+import argparse
+import math
+
+import os.path
+
 from pathlib import Path
 
+from typing import Dict, Tuple
+
 from lambdalib import LambalibTechLibrary
 from lambdapdk import LambdaLibrary, _LambdaPath
-from lambdalib.ramlib import Spram, Dpram, Tdpram
+from lambdalib.ramlib import Spram, Dpram, Tdpram, RAMTechLib
 from lambdapdk.asap7 import ASAP7PDK
+from lambdapdk.utils import format_verilog
 
 
-class _FakeRAM7Library(LambdaLibrary):
+class _FakeRAM7Library(LambdaLibrary, RAMTechLib):
     def __init__(self, config):
         super().__init__()
         self.set_name(f"fakeram7_{config}")
@@ -33,6 +41,89 @@ class _FakeRAM7Library(LambdaLibrary):
 
             self.add_klayout_allowmissingcell(self.name)
 
+    def __ram_props(self) -> Tuple[str, int, int]:
+        """Returns the RAM properties (width, depth) based on the configuration."""
+        type, size = self.name.split('_')[-2:]
+        width = int(size.split('x')[1])
+        depth = int(size.split('x')[0])
+        return type, width, depth
+
+    def get_ram_width(self) -> int:
+        """Returns the width of the RAM cell.
+
+        Returns:
+            int: The width of the RAM cell.
+        """
+        _, width, _ = self.__ram_props()
+        return width
+
+    def get_ram_depth(self) -> int:
+        """Returns the depth of the RAM cell.
+
+        Returns:
+            int: The depth of the RAM cell.
+        """
+        _, _, depth = self.__ram_props()
+        return int(math.log2(depth))
+
+    def get_ram_ports(self) -> Dict[str, str]:
+        """Returns the port mapping for the RAM cell.
+
+        Returns:
+            Dict[str, str]: A dictionary mapping port names to their expressions.
+        """
+        type, _, _ = self.__ram_props()
+        if type == "sp":
+            return {
+                "clk": "clk",
+                "addr_in": "mem_addr",
+                "ce_in": "ce_in",
+                "rd_out": "mem_dout",
+                "we_in": "we_in",
+                "w_mask_in": "mem_wmask",
+                "wd_in": "mem_din"
+            }
+        if type == "dp":
+            return {
+                "clk": "wr_clk",
+                "addr_in_A": "wr_mem_addr",
+                "addr_in_B": "rd_mem_addr",
+                "ce_in": "wr_ce_in | rd_ce_in",
+                "rd_out_A": "",
+                "rd_out_B": "mem_dout",
+                "we_in_A": "we_in",
+                "we_in_B": "1'b0",
+                "w_mask_in_A": "mem_wmask",
+                "w_mask_in_B": "'b0",
+                "wd_in_A": "mem_din",
+                "wd_in_B": "'b0"
+            }
+        if type == "tdp":
+            return {
+                "clk_A": "clk_a",
+                "clk_B": "clk_b",
+                "addr_in_A": "mem_addrA",
+                "addr_in_B": "mem_addrB",
+                "ce_in_A": "ce_in_A",
+                "ce_in_B": "ce_in_B",
+                "rd_out_A": "mem_doutA",
+                "rd_out_B": "mem_doutB",
+                "we_in_A": "we_in_A",
+                "we_in_B": "we_in_B",
+                "w_mask_in_A": "mem_wmaskA",
+                "w_mask_in_B": "mem_wmaskB",
+                "wd_in_A": "mem_dinA",
+                "wd_in_B": "mem_dinB"
+            }
+
+    def get_ram_libcell(self) -> str:
+        """Returns the name of the RAM library cell.
+
+        Returns:
+            str: The name of the RAM library cell.
+        """
+        return self.name
+
 
 class FakeRAM7_tdp_64x32(_FakeRAM7Library):
     def __init__(self):
@@ -246,12 +337,12 @@ class FakeRAM7_sp_8192x32(_FakeRAM7Library):
 
 class FakeRAM7_tdp_8192x64(_FakeRAM7Library):
     def __init__(self):
-        super().__init__("dp_8192x64")
+        super().__init__("tdp_8192x64")
 
 
 class FakeRAM7_dp_8192x64(_FakeRAM7Library):
     def __init__(self):
-        super().__init__("tdp_8192x64")
+        super().__init__("dp_8192x64")
 
 
 class FakeRAM7_sp_8192x64(_FakeRAM7Library):
@@ -350,3 +441,33 @@ class FakeRAM7Lambdalib_TrueDoublePort(LambalibTechLibrary, _LambdaPath):
             with self.active_fileset("rtl"):
                 self.add_file(lib_path / "lambda" / "la_tdpram.v")
                 self.add_depfileset(Tdpram(), "rtl.impl")
+
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser()
+    parser.add_argument('--verible_bin',
+                        metavar='<verible>',
+                        required=True,
+                        help='path to verible-verilog-format')
+    args = parser.parse_args()
+
+    files = []
+
+    spram = Spram()
+    files.append(os.path.join(os.path.dirname(__file__), "fakeram7", "lambda", f"{spram.name}.v"))
+    spram.write_lambdalib(
+        files[-1],
+        FakeRAM7Lambdalib_SinglePort().techlibs)
+    dpram = Dpram()
+    files.append(os.path.join(os.path.dirname(__file__), "fakeram7", "lambda", f"{dpram.name}.v"))
+    dpram.write_lambdalib(
+        files[-1],
+        FakeRAM7Lambdalib_DoublePort().techlibs)
+    tdpram = Tdpram()
+    files.append(os.path.join(os.path.dirname(__file__), "fakeram7", "lambda", f"{tdpram.name}.v"))
+    tdpram.write_lambdalib(
+        files[-1],
+        FakeRAM7Lambdalib_TrueDoublePort().techlibs)
+
+    for f in files:
+        format_verilog(f, args.verible_bin)

{lambdapdk-0.2.6 → lambdapdk-0.2.7}/lambdapdk/freepdk45/libs/fakeram45.py

@@ -1,12 +1,20 @@
+import argparse
+import math
+
+import os.path
+
 from pathlib import Path
 
+from typing import Dict, Tuple
+
 from lambdalib import LambalibTechLibrary
 from lambdapdk import LambdaLibrary, _LambdaPath
-from lambdalib.ramlib import Spram
+from lambdalib.ramlib import Spram, RAMTechLib
 from lambdapdk.freepdk45 import FreePDK45PDK
+from lambdapdk.utils import format_verilog
 
 
-class _FakeRAM45Library(LambdaLibrary):
+class _FakeRAM45Library(LambdaLibrary, RAMTechLib):
     def __init__(self, config):
         super().__init__()
         self.set_name(f"fakeram45_{config}")
@@ -33,6 +41,55 @@ class _FakeRAM45Library(LambdaLibrary):
 
             self.add_klayout_allowmissingcell(self.name)
 
+    def __ram_props(self) -> Tuple[int, int]:
+        """Returns the RAM properties (width, depth) based on the configuration."""
+        size = self.name.split('_')[-1]
+        width = int(size.split('x')[1])
+        depth = int(size.split('x')[0])
+        return width, depth
+
+    def get_ram_width(self) -> int:
+        """Returns the width of the RAM cell.
+
+        Returns:
+            int: The width of the RAM cell.
+        """
+        width, _ = self.__ram_props()
+        return width
+
+    def get_ram_depth(self) -> int:
+        """Returns the depth of the RAM cell.
+
+        Returns:
+            int: The depth of the RAM cell.
+        """
+        _, depth = self.__ram_props()
+        return int(math.log2(depth))
+
+    def get_ram_ports(self) -> Dict[str, str]:
+        """Returns the port mapping for the RAM cell.
+
+        Returns:
+            Dict[str, str]: A dictionary mapping port names to their expressions.
+        """
+        return {
+            "clk": "clk",
+            "addr_in": "mem_addr",
+            "ce_in": "ce_in",
+            "rd_out": "mem_dout",
+            "we_in": "we_in",
+            "w_mask_in": "mem_wmask",
+            "wd_in": "mem_din"
+        }
+
+    def get_ram_libcell(self) -> str:
+        """Returns the name of the RAM library cell.
+
+        Returns:
+            str: The name of the RAM library cell.
+        """
+        return self.name
+
 
 class FakeRAM45_64x32(_FakeRAM45Library):
     def __init__(self):
@@ -84,3 +141,23 @@ class FakeRAM45Lambdalib_SinglePort(LambalibTechLibrary, _LambdaPath):
             with self.active_fileset("rtl"):
                 self.add_file(lib_path / "lambda" / "la_spram.v")
                 self.add_depfileset(Spram(), "rtl.impl")
+
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser()
+    parser.add_argument('--verible_bin',
+                        metavar='<verible>',
+                        required=True,
+                        help='path to verible-verilog-format')
+    args = parser.parse_args()
+
+    files = []
+
+    spram = Spram()
+    files.append(os.path.join(os.path.dirname(__file__), "fakeram45", "lambda", f"{spram.name}.v"))
+    spram.write_lambdalib(
+        files[-1],
+        FakeRAM45Lambdalib_SinglePort().techlibs)
+
+    for f in files:
+        format_verilog(f, args.verible_bin)

{lambdapdk-0.2.6 → lambdapdk-0.2.7}/lambdapdk/gf180/libs/gf180sram.py

@@ -1,8 +1,15 @@
+import argparse
+import math
+
+import os.path
+
 from pathlib import Path
 
+from typing import Dict, Tuple
+
 from lambdalib import LambalibTechLibrary
 from lambdapdk import LambdaLibrary, _LambdaPath
-from lambdalib.ramlib import Spram
+from lambdalib.ramlib import Spram, RAMTechLib
 from lambdapdk.gf180 import GF180_3LM_1TM_6K_7t, \
     GF180_3LM_1TM_6K_9t, \
     GF180_3LM_1TM_9K_7t, \
@@ -25,9 +32,10 @@ from lambdapdk.gf180 import GF180_3LM_1TM_6K_7t, \
     GF180_5LM_1TM_11K_9t, \
     GF180_6LM_1TM_9K_7t, \
     GF180_6LM_1TM_9K_9t
+from lambdapdk.utils import format_verilog
 
 
-class _GF180SRAMLibrary(LambdaLibrary):
+class _GF180SRAMLibrary(LambdaLibrary, RAMTechLib):
     def __init__(self, config):
         super().__init__()
         self.set_name(f"gf180mcu_fd_ip_sram__sram{config}m8wm1")
@@ -84,6 +92,55 @@ class _GF180SRAMLibrary(LambdaLibrary):
             with self.active_fileset("openroad.globalconnect"):
                 self.add_file(path_base / "apr" / "openroad" / "global_connect.tcl")
 
+    def __ram_props(self) -> Tuple[int, int]:
+        """Returns the RAM properties (width, depth) based on the configuration."""
+        size = self.name.split('_')[-1][4:-5]
+        width = int(size.split('x')[1])
+        depth = int(size.split('x')[0])
+        return width, depth
+
+    def get_ram_width(self) -> int:
+        """Returns the width of the RAM cell.
+
+        Returns:
+            int: The width of the RAM cell.
+        """
+        width, _ = self.__ram_props()
+        return width
+
+    def get_ram_depth(self) -> int:
+        """Returns the depth of the RAM cell.
+
+        Returns:
+            int: The depth of the RAM cell.
+        """
+        _, depth = self.__ram_props()
+        return int(math.log2(depth))
+
+    def get_ram_ports(self) -> Dict[str, str]:
+        """Returns the port mapping for the RAM cell.
+
+        Returns:
+            Dict[str, str]: A dictionary mapping port names to their expressions.
+        """
+        return {
+            "CLK": "clk",
+            "CEN": "~ce_in",
+            "GWEN": "~we_in",
+            "WEN": "~mem_wmask",
+            "A": "mem_addr",
+            "D": "mem_din",
+            "Q": "mem_dout"
+        }
+
+    def get_ram_libcell(self) -> str:
+        """Returns the name of the RAM library cell.
+
+        Returns:
+            str: The name of the RAM library cell.
+        """
+        return self.name
+
 
 class GF180_SRAM_64x8(_GF180SRAMLibrary):
     def __init__(self):
@@ -123,3 +180,24 @@ class GF180Lambdalib_SinglePort(LambalibTechLibrary, _LambdaPath):
             with self.active_fileset("rtl"):
                 self.add_file(lib_path / "lambda" / "la_spram.v")
                 self.add_depfileset(Spram(), "rtl.impl")
+
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser()
+    parser.add_argument('--verible_bin',
+                        metavar='<verible>',
+                        required=True,
+                        help='path to verible-verilog-format')
+    args = parser.parse_args()
+
+    files = []
+
+    spram = Spram()
+    files.append(os.path.join(os.path.dirname(__file__), "gf180mcu_fd_ip_sram",
+                              "lambda", f"{spram.name}.v"))
+    spram.write_lambdalib(
+        files[-1],
+        GF180Lambdalib_SinglePort().techlibs)
+
+    for f in files:
+        format_verilog(f, args.verible_bin)

{lambdapdk-0.2.6 → lambdapdk-0.2.7}/lambdapdk/ihp130/__init__.py

@@ -3,7 +3,7 @@ from pathlib import Path
 from lambdapdk import LambdaPDK, _LambdaPath
 
 
-pdk_rev = '62c1d640dc1c91f57bc1a8e4e08e537a7a105ae8'
+pdk_rev = 'd490cfb2e3258f71f362167e74e1fcfc55381ab4'
 
 
 class _IHP130Path(_LambdaPath):
@@ -100,8 +100,7 @@ class IHP130PDK(LambdaPDK, _IHP130Path):
 
         # DRC
         drcs = {
-            "maximal": 'ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_maximal.lydrc',
-            "minimal": 'ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_minimal.lydrc'
+            "drc": 'ihp-sg13g2/libs.tech/klayout/tech/drc/ihp-sg13g2.drc',
         }
         with self.active_dataroot("ihp130"):
             for drc, runset in drcs.items():
@@ -109,6 +108,6 @@ class IHP130PDK(LambdaPDK, _IHP130Path):
                     self.add_file(runset, filetype="drc")
                     self.add_runsetfileset("drc", "klayout", drc)
 
-                self.add_klayout_drcparam(drc, "in_gds=<input>")
-                self.add_klayout_drcparam(drc, "cell=<topcell>")
-                self.add_klayout_drcparam(drc, "report_file=<report>")
+                self.add_klayout_drcparam(drc, "input=<input>")
+                self.add_klayout_drcparam(drc, "topcell=<topcell>")
+                self.add_klayout_drcparam(drc, "report=<report>")

{lambdapdk-0.2.6 → lambdapdk-0.2.7}/lambdapdk/ihp130/libs/sg13g2_sram.py

@@ -1,12 +1,20 @@
+import argparse
+import math
+
+import os.path
+
 from pathlib import Path
 
+from typing import Dict, Tuple
+
 from lambdalib import LambalibTechLibrary
 from lambdapdk import LambdaLibrary, _LambdaPath
-from lambdalib.ramlib import Spram
+from lambdalib.ramlib import Spram, RAMTechLib
 from lambdapdk.ihp130 import IHP130PDK, _IHP130Path
+from lambdapdk.utils import format_verilog
 
 
-class _IHP130SRAMLibrary(LambdaLibrary, _IHP130Path):
+class _IHP130SRAMLibrary(LambdaLibrary, _IHP130Path, RAMTechLib):
     def __init__(self, config):
         super().__init__()
         self.set_name(f'RM_IHPSG13_1P_{config}_c2_bm_bist')
@@ -46,6 +54,65 @@ class _IHP130SRAMLibrary(LambdaLibrary, _IHP130Path):
                 self.add_file(path_base / "apr" / "openroad" / "global_connect.tcl")
                 self.add_openroad_globalconnectfileset()
 
+    def __ram_props(self) -> Tuple[int, int]:
+        """Returns the RAM properties (width, depth) based on the configuration."""
+        size = self.name.split('_')[3]
+        width = int(size.split('x')[1])
+        depth = int(size.split('x')[0])
+        return width, depth
+
+    def get_ram_width(self) -> int:
+        """Returns the width of the RAM cell.
+
+        Returns:
+            int: The width of the RAM cell.
+        """
+        width, _ = self.__ram_props()
+        return width
+
+    def get_ram_depth(self) -> int:
+        """Returns the depth of the RAM cell.
+
+        Returns:
+            int: The depth of the RAM cell.
+        """
+        _, depth = self.__ram_props()
+        return int(math.log2(depth))
+
+    def get_ram_ports(self) -> Dict[str, str]:
+        """Returns the port mapping for the RAM cell.
+
+        Returns:
+            Dict[str, str]: A dictionary mapping port names to their expressions.
+        """
+        return {
+            "A_CLK": "clk",
+            "A_MEN": "~ce_in",
+            "A_WEN": "~we_in",
+            "A_REN": "we_in",
+            "A_ADDR": "mem_addr",
+            "A_DIN": "mem_din",
+            "A_DLY": "1'b1",
+            "A_DOUT": "mem_dout",
+            "A_BM": "mem_wmask",
+            "A_BIST_CLK": "1'b0",
+            "A_BIST_EN": "1'b0",
+            "A_BIST_MEN": "1'b0",
+            "A_BIST_WEN": "1'b0",
+            "A_BIST_REN": "1'b0",
+            "A_BIST_ADDR": "'b0",
+            "A_BIST_DIN": "'b0",
+            "A_BIST_BM": "'b0"
+        }
+
+    def get_ram_libcell(self) -> str:
+        """Returns the name of the RAM library cell.
+
+        Returns:
+            str: The name of the RAM library cell.
+        """
+        return self.name
+
 
 class IHP130_SRAM_1024x64(_IHP130SRAMLibrary):
     def __init__(self):
@@ -97,3 +164,24 @@ class IHP130Lambdalib_SinglePort(LambalibTechLibrary, _LambdaPath):
             with self.active_fileset("rtl"):
                 self.add_file(lib_path / "lambda" / "la_spram.v")
                 self.add_depfileset(Spram(), "rtl.impl")
+
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser()
+    parser.add_argument('--verible_bin',
+                        metavar='<verible>',
+                        required=True,
+                        help='path to verible-verilog-format')
+    args = parser.parse_args()
+
+    files = []
+
+    spram = Spram()
+    files.append(os.path.join(os.path.dirname(__file__), "sg13g2_sram",
+                              "lambda", f"{spram.name}.v"))
+    spram.write_lambdalib(
+        files[-1],
+        IHP130Lambdalib_SinglePort().techlibs)
+
+    for f in files:
+        format_verilog(f, args.verible_bin)

lambdapdk-0.2.7/lambdapdk/sky130/libs/sky130sram.py

@@ -0,0 +1,141 @@
+import argparse
+import math
+
+import os.path
+
+from pathlib import Path
+
+from typing import Dict, Tuple
+
+from lambdalib import LambalibTechLibrary
+from lambdapdk import LambdaLibrary, _LambdaPath
+from lambdalib.ramlib import Spram, RAMTechLib
+from lambdapdk.sky130 import Sky130PDK
+from lambdapdk.utils import format_verilog
+
+
+class Sky130_SRAM_64x256(LambdaLibrary, RAMTechLib):
+    def __init__(self):
+        super().__init__()
+        self.set_name('sky130_sram_1rw1r_64x256_8')
+
+        self.add_asic_pdk(Sky130PDK())
+
+        path_base = Path('lambdapdk', 'sky130', 'libs', "sky130sram")
+
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("models.timing.nldm"):
+                self.add_file(path_base / self.name / "nldm" / f"{self.name}_TT_1p8V_25C.lib")
+                self.add_asic_libcornerfileset("generic", "nldm")
+
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("models.physical"):
+                self.add_file(path_base / self.name / "lef" / f"{self.name}.lef.gz")
+                self.add_file(path_base / self.name / "gds" / f"{self.name}.gds")
+                self.add_asic_aprfileset()
+
+            with self.active_fileset("models.lvs"):
+                self.add_file(path_base / self.name / "spice" / f"{self.name}.lvs.sp",
+                              filetype="cdl")
+                self.add_asic_aprfileset()
+
+            with self.active_fileset("models.spice"):
+                self.add_file(path_base / self.name / "spice" / f"{self.name}.sp")
+
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("openroad.powergrid"):
+                self.add_file(path_base / "apr" / "openroad" / "pdngen.tcl")
+                self.add_openroad_powergridfileset()
+            with self.active_fileset("openroad.globalconnect"):
+                self.add_file(path_base / "apr" / "openroad" / "global_connect.tcl")
+                self.add_openroad_globalconnectfileset()
+
+    def __ram_props(self) -> Tuple[int, int]:
+        """Returns the RAM properties (width, depth) based on the configuration."""
+        size = self.name.split('_')[-2]
+        depth = int(size.split('x')[1])
+        width = int(size.split('x')[0])
+        return width, depth
+
+    def get_ram_width(self) -> int:
+        """Returns the width of the RAM cell.
+
+        Returns:
+            int: The width of the RAM cell.
+        """
+        width, _ = self.__ram_props()
+        return width
+
+    def get_ram_depth(self) -> int:
+        """Returns the depth of the RAM cell.
+
+        Returns:
+            int: The depth of the RAM cell.
+        """
+        _, depth = self.__ram_props()
+        return int(math.log2(depth))
+
+    def get_ram_ports(self) -> Dict[str, str]:
+        """Returns the port mapping for the RAM cell.
+
+        Returns:
+            Dict[str, str]: A dictionary mapping port names to their expressions.
+        """
+        return {
+            "clk0": "clk",
+            "csb0": "ce_in && we_in",
+            "web0": "ce_in && we_in",
+            "wmask0": "{mem_wmask[24], mem_wmask[16], mem_wmask[8], mem_wmask[0]}",
+            "addr0": "mem_addr",
+            "din0": "mem_din",
+            "dout0": "",
+            "clk1": "clk",
+            "csb1": "ce_in && ~we_in",
+            "addr1": "mem_addr",
+            "dout1": "mem_dout",
+        }
+
+    def get_ram_libcell(self) -> str:
+        """Returns the name of the RAM library cell.
+
+        Returns:
+            str: The name of the RAM library cell.
+        """
+        return self.name
+
+
+class Sky130Lambdalib_SinglePort(LambalibTechLibrary, _LambdaPath):
+    def __init__(self):
+        super().__init__("la_spram", [
+            Sky130_SRAM_64x256])
+        self.set_name("sky130_la_spram")
+
+        # version
+        self.package.set_version("v1")
+
+        lib_path = Path("lambdapdk", "sky130", "libs", "sky130sram")
+
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("rtl"):
+                self.add_file(lib_path / "lambda" / "la_spram.v")
+                self.add_depfileset(Spram(), "rtl.impl")
+
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser()
+    parser.add_argument('--verible_bin',
+                        metavar='<verible>',
+                        required=True,
+                        help='path to verible-verilog-format')
+    args = parser.parse_args()
+
+    files = []
+
+    spram = Spram()
+    files.append(os.path.join(os.path.dirname(__file__), "sky130sram", "lambda", f"{spram.name}.v"))
+    spram.write_lambdalib(
+        files[-1],
+        Sky130Lambdalib_SinglePort().techlibs)
+
+    for f in files:
+        format_verilog(f, args.verible_bin)

lambdapdk-0.2.7/lambdapdk/utils.py

@@ -0,0 +1,16 @@
+import subprocess
+import os.path
+import glob
+
+
+def format_verilog(path: str, verible_bin: str):
+    """Format Verilog files using Verible."""
+    if os.path.isfile(path):
+        paths = [os.path.abspath(path)]
+    elif os.path.isdir(path):
+        paths = glob.glob(os.path.join(path, '*.v'))
+        paths.extend(glob.glob(os.path.join(path, '*.vh')))
+
+    for f in paths:
+        print(f"Formatting: {f}")
+        subprocess.run([verible_bin, '--inplace', f])

{lambdapdk-0.2.6 → lambdapdk-0.2.7/lambdapdk.egg-info}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: lambdapdk
-Version: 0.2.6
+Version: 0.2.7
 Summary: Library of open source Process Design Kits
 Author: Zero ASIC
 License:                                  Apache License
@@ -199,12 +199,12 @@ Requires-Python: >=3.8
 Description-Content-Type: text/markdown
 License-File: LICENSE
 Requires-Dist: siliconcompiler>=0.35.0
-Requires-Dist: lambdalib>=0.5.0
+Requires-Dist: lambdalib>=0.7.0
 Provides-Extra: test
 Requires-Dist: flake8==7.3.0; extra == "test"
-Requires-Dist: pytest==8.4.2; extra == "test"
+Requires-Dist: pytest==9.0.2; extra == "test"
 Requires-Dist: pytest-timeout==2.4.0; extra == "test"
-Requires-Dist: tclint==0.6.2; extra == "test"
+Requires-Dist: tclint==0.7.0; extra == "test"
 Requires-Dist: sc-leflib==0.5.1; extra == "test"
 Requires-Dist: Jinja2==3.1.6; extra == "test"
 Dynamic: license-file

{lambdapdk-0.2.6 → lambdapdk-0.2.7}/lambdapdk.egg-info/SOURCES.txt

@@ -3,6 +3,7 @@ MANIFEST.in
 README.md
 pyproject.toml
 lambdapdk/__init__.py
+lambdapdk/utils.py
 lambdapdk.egg-info/PKG-INFO
 lambdapdk.egg-info/SOURCES.txt
 lambdapdk.egg-info/dependency_links.txt

{lambdapdk-0.2.6 → lambdapdk-0.2.7}/lambdapdk.egg-info/requires.txt

@@ -1,10 +1,10 @@
 siliconcompiler>=0.35.0
-lambdalib>=0.5.0
+lambdalib>=0.7.0
 
 [test]
 flake8==7.3.0
-pytest==8.4.2
+pytest==9.0.2
 pytest-timeout==2.4.0
-tclint==0.6.2
+tclint==0.7.0
 sc-leflib==0.5.1
 Jinja2==3.1.6

{lambdapdk-0.2.6 → lambdapdk-0.2.7}/pyproject.toml

@@ -14,7 +14,7 @@ requires-python = ">= 3.8"
 license = {file = "LICENSE"}
 dependencies = [
     "siliconcompiler >= 0.35.0",
-    "lambdalib >= 0.5.0"
+    "lambdalib >= 0.7.0"
 ]
 dynamic = ['version']
 
@@ -32,9 +32,9 @@ timeout = "180"
 # Test dependencies.
 test = [
     "flake8 == 7.3.0",
-    "pytest == 8.4.2",
+    "pytest == 9.0.2",
     "pytest-timeout == 2.4.0",
-    "tclint == 0.6.2",
+    "tclint == 0.7.0",
     "sc-leflib == 0.5.1",
     "Jinja2 == 3.1.6"
 ]

lambdapdk-0.2.6/lambdapdk/sky130/libs/sky130sram.py

@@ -1,60 +0,0 @@
-from pathlib import Path
-
-from lambdalib import LambalibTechLibrary
-from lambdapdk import LambdaLibrary, _LambdaPath
-from lambdalib.ramlib import Spram
-from lambdapdk.sky130 import Sky130PDK
-
-
-class Sky130_SRAM_64x256(LambdaLibrary):
-    def __init__(self):
-        super().__init__()
-        self.set_name('sky130_sram_1rw1r_64x256_8')
-
-        self.add_asic_pdk(Sky130PDK())
-
-        path_base = Path('lambdapdk', 'sky130', 'libs', "sky130sram")
-
-        with self.active_dataroot("lambdapdk"):
-            with self.active_fileset("models.timing.nldm"):
-                self.add_file(path_base / self.name / "nldm" / f"{self.name}_TT_1p8V_25C.lib")
-                self.add_asic_libcornerfileset("generic", "nldm")
-
-        with self.active_dataroot("lambdapdk"):
-            with self.active_fileset("models.physical"):
-                self.add_file(path_base / self.name / "lef" / f"{self.name}.lef.gz")
-                self.add_file(path_base / self.name / "gds" / f"{self.name}.gds")
-                self.add_asic_aprfileset()
-
-            with self.active_fileset("models.lvs"):
-                self.add_file(path_base / self.name / "spice" / f"{self.name}.lvs.sp",
-                              filetype="cdl")
-                self.add_asic_aprfileset()
-
-            with self.active_fileset("models.spice"):
-                self.add_file(path_base / self.name / "spice" / f"{self.name}.sp")
-
-        with self.active_dataroot("lambdapdk"):
-            with self.active_fileset("openroad.powergrid"):
-                self.add_file(path_base / "apr" / "openroad" / "pdngen.tcl")
-                self.add_openroad_powergridfileset()
-            with self.active_fileset("openroad.globalconnect"):
-                self.add_file(path_base / "apr" / "openroad" / "global_connect.tcl")
-                self.add_openroad_globalconnectfileset()
-
-
-class Sky130Lambdalib_SinglePort(LambalibTechLibrary, _LambdaPath):
-    def __init__(self):
-        super().__init__("la_spram", [
-            Sky130_SRAM_64x256])
-        self.set_name("sky130_la_spram")
-
-        # version
-        self.package.set_version("v1")
-
-        lib_path = Path("lambdapdk", "sky130", "libs", "sky130sram")
-
-        with self.active_dataroot("lambdapdk"):
-            with self.active_fileset("rtl"):
-                self.add_file(lib_path / "lambda" / "la_spram.v")
-                self.add_depfileset(Spram(), "rtl.impl")