lambdapdk 0.2.1__tar.gz → 0.2.2__tar.gz

{lambdapdk-0.2.1/lambdapdk.egg-info → lambdapdk-0.2.2}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: lambdapdk
-Version: 0.2.1
+Version: 0.2.2
 Summary: Library of open source Process Design Kits
 Author: Zero ASIC
 License:                                  Apache License
@@ -199,7 +199,7 @@ Requires-Python: >=3.8
 Description-Content-Type: text/markdown
 License-File: LICENSE
 Requires-Dist: siliconcompiler>=0.35.0
-Requires-Dist: lambdalib>=0.4.0
+Requires-Dist: lambdalib>=0.5.0
 Provides-Extra: test
 Requires-Dist: flake8==7.3.0; extra == "test"
 Requires-Dist: pytest==8.4.2; extra == "test"

{lambdapdk-0.2.1 → lambdapdk-0.2.2}/lambdapdk/__init__.py

@@ -11,7 +11,7 @@ from siliconcompiler.tools.openroad import OpenROADStdCellLibrary
 from siliconcompiler.tools.bambu import BambuStdCellLibrary
 from siliconcompiler.tools.klayout import KLayoutLibrary
 
-__version__ = "0.2.1"
+__version__ = "0.2.2"
 
 
 class _LambdaPath(PathSchema):
@@ -158,35 +158,35 @@ def get_libs():
         FakeIO7Lambdalib_la_iobidir
     from lambdapdk.asap7.libs.fakekit7 import FakeKit7Library
     from lambdapdk.asap7.libs.fakeram7 import \
-        FakeRAM7_dp_64x32, \
+        FakeRAM7_dp_64x32, FakeRAM7_tdp_64x32, \
         FakeRAM7_sp_64x32, \
-        FakeRAM7_dp_128x32, \
+        FakeRAM7_dp_128x32, FakeRAM7_tdp_128x32, \
         FakeRAM7_sp_128x32, \
-        FakeRAM7_dp_256x32, \
+        FakeRAM7_dp_256x32, FakeRAM7_tdp_256x32, \
         FakeRAM7_sp_256x32, \
-        FakeRAM7_dp_256x64, \
+        FakeRAM7_dp_256x64, FakeRAM7_tdp_256x64, \
         FakeRAM7_sp_256x64, \
-        FakeRAM7_dp_512x32, \
+        FakeRAM7_dp_512x32, FakeRAM7_tdp_512x32, \
         FakeRAM7_sp_512x32, \
-        FakeRAM7_dp_512x64, \
+        FakeRAM7_dp_512x64, FakeRAM7_tdp_512x64, \
         FakeRAM7_sp_512x64, \
-        FakeRAM7_dp_512x128, \
+        FakeRAM7_dp_512x128, FakeRAM7_tdp_512x128, \
         FakeRAM7_sp_512x128, \
-        FakeRAM7_dp_1024x32, \
+        FakeRAM7_dp_1024x32, FakeRAM7_tdp_1024x32, \
         FakeRAM7_sp_1024x32, \
-        FakeRAM7_dp_1024x64, \
+        FakeRAM7_dp_1024x64, FakeRAM7_tdp_1024x64, \
         FakeRAM7_sp_1024x64, \
-        FakeRAM7_dp_2048x32, \
+        FakeRAM7_dp_2048x32, FakeRAM7_tdp_2048x32, \
         FakeRAM7_sp_2048x32, \
-        FakeRAM7_dp_2048x64, \
+        FakeRAM7_dp_2048x64, FakeRAM7_tdp_2048x64, \
         FakeRAM7_sp_2048x64, \
-        FakeRAM7_dp_4096x32, \
+        FakeRAM7_dp_4096x32, FakeRAM7_tdp_4096x32, \
         FakeRAM7_sp_4096x32, \
-        FakeRAM7_dp_4096x64, \
+        FakeRAM7_dp_4096x64, FakeRAM7_tdp_4096x64, \
         FakeRAM7_sp_4096x64, \
-        FakeRAM7_dp_8192x32, \
+        FakeRAM7_dp_8192x32, FakeRAM7_tdp_8192x32, \
         FakeRAM7_sp_8192x32, \
-        FakeRAM7_dp_8192x64, \
+        FakeRAM7_dp_8192x64, FakeRAM7_tdp_8192x64, \
         FakeRAM7_sp_8192x64, \
         FakeRAM7Lambdalib_SinglePort, \
         FakeRAM7Lambdalib_DoublePort
@@ -304,35 +304,35 @@ def get_libs():
     return set([
         ASAP7SC7p5RVT(), ASAP7SC7p5SLVT(), ASAP7SC7p5LVT(),
         FakeIO7Library(), FakeKit7Library(),
-        FakeRAM7_dp_64x32(),
+        FakeRAM7_dp_64x32(), FakeRAM7_tdp_64x32(),
         FakeRAM7_sp_64x32(),
-        FakeRAM7_dp_128x32(),
+        FakeRAM7_dp_128x32(), FakeRAM7_tdp_128x32(),
         FakeRAM7_sp_128x32(),
-        FakeRAM7_dp_256x32(),
+        FakeRAM7_dp_256x32(), FakeRAM7_tdp_256x32(),
         FakeRAM7_sp_256x32(),
-        FakeRAM7_dp_256x64(),
+        FakeRAM7_dp_256x64(), FakeRAM7_tdp_256x64(),
         FakeRAM7_sp_256x64(),
-        FakeRAM7_dp_512x32(),
+        FakeRAM7_dp_512x32(), FakeRAM7_tdp_512x32(),
         FakeRAM7_sp_512x32(),
-        FakeRAM7_dp_512x64(),
+        FakeRAM7_dp_512x64(), FakeRAM7_tdp_512x64(),
         FakeRAM7_sp_512x64(),
-        FakeRAM7_dp_512x128(),
+        FakeRAM7_dp_512x128(), FakeRAM7_tdp_512x128(),
         FakeRAM7_sp_512x128(),
-        FakeRAM7_dp_1024x32(),
+        FakeRAM7_dp_1024x32(), FakeRAM7_tdp_1024x32(),
         FakeRAM7_sp_1024x32(),
-        FakeRAM7_dp_1024x64(),
+        FakeRAM7_dp_1024x64(), FakeRAM7_tdp_1024x64(),
         FakeRAM7_sp_1024x64(),
-        FakeRAM7_dp_2048x32(),
+        FakeRAM7_dp_2048x32(), FakeRAM7_tdp_2048x32(),
         FakeRAM7_sp_2048x32(),
-        FakeRAM7_dp_2048x64(),
+        FakeRAM7_dp_2048x64(), FakeRAM7_tdp_2048x64(),
         FakeRAM7_sp_2048x64(),
-        FakeRAM7_dp_4096x32(),
+        FakeRAM7_dp_4096x32(), FakeRAM7_tdp_4096x32(),
         FakeRAM7_sp_4096x32(),
-        FakeRAM7_dp_4096x64(),
+        FakeRAM7_dp_4096x64(), FakeRAM7_tdp_4096x64(),
         FakeRAM7_sp_4096x64(),
-        FakeRAM7_dp_8192x32(),
+        FakeRAM7_dp_8192x32(), FakeRAM7_tdp_8192x32(),
         FakeRAM7_sp_8192x32(),
-        FakeRAM7_dp_8192x64(),
+        FakeRAM7_dp_8192x64(), FakeRAM7_tdp_8192x64(),
         FakeRAM7_sp_8192x64(),
         FakeRAM7Lambdalib_SinglePort(),
         FakeRAM7Lambdalib_DoublePort(),

{lambdapdk-0.2.1 → lambdapdk-0.2.2}/lambdapdk/asap7/libs/fakeram7.py

@@ -2,6 +2,7 @@ from pathlib import Path
 
 from lambdalib import LambalibTechLibrary
 from lambdapdk import LambdaLibrary, _LambdaPath
+from lambdalib.ramlib import Spram, Dpram, Tdpram
 from lambdapdk.asap7 import ASAP7PDK
 
 
@@ -33,6 +34,11 @@ class _FakeRAM7Library(LambdaLibrary):
             self.add_klayout_allowmissingcell(self.name)
 
 
+class FakeRAM7_tdp_64x32(_FakeRAM7Library):
+    def __init__(self):
+        super().__init__("tdp_64x32")
+
+
 class FakeRAM7_dp_64x32(_FakeRAM7Library):
     def __init__(self):
         super().__init__("dp_64x32")
@@ -43,6 +49,11 @@ class FakeRAM7_sp_64x32(_FakeRAM7Library):
         super().__init__("sp_64x32")
 
 
+class FakeRAM7_tdp_128x32(_FakeRAM7Library):
+    def __init__(self):
+        super().__init__("tdp_128x32")
+
+
 class FakeRAM7_dp_128x32(_FakeRAM7Library):
     def __init__(self):
         super().__init__("dp_128x32")
@@ -53,6 +64,11 @@ class FakeRAM7_sp_128x32(_FakeRAM7Library):
         super().__init__("sp_128x32")
 
 
+class FakeRAM7_tdp_256x32(_FakeRAM7Library):
+    def __init__(self):
+        super().__init__("tdp_256x32")
+
+
 class FakeRAM7_dp_256x32(_FakeRAM7Library):
     def __init__(self):
         super().__init__("dp_256x32")
@@ -63,6 +79,11 @@ class FakeRAM7_sp_256x32(_FakeRAM7Library):
         super().__init__("sp_256x32")
 
 
+class FakeRAM7_tdp_256x64(_FakeRAM7Library):
+    def __init__(self):
+        super().__init__("tdp_256x64")
+
+
 class FakeRAM7_dp_256x64(_FakeRAM7Library):
     def __init__(self):
         super().__init__("dp_256x64")
@@ -73,6 +94,11 @@ class FakeRAM7_sp_256x64(_FakeRAM7Library):
         super().__init__("sp_256x64")
 
 
+class FakeRAM7_tdp_512x32(_FakeRAM7Library):
+    def __init__(self):
+        super().__init__("tdp_512x32")
+
+
 class FakeRAM7_dp_512x32(_FakeRAM7Library):
     def __init__(self):
         super().__init__("dp_512x32")
@@ -83,6 +109,11 @@ class FakeRAM7_sp_512x32(_FakeRAM7Library):
         super().__init__("sp_512x32")
 
 
+class FakeRAM7_tdp_512x64(_FakeRAM7Library):
+    def __init__(self):
+        super().__init__("tdp_512x64")
+
+
 class FakeRAM7_dp_512x64(_FakeRAM7Library):
     def __init__(self):
         super().__init__("dp_512x64")
@@ -93,6 +124,11 @@ class FakeRAM7_sp_512x64(_FakeRAM7Library):
         super().__init__("sp_512x64")
 
 
+class FakeRAM7_tdp_512x128(_FakeRAM7Library):
+    def __init__(self):
+        super().__init__("tdp_512x128")
+
+
 class FakeRAM7_dp_512x128(_FakeRAM7Library):
     def __init__(self):
         super().__init__("dp_512x128")
@@ -103,6 +139,11 @@ class FakeRAM7_sp_512x128(_FakeRAM7Library):
         super().__init__("sp_512x128")
 
 
+class FakeRAM7_tdp_1024x32(_FakeRAM7Library):
+    def __init__(self):
+        super().__init__("tdp_1024x32")
+
+
 class FakeRAM7_dp_1024x32(_FakeRAM7Library):
     def __init__(self):
         super().__init__("dp_1024x32")
@@ -113,6 +154,11 @@ class FakeRAM7_sp_1024x32(_FakeRAM7Library):
         super().__init__("sp_1024x32")
 
 
+class FakeRAM7_tdp_1024x64(_FakeRAM7Library):
+    def __init__(self):
+        super().__init__("tdp_1024x64")
+
+
 class FakeRAM7_dp_1024x64(_FakeRAM7Library):
     def __init__(self):
         super().__init__("dp_1024x64")
@@ -123,6 +169,11 @@ class FakeRAM7_sp_1024x64(_FakeRAM7Library):
         super().__init__("sp_1024x64")
 
 
+class FakeRAM7_tdp_2048x32(_FakeRAM7Library):
+    def __init__(self):
+        super().__init__("tdp_2048x32")
+
+
 class FakeRAM7_dp_2048x32(_FakeRAM7Library):
     def __init__(self):
         super().__init__("dp_2048x32")
@@ -133,6 +184,11 @@ class FakeRAM7_sp_2048x32(_FakeRAM7Library):
         super().__init__("sp_2048x32")
 
 
+class FakeRAM7_tdp_2048x64(_FakeRAM7Library):
+    def __init__(self):
+        super().__init__("tdp_2048x64")
+
+
 class FakeRAM7_dp_2048x64(_FakeRAM7Library):
     def __init__(self):
         super().__init__("dp_2048x64")
@@ -143,6 +199,11 @@ class FakeRAM7_sp_2048x64(_FakeRAM7Library):
         super().__init__("sp_2048x64")
 
 
+class FakeRAM7_tdp_4096x32(_FakeRAM7Library):
+    def __init__(self):
+        super().__init__("tdp_4096x32")
+
+
 class FakeRAM7_dp_4096x32(_FakeRAM7Library):
     def __init__(self):
         super().__init__("dp_4096x32")
@@ -153,6 +214,11 @@ class FakeRAM7_sp_4096x32(_FakeRAM7Library):
         super().__init__("sp_4096x32")
 
 
+class FakeRAM7_tdp_4096x64(_FakeRAM7Library):
+    def __init__(self):
+        super().__init__("tdp_4096x64")
+
+
 class FakeRAM7_dp_4096x64(_FakeRAM7Library):
     def __init__(self):
         super().__init__("dp_4096x64")
@@ -163,6 +229,11 @@ class FakeRAM7_sp_4096x64(_FakeRAM7Library):
         super().__init__("sp_4096x64")
 
 
+class FakeRAM7_tdp_8192x32(_FakeRAM7Library):
+    def __init__(self):
+        super().__init__("tdp_8192x32")
+
+
 class FakeRAM7_dp_8192x32(_FakeRAM7Library):
     def __init__(self):
         super().__init__("dp_8192x32")
@@ -173,11 +244,16 @@ class FakeRAM7_sp_8192x32(_FakeRAM7Library):
         super().__init__("sp_8192x32")
 
 
-class FakeRAM7_dp_8192x64(_FakeRAM7Library):
+class FakeRAM7_tdp_8192x64(_FakeRAM7Library):
     def __init__(self):
         super().__init__("dp_8192x64")
 
 
+class FakeRAM7_dp_8192x64(_FakeRAM7Library):
+    def __init__(self):
+        super().__init__("tdp_8192x64")
+
+
 class FakeRAM7_sp_8192x64(_FakeRAM7Library):
     def __init__(self):
         super().__init__("sp_8192x64")
@@ -211,6 +287,7 @@ class FakeRAM7Lambdalib_SinglePort(LambalibTechLibrary, _LambdaPath):
         with self.active_dataroot("lambdapdk"):
             with self.active_fileset("rtl"):
                 self.add_file(lib_path / "lambda" / "la_spram.v")
+                self.add_depfileset(Spram(), "rtl.impl")
 
 
 class FakeRAM7Lambdalib_DoublePort(LambalibTechLibrary, _LambdaPath):
@@ -241,3 +318,35 @@ class FakeRAM7Lambdalib_DoublePort(LambalibTechLibrary, _LambdaPath):
         with self.active_dataroot("lambdapdk"):
             with self.active_fileset("rtl"):
                 self.add_file(lib_path / "lambda" / "la_dpram.v")
+                self.add_depfileset(Dpram(), "rtl.impl")
+
+
+class FakeRAM7Lambdalib_TrueDoublePort(LambalibTechLibrary, _LambdaPath):
+    def __init__(self):
+        super().__init__("la_tdpram", [
+            FakeRAM7_tdp_64x32,
+            FakeRAM7_tdp_128x32,
+            FakeRAM7_tdp_256x32,
+            FakeRAM7_tdp_256x64,
+            FakeRAM7_tdp_512x32,
+            FakeRAM7_tdp_512x64,
+            FakeRAM7_tdp_512x128,
+            FakeRAM7_tdp_1024x32,
+            FakeRAM7_tdp_1024x64,
+            FakeRAM7_tdp_2048x32,
+            FakeRAM7_tdp_2048x64,
+            FakeRAM7_tdp_4096x32,
+            FakeRAM7_tdp_4096x64,
+            FakeRAM7_tdp_8192x32,
+            FakeRAM7_tdp_8192x64])
+        self.set_name("fakeram7_la_tdpram")
+
+        # version
+        self.package.set_version("v1")
+
+        lib_path = Path("lambdapdk", "asap7", "libs", "fakeram7")
+
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("rtl"):
+                self.add_file(lib_path / "lambda" / "la_tdpram.v")
+                self.add_depfileset(Tdpram(), "rtl.impl")

{lambdapdk-0.2.1 → lambdapdk-0.2.2}/lambdapdk/freepdk45/libs/fakeram45.py

@@ -2,6 +2,7 @@ from pathlib import Path
 
 from lambdalib import LambalibTechLibrary
 from lambdapdk import LambdaLibrary, _LambdaPath
+from lambdalib.ramlib import Spram
 from lambdapdk.freepdk45 import FreePDK45PDK
 
 
@@ -82,3 +83,4 @@ class FakeRAM45Lambdalib_SinglePort(LambalibTechLibrary, _LambdaPath):
         with self.active_dataroot("lambdapdk"):
             with self.active_fileset("rtl"):
                 self.add_file(lib_path / "lambda" / "la_spram.v")
+                self.add_depfileset(Spram(), "rtl.impl")

{lambdapdk-0.2.1 → lambdapdk-0.2.2}/lambdapdk/gf180/libs/gf180sram.py

@@ -2,6 +2,7 @@ from pathlib import Path
 
 from lambdalib import LambalibTechLibrary
 from lambdapdk import LambdaLibrary, _LambdaPath
+from lambdalib.ramlib import Spram
 from lambdapdk.gf180 import GF180_3LM_1TM_6K_7t, \
     GF180_3LM_1TM_6K_9t, \
     GF180_3LM_1TM_9K_7t, \
@@ -121,3 +122,4 @@ class GF180Lambdalib_SinglePort(LambalibTechLibrary, _LambdaPath):
         with self.active_dataroot("lambdapdk"):
             with self.active_fileset("rtl"):
                 self.add_file(lib_path / "lambda" / "la_spram.v")
+                self.add_depfileset(Spram(), "rtl.impl")

{lambdapdk-0.2.1 → lambdapdk-0.2.2}/lambdapdk/ihp130/__init__.py

@@ -9,7 +9,9 @@ pdk_rev = '62c1d640dc1c91f57bc1a8e4e08e537a7a105ae8'
 class _IHP130Path(_LambdaPath):
     def __init__(self):
         super().__init__()
-        self.set_dataroot("ihp130", "git+https://github.com/IHP-GmbH/IHP-Open-PDK", pdk_rev)
+        self.set_dataroot("ihp130",
+                          f"https://github.com/IHP-GmbH/IHP-Open-PDK/archive/{pdk_rev}.tar.gz",
+                          pdk_rev)
 
 
 class IHP130PDK(LambdaPDK, _IHP130Path):

{lambdapdk-0.2.1 → lambdapdk-0.2.2}/lambdapdk/ihp130/libs/sg13g2_sram.py

@@ -2,6 +2,7 @@ from pathlib import Path
 
 from lambdalib import LambalibTechLibrary
 from lambdapdk import LambdaLibrary, _LambdaPath
+from lambdalib.ramlib import Spram
 from lambdapdk.ihp130 import IHP130PDK, _IHP130Path
 
 
@@ -95,3 +96,4 @@ class IHP130Lambdalib_SinglePort(LambalibTechLibrary, _LambdaPath):
         with self.active_dataroot("lambdapdk"):
             with self.active_fileset("rtl"):
                 self.add_file(lib_path / "lambda" / "la_spram.v")
+                self.add_depfileset(Spram(), "rtl.impl")

{lambdapdk-0.2.1 → lambdapdk-0.2.2}/lambdapdk/sky130/libs/sky130sram.py

@@ -2,6 +2,7 @@ from pathlib import Path
 
 from lambdalib import LambalibTechLibrary
 from lambdapdk import LambdaLibrary, _LambdaPath
+from lambdalib.ramlib import Spram
 from lambdapdk.sky130 import Sky130PDK
 
 
@@ -56,3 +57,4 @@ class Sky130Lambdalib_SinglePort(LambalibTechLibrary, _LambdaPath):
         with self.active_dataroot("lambdapdk"):
             with self.active_fileset("rtl"):
                 self.add_file(lib_path / "lambda" / "la_spram.v")
+                self.add_depfileset(Spram(), "rtl.impl")

{lambdapdk-0.2.1 → lambdapdk-0.2.2/lambdapdk.egg-info}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: lambdapdk
-Version: 0.2.1
+Version: 0.2.2
 Summary: Library of open source Process Design Kits
 Author: Zero ASIC
 License:                                  Apache License
@@ -199,7 +199,7 @@ Requires-Python: >=3.8
 Description-Content-Type: text/markdown
 License-File: LICENSE
 Requires-Dist: siliconcompiler>=0.35.0
-Requires-Dist: lambdalib>=0.4.0
+Requires-Dist: lambdalib>=0.5.0
 Provides-Extra: test
 Requires-Dist: flake8==7.3.0; extra == "test"
 Requires-Dist: pytest==8.4.2; extra == "test"

{lambdapdk-0.2.1 → lambdapdk-0.2.2}/lambdapdk.egg-info/requires.txt

@@ -1,5 +1,5 @@
 siliconcompiler>=0.35.0
-lambdalib>=0.4.0
+lambdalib>=0.5.0
 
 [test]
 flake8==7.3.0

{lambdapdk-0.2.1 → lambdapdk-0.2.2}/pyproject.toml

@@ -14,7 +14,7 @@ requires-python = ">= 3.8"
 license = {file = "LICENSE"}
 dependencies = [
     "siliconcompiler >= 0.35.0",
-    "lambdalib >= 0.4.0"
+    "lambdalib >= 0.5.0"
 ]
 dynamic = ['version']