lambdapdk 0.1.55__tar.gz → 0.2.0rc1__tar.gz

{lambdapdk-0.1.55/lambdapdk.egg-info → lambdapdk-0.2.0rc1}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: lambdapdk
-Version: 0.1.55
+Version: 0.2.0rc1
 Summary: Library of open source Process Design Kits
 Author: Zero ASIC
 License:                                  Apache License
@@ -198,13 +198,13 @@ Project-URL: Homepage, https://github.com/siliconcompiler/lambdapdk
 Requires-Python: >=3.8
 Description-Content-Type: text/markdown
 License-File: LICENSE
-Requires-Dist: siliconcompiler>=0.27.0
+Requires-Dist: siliconcompiler>=0.34.3
+Requires-Dist: lambdalib==0.4.0-rc1
 Provides-Extra: test
-Requires-Dist: flake8==7.2.0; extra == "test"
-Requires-Dist: pytest==8.4.0; extra == "test"
+Requires-Dist: flake8==7.3.0; extra == "test"
+Requires-Dist: pytest==8.4.1; extra == "test"
 Requires-Dist: pytest-timeout==2.4.0; extra == "test"
-Requires-Dist: tclint==0.5.4; extra == "test"
-Requires-Dist: lambdalib==0.3.4; extra == "test"
+Requires-Dist: tclint==0.6.0; extra == "test"
 Requires-Dist: sc-leflib==0.4.0; extra == "test"
 Requires-Dist: Jinja2==3.1.6; extra == "test"
 Dynamic: license-file

lambdapdk-0.2.0rc1/lambdapdk/__init__.py

@@ -0,0 +1,310 @@
+import os.path
+from siliconcompiler.pathschema import PathSchema
+
+from siliconcompiler.package import PythonPathResolver
+
+from siliconcompiler.tools.klayout import KLayoutPDK
+from siliconcompiler.tools.openroad import OpenROADPDK
+
+from siliconcompiler.tools.yosys import YosysStdCellLibrary
+from siliconcompiler.tools.openroad import OpenROADStdCellLibrary
+from siliconcompiler.tools.bambu import BambuStdCellLibrary
+from siliconcompiler.tools.klayout import KLayoutLibrary
+
+__version__ = "0.2.0-rc1"
+
+
+class _LambdaPath(PathSchema):
+    def __init__(self):
+        super().__init__()
+        PythonPathResolver.set_dataroot(
+            self,
+            "lambdapdk",
+            "lambdapdk",
+            "https://github.com/siliconcompiler/lambdapdk/archive/refs/tags/",
+            alternative_ref=f"v{__version__}",
+            python_module_path_append="..")
+
+
+class LambdaPDK(KLayoutPDK, OpenROADPDK, _LambdaPath):
+    def __init__(self):
+        super().__init__()
+
+
+class LambdaLibrary(YosysStdCellLibrary,
+                    OpenROADStdCellLibrary,
+                    KLayoutLibrary,
+                    BambuStdCellLibrary,
+                    _LambdaPath):
+    def __init__(self):
+        super().__init__()
+
+
+def get_pdks():
+    '''
+    Returns a list of pdks in lambdapdk
+    '''
+
+    from lambdapdk.asap7 import ASAP7PDK
+    from lambdapdk.freepdk45 import FreePDK45PDK
+    from lambdapdk.sky130 import Sky130PDK
+    from lambdapdk.gf180 import GF180_3LM_1TM_6K_7t, \
+        GF180_3LM_1TM_6K_9t, \
+        GF180_3LM_1TM_9K_7t, \
+        GF180_3LM_1TM_9K_9t, \
+        GF180_3LM_1TM_11K_7t, \
+        GF180_3LM_1TM_11K_9t, \
+        GF180_3LM_1TM_30K_7t, \
+        GF180_3LM_1TM_30K_9t, \
+        GF180_4LM_1TM_6K_7t, \
+        GF180_4LM_1TM_6K_9t, \
+        GF180_4LM_1TM_9K_7t, \
+        GF180_4LM_1TM_9K_9t, \
+        GF180_4LM_1TM_11K_7t, \
+        GF180_4LM_1TM_11K_9t, \
+        GF180_4LM_1TM_30K_7t, \
+        GF180_4LM_1TM_30K_9t, \
+        GF180_5LM_1TM_9K_7t, \
+        GF180_5LM_1TM_9K_9t, \
+        GF180_5LM_1TM_11K_7t, \
+        GF180_5LM_1TM_11K_9t, \
+        GF180_6LM_1TM_9K_7t, \
+        GF180_6LM_1TM_9K_9t
+    from lambdapdk.ihp130 import IHP130PDK
+    from lambdapdk.interposer import Interposer_3ML_0400, \
+        Interposer_3ML_0800, \
+        Interposer_3ML_2000, \
+        Interposer_3ML_0400_2000, \
+        Interposer_4ML_0400, \
+        Interposer_4ML_0800, \
+        Interposer_4ML_2000, \
+        Interposer_4ML_0400_2000, \
+        Interposer_5ML_0400, \
+        Interposer_5ML_0800, \
+        Interposer_5ML_2000, \
+        Interposer_5ML_0400_2000
+
+    return set([
+        ASAP7PDK(),
+        FreePDK45PDK(),
+        Sky130PDK(),
+        IHP130PDK(),
+        GF180_3LM_1TM_6K_7t(),
+        GF180_3LM_1TM_6K_9t(),
+        GF180_3LM_1TM_9K_7t(),
+        GF180_3LM_1TM_9K_9t(),
+        GF180_3LM_1TM_11K_7t(),
+        GF180_3LM_1TM_11K_9t(),
+        GF180_3LM_1TM_30K_7t(),
+        GF180_3LM_1TM_30K_9t(),
+        GF180_4LM_1TM_6K_7t(),
+        GF180_4LM_1TM_6K_9t(),
+        GF180_4LM_1TM_9K_7t(),
+        GF180_4LM_1TM_9K_9t(),
+        GF180_4LM_1TM_11K_7t(),
+        GF180_4LM_1TM_11K_9t(),
+        GF180_4LM_1TM_30K_7t(),
+        GF180_4LM_1TM_30K_9t(),
+        GF180_5LM_1TM_9K_7t(),
+        GF180_5LM_1TM_9K_9t(),
+        GF180_5LM_1TM_11K_7t(),
+        GF180_5LM_1TM_11K_9t(),
+        GF180_6LM_1TM_9K_7t(),
+        GF180_6LM_1TM_9K_9t(),
+        Interposer_3ML_0400(),
+        Interposer_3ML_0800(),
+        Interposer_3ML_2000(),
+        Interposer_3ML_0400_2000(),
+        Interposer_4ML_0400(),
+        Interposer_4ML_0800(),
+        Interposer_4ML_2000(),
+        Interposer_4ML_0400_2000(),
+        Interposer_5ML_0400(),
+        Interposer_5ML_0800(),
+        Interposer_5ML_2000(),
+        Interposer_5ML_0400_2000()
+    ])
+
+
+def get_pdk_names():
+    '''
+    Returns a list of pdks in lambdapdk
+    '''
+
+    return set([pdk.name for pdk in get_pdks()])
+
+
+def get_libs():
+    '''
+    Returns a list of libraries in lambdapdk
+    '''
+
+    from lambdapdk.asap7.libs.asap7sc7p5t import ASAP7SC7p5RVT, ASAP7SC7p5SLVT, ASAP7SC7p5LVT
+    from lambdapdk.asap7.libs.fakeio7 import FakeIO7Library
+    from lambdapdk.asap7.libs.fakekit7 import FakeKit7Library
+    from lambdapdk.asap7.libs.fakeram7 import \
+        FakeRAM7_dp_64x32, \
+        FakeRAM7_sp_64x32, \
+        FakeRAM7_dp_128x32, \
+        FakeRAM7_sp_128x32, \
+        FakeRAM7_dp_256x32, \
+        FakeRAM7_sp_256x32, \
+        FakeRAM7_dp_256x64, \
+        FakeRAM7_sp_256x64, \
+        FakeRAM7_dp_512x32, \
+        FakeRAM7_sp_512x32, \
+        FakeRAM7_dp_512x64, \
+        FakeRAM7_sp_512x64, \
+        FakeRAM7_dp_512x128, \
+        FakeRAM7_sp_512x128, \
+        FakeRAM7_dp_1024x32, \
+        FakeRAM7_sp_1024x32, \
+        FakeRAM7_dp_1024x64, \
+        FakeRAM7_sp_1024x64, \
+        FakeRAM7_dp_2048x32, \
+        FakeRAM7_sp_2048x32, \
+        FakeRAM7_dp_2048x64, \
+        FakeRAM7_sp_2048x64, \
+        FakeRAM7_dp_4096x32, \
+        FakeRAM7_sp_4096x32, \
+        FakeRAM7_dp_4096x64, \
+        FakeRAM7_sp_4096x64, \
+        FakeRAM7_dp_8192x32, \
+        FakeRAM7_sp_8192x32, \
+        FakeRAM7_dp_8192x64, \
+        FakeRAM7_sp_8192x64, \
+        FakeRAM7Lambdalib_SinglePort, \
+        FakeRAM7Lambdalib_DoublePort
+    from lambdapdk.freepdk45.libs.nangate45 import Nangate45
+    from lambdapdk.freepdk45.libs.fakeram45 import \
+        FakeRAM45_64x32, \
+        FakeRAM45_128x32, \
+        FakeRAM45_256x32, \
+        FakeRAM45_256x64, \
+        FakeRAM45_512x32, \
+        FakeRAM45_512x64, \
+        FakeRAM45Lambdalib_SinglePort
+    from lambdapdk.gf180.libs.gf180io import GF180_IO_3LM, GF180_IO_4LM, GF180_IO_5LM
+    from lambdapdk.gf180.libs.gf180mcu import GF180_MCU_7T_3LMLibrary, \
+        GF180_MCU_7T_4LMLibrary, \
+        GF180_MCU_7T_5LMLibrary, \
+        GF180_MCU_7T_6LMLibrary, \
+        GF180_MCU_9T_3LMLibrary, \
+        GF180_MCU_9T_4LMLibrary, \
+        GF180_MCU_9T_5LMLibrary, \
+        GF180_MCU_9T_6LMLibrary
+    from lambdapdk.gf180.libs.gf180sram import GF180_SRAM_64x8, \
+        GF180_SRAM_128x8, \
+        GF180_SRAM_256x8, \
+        GF180_SRAM_512x8, \
+        GF180Lambdalib_SinglePort
+    from lambdapdk.ihp130.libs.sg13g2_io import IHP130_IO_1p2, IHP130_IO_1p5
+    from lambdapdk.ihp130.libs.sg13g2_sram import \
+        IHP130_SRAM_1024x64, IHP130_SRAM_2048x64, \
+        IHP130_SRAM_256x48, IHP130_SRAM_256x64, \
+        IHP130_SRAM_512x64, IHP130_SRAM_64x64, \
+        IHP130Lambdalib_SinglePort
+    from lambdapdk.ihp130.libs.sg13g2_stdcell import IHP130StdCell_1p2, IHP130StdCell_1p5
+    from lambdapdk.interposer.libs.bumps import BumpLibrary
+    from lambdapdk.sky130.libs.sky130io import Sky130_IOLibrary
+    from lambdapdk.sky130.libs.sky130sc import Sky130_SCHDLibrary, Sky130_SCHDLLLibrary
+    from lambdapdk.sky130.libs.sky130sram import Sky130_SRAM_64x256, Sky130Lambdalib_SinglePort
+
+    return set([
+        ASAP7SC7p5RVT(), ASAP7SC7p5SLVT(), ASAP7SC7p5LVT(),
+        FakeIO7Library(), FakeKit7Library(),
+        FakeRAM7_dp_64x32(),
+        FakeRAM7_sp_64x32(),
+        FakeRAM7_dp_128x32(),
+        FakeRAM7_sp_128x32(),
+        FakeRAM7_dp_256x32(),
+        FakeRAM7_sp_256x32(),
+        FakeRAM7_dp_256x64(),
+        FakeRAM7_sp_256x64(),
+        FakeRAM7_dp_512x32(),
+        FakeRAM7_sp_512x32(),
+        FakeRAM7_dp_512x64(),
+        FakeRAM7_sp_512x64(),
+        FakeRAM7_dp_512x128(),
+        FakeRAM7_sp_512x128(),
+        FakeRAM7_dp_1024x32(),
+        FakeRAM7_sp_1024x32(),
+        FakeRAM7_dp_1024x64(),
+        FakeRAM7_sp_1024x64(),
+        FakeRAM7_dp_2048x32(),
+        FakeRAM7_sp_2048x32(),
+        FakeRAM7_dp_2048x64(),
+        FakeRAM7_sp_2048x64(),
+        FakeRAM7_dp_4096x32(),
+        FakeRAM7_sp_4096x32(),
+        FakeRAM7_dp_4096x64(),
+        FakeRAM7_sp_4096x64(),
+        FakeRAM7_dp_8192x32(),
+        FakeRAM7_sp_8192x32(),
+        FakeRAM7_dp_8192x64(),
+        FakeRAM7_sp_8192x64(),
+        FakeRAM7Lambdalib_SinglePort(),
+        FakeRAM7Lambdalib_DoublePort(),
+        Nangate45(),
+        FakeRAM45_64x32(),
+        FakeRAM45_128x32(),
+        FakeRAM45_256x32(),
+        FakeRAM45_256x64(),
+        FakeRAM45_512x32(),
+        FakeRAM45_512x64(),
+        FakeRAM45Lambdalib_SinglePort(),
+        GF180_IO_3LM(), GF180_IO_4LM(), GF180_IO_5LM(),
+        GF180_MCU_7T_3LMLibrary(),
+        GF180_MCU_7T_4LMLibrary(),
+        GF180_MCU_7T_5LMLibrary(),
+        GF180_MCU_7T_6LMLibrary(),
+        GF180_MCU_9T_3LMLibrary(),
+        GF180_MCU_9T_4LMLibrary(),
+        GF180_MCU_9T_5LMLibrary(),
+        GF180_MCU_9T_6LMLibrary(),
+        GF180_SRAM_64x8(),
+        GF180_SRAM_128x8(),
+        GF180_SRAM_256x8(),
+        GF180_SRAM_512x8(),
+        GF180Lambdalib_SinglePort(),
+        IHP130_IO_1p2(), IHP130_IO_1p5(),
+        IHP130_SRAM_1024x64(), IHP130_SRAM_2048x64(),
+        IHP130_SRAM_256x48(), IHP130_SRAM_256x64(),
+        IHP130_SRAM_512x64(), IHP130_SRAM_64x64(),
+        IHP130Lambdalib_SinglePort(),
+        IHP130StdCell_1p2(), IHP130StdCell_1p5(),
+        BumpLibrary(),
+        Sky130_IOLibrary(),
+        Sky130_SCHDLibrary(), Sky130_SCHDLLLibrary(),
+        Sky130_SRAM_64x256(), Sky130Lambdalib_SinglePort()
+    ])
+
+
+def get_lib_names():
+    '''
+    Returns a list of libraries names in lambdapdk
+    '''
+
+    return set([lib.name for lib in get_libs()])
+
+
+def get_docs_codeurl(file=None):
+    base_url = f"https://github.com/siliconcompiler/lambdapdk/blob/v{__version__}"
+
+    if not file:
+        return base_url
+
+    root = os.path.dirname(os.path.dirname(os.path.abspath(__file__)))
+
+    def relpath(file):
+        file = os.path.abspath(file)
+        if file.startswith(root):
+            return os.path.relpath(file, root)
+        return None
+
+    if os.path.isabs(file):
+        file = relpath(file)
+        if not file:
+            return None
+
+    return f"{base_url}/{file}"

lambdapdk-0.2.0rc1/lambdapdk/asap7/__init__.py

@@ -0,0 +1,111 @@
+from pathlib import Path
+
+from lambdapdk import LambdaPDK
+
+
+class ASAP7PDK(LambdaPDK):
+    '''
+    The asap7 PDK was developed at ASU in collaboration with ARM Research.
+    With funding from the DARPA IDEA program, the PDK was released
+    a permissive open source PDK in 2021. The PDK contains SPICE-compatible
+    FinFET device models (BSIM-CMG), Technology files for Cadence Virtuoso,
+    Design Rule Checker (DRC), Layout vs Schematic Checker (LVS) and
+    Extraction Deck for the 7nm technology node. For more details regarding
+    the technical specifications of the PDK, please refer the PDK
+    documentation and associated publication. Note that this process
+    design kit is provided as an academic and research aid only and the
+    resulting designs are not manufacturable.
+
+    PDK content:
+
+    * open source DRM
+    * device primitive library (virtuoso)
+    * spice (hspice)
+    * extraction runsets (calibre)
+    * drc runsets (calibre)
+    * APR technology files
+    * 7.5 track multi-vt standard cell libraries
+
+    More information:
+
+    * https://asap.asu.edu/
+    * L.T. Clark, V. Vashishtha, L. Shifren, A. Gujja, S. Sinha, B. Cline,
+      C. Ramamurthya, and G. Yeric, “ASAP7: A 7-nm FinFET Predictive Process
+      Design Kit,” Microelectronics Journal, vol. 53, pp. 105-115, July 2016.
+
+
+    Sources: https://github.com/The-OpenROAD-Project/asap7
+
+    .. warning::
+       Work in progress (not ready for use)
+    '''
+
+    def __init__(self):
+        super().__init__()
+        self.set_name("asap7")
+
+        pdk_path = Path("lambdapdk", "asap7", "base")
+
+        self.set_foundry("virtual")
+        self.set_version("r1p7")
+        self.set_node(7)
+        self.set_stackup("10M")
+        self.set_wafersize(300)
+        self.set_scribewidth(0.1, 0.1)
+        self.set_edgemargin(2)
+        self.set_defectdensity(1.25)
+
+        with self.active_dataroot("lambdapdk"):
+            # APR Setup
+            with self.active_fileset("views.lef"):
+                self.add_file(pdk_path / "apr" / "asap7_tech.lef")
+                for tool in ('openroad', 'klayout', 'magic'):
+                    self.add_aprtechfileset(tool)
+
+            with self.active_fileset("layermap"):
+                self.add_file(pdk_path / "apr" / "asap7.layermap", filetype="layermap")
+
+            with self.active_fileset("models.spice"):
+                self.add_file(pdk_path / "spice" / "hspice" / "7nm.lib", filetype="library")
+                self.add_devmodelfileset("xyce", "spice")
+
+            # Klayout setup
+            with self.active_fileset("klayout.techmap"):
+                self.add_file(pdk_path / "setup" / "klayout" / "asap7.lyt", filetype="layermap")
+                self.add_file(pdk_path / "setup" / "klayout" / "asap7.lyp", filetype="display")
+                self.add_layermapfileset("klayout", "def", "klayout")
+                self.add_displayfileset("klayout")
+            self.add_layermapfileset("klayout", "def", "gds", fileset="layermap")
+
+            self.set_aprroutinglayers(min="M2", max="M7")
+
+            # OpenROAD setup
+            self.set_openroad_rclayers(signal="M3", clock="M3")
+
+            # Openroad global routing grid derating
+            for layer, derate in [
+                    ('M1', 0.25),
+                    ('M2', 0.25),
+                    ('M3', 0.25),
+                    ('M4', 0.25),
+                    ('M5', 0.25),
+                    ('M6', 0.25),
+                    ('M7', 0.25),
+                    ('M8', 0.25),
+                    ('M9', 0.25),
+                    ('Pad', 0.25)]:
+                self.set_openroad_globalroutingderating(layer, derate)
+
+            self.add_openroad_pinlayers(vertical="M5", horizontal="M4")
+
+            with self.active_fileset("openroad.routing"):
+                # Relaxed routing rules
+                self.add_file(pdk_path / "apr" / "openroad_relaxed_rules.tcl", filetype="tcl")
+
+            # PEX
+            with self.active_fileset("openroad.pex"):
+                self.add_file(pdk_path / "pex" / "openroad" / "typical.tcl", filetype="tcl")
+                self.add_file(pdk_path / "pex" / "openroad" / "typical.rules", filetype="openrcx")
+
+                self.add_pexmodelfileset("openroad", "typical")
+                self.add_pexmodelfileset("openroad-openrcx", "typical")

lambdapdk-0.2.0rc1/lambdapdk/asap7/libs/asap7sc7p5t.py

@@ -0,0 +1,123 @@
+from pathlib import Path
+
+from lambdapdk import LambdaLibrary
+from lambdapdk.asap7 import ASAP7PDK
+
+
+class _ASAP7SC7p5Base(LambdaLibrary):
+    '''
+    ASAP 7 7.5-track standard cell library.
+    '''
+    def __init__(self, vt, suffix):
+        super().__init__()
+        self.set_name(f"asap7sc7p5t_{vt}")
+
+        # version
+        self.set_version("28")
+
+        # PDK
+        self.add_asic_pdk(ASAP7PDK())
+
+        # site name
+        self.add_asic_site('asap7sc7p5t')
+
+        # tie cells
+        self.add_asic_celllist('tie', [f"TIEHIx1_ASAP7_75t_{suffix}",
+                                       f"TIELOx1_ASAP7_75t_{suffix}"])
+
+        # filler
+        self.add_asic_celllist('filler', [f"FILLER_ASAP7_75t_{suffix}",
+                                          f"FILLERxp5_ASAP7_75t_{suffix}"])
+
+        # decap
+        self.add_asic_celllist('decap', [f"DECAPx1_ASAP7_75t_{suffix}",
+                                         f"DECAPx2_ASAP7_75t_{suffix}",
+                                         f"DECAPx4_ASAP7_75t_{suffix}",
+                                         f"DECAPx6_ASAP7_75t_{suffix}",
+                                         f"DECAPx10_ASAP7_75t_{suffix}"])
+
+        # Stupid small cells
+        self.add_asic_celllist('dontuse', ["*x1p*_ASAP7*",
+                                           "*xp*_ASAP7*",
+                                           "SDF*",
+                                           "ICG*"])
+
+        # Tapcell
+        self.add_asic_celllist('tap', f"TAPCELL_ASAP7_75t_{suffix}")
+
+        # Endcap
+        self.add_asic_celllist('endcap', f"DECAPx1_ASAP7_75t_{suffix}")
+
+        lib_path = Path("lambdapdk", "asap7", "libs", f"asap7sc7p5t_{vt}")
+
+        # General filelists
+        with self.active_dataroot("lambdapdk"):
+            for corner_name, lib_corner in [
+                    ('typical', 'TT'),
+                    ('fast', 'FF'),
+                    ('slow', 'SS')]:
+
+                for lib_type in ('AO', 'INVBUF', 'OA', 'SEQ', 'SIMPLE'):
+                    with self.active_fileset(f"models.timing.{corner_name}.nldm.{lib_type}"):
+                        self.add_file(lib_path / "nldm" /
+                                      f"asap7sc7p5t_{lib_type}_{suffix}VT_{lib_corner}_nldm.lib.gz")
+                        self.add_asic_libcornerfileset(corner_name, "nldm")
+
+            with self.active_fileset("models.spice"):
+                self.add_file(lib_path / "netlist" / f"asap7sc7p5t_28_{suffix}.sp")
+
+            with self.active_fileset("models.physical"):
+                self.add_file(lib_path / "lef" / f"asap7sc7p5t_28_{suffix}.lef")
+                self.add_file(lib_path / "gds" / f"asap7sc7p5t_28_{suffix}.gds.gz")
+                self.add_asic_aprfileset()
+
+            with self.active_fileset("models.lvs"):
+                self.add_file(lib_path / "netlist" / f"asap7sc7p5t_28_{suffix}.cdl")
+                self.add_asic_aprfileset()
+
+        # Setup for yosys
+        with self.active_dataroot("lambdapdk"):
+            self.set_yosys_driver_cell(f"BUFx2_ASAP7_75t_{suffix}")
+            self.set_yosys_buffer_cell(f"BUFx2_ASAP7_75t_{suffix}", "A", "Y")
+            self.set_yosys_tielow_cell(f"TIELOx1_ASAP7_75t_{suffix}", "L")
+            self.set_yosys_tiehigh_cell(f"TIEHIx1_ASAP7_75t_{suffix}", "H")
+
+            cap_table = {  # BUFx2_ASAP7_75t_, fF
+                'R': "2.308",
+                'L': "2.383",
+                'SL': "2.464"
+            }
+            self.set_yosys_abc(1, cap_table[suffix])
+            self.set_yosys_adder_map(lib_path / "techmap" / "yosys" / "cells_adders.v")
+            self.add_yosys_tech_map(lib_path / "techmap" / "yosys" / "cells_latch.v")
+
+        # Setup for openroad
+        with self.active_dataroot("lambdapdk"):
+            self.set_openroad_placement_density(0.60)
+            self.set_openroad_tielow_cell(f"TIELOx1_ASAP7_75t_{suffix}", "L")
+            self.set_openroad_tiehigh_cell(f"TIEHIx1_ASAP7_75t_{suffix}", "H")
+            self.set_openroad_macro_placement_halo(5, 5)
+            self.set_openroad_tracks_file(lib_path / "apr" / "openroad" / "tracks.tcl")
+            self.set_openroad_tapcells_file(lib_path / "apr" / "openroad" / "tapcells.tcl")
+            self.add_openroad_global_connect_file(lib_path / "apr" / "openroad" /
+                                                  "global_connect.tcl")
+            self.add_openroad_power_grid_file(lib_path / "apr" / "openroad" / "pdngen.tcl")
+
+        # Setup for bambu
+        self.set_bambu_device_name("asap7-WC")
+        self.set_bambu_clock_multiplier(0.001)
+
+
+class ASAP7SC7p5RVT(_ASAP7SC7p5Base):
+    def __init__(self):
+        super().__init__("rvt", "R")
+
+
+class ASAP7SC7p5LVT(_ASAP7SC7p5Base):
+    def __init__(self):
+        super().__init__("lvt", "L")
+
+
+class ASAP7SC7p5SLVT(_ASAP7SC7p5Base):
+    def __init__(self):
+        super().__init__("slvt", "SL")

lambdapdk-0.2.0rc1/lambdapdk/asap7/libs/fakeio7.py

@@ -0,0 +1,26 @@
+from pathlib import Path
+
+from lambdapdk import LambdaLibrary
+from lambdapdk.asap7 import ASAP7PDK
+
+
+class FakeIO7Library(LambdaLibrary):
+    '''
+    ASAP7 Fake I/O library.
+    '''
+    def __init__(self):
+        super().__init__()
+        self.set_name("fakeio7")
+
+        self.add_asic_pdk(ASAP7PDK())
+
+        path_base = Path("lambdapdk", "asap7", "libs", "fakeio7")
+
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("models.physical"):
+                self.add_file(path_base / "lef" / "fakeio7.lef")
+                self.add_asic_aprfileset()
+
+            with self.active_fileset("models.blackbox"):
+                self.add_file(path_base / "blackbox" / "model.v")
+            self.add_yosys_blackbox_fileset("models.blackbox")

lambdapdk-0.2.0rc1/lambdapdk/asap7/libs/fakekit7.py

@@ -0,0 +1,22 @@
+from pathlib import Path
+
+from lambdapdk import LambdaLibrary
+from lambdapdk.asap7 import ASAP7PDK
+
+
+class FakeKit7Library(LambdaLibrary):
+    '''
+    ASAP7 Fake Chip Collatoral library.
+    '''
+    def __init__(self):
+        super().__init__()
+        self.set_name("fakekit7")
+
+        self.add_asic_pdk(ASAP7PDK())
+
+        path_base = Path("lambdapdk", "asap7", "libs", "fakekit7")
+
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("models.physical"):
+                self.add_file(path_base / "lef" / "tsv.lef")
+                self.add_asic_aprfileset()