lambdapdk 0.1.39__tar.gz → 0.1.41__tar.gz

{lambdapdk-0.1.39/lambdapdk.egg-info → lambdapdk-0.1.41}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: lambdapdk
-Version: 0.1.39
+Version: 0.1.41
 Summary: Library of open source Process Design Kits
 Author: Zero ASIC
 License:                                  Apache License

{lambdapdk-0.1.39 → lambdapdk-0.1.41}/lambdapdk/__init__.py

@@ -1,7 +1,7 @@
 import siliconcompiler.package as sc_package
 
 
-__version__ = "0.1.39"
+__version__ = "0.1.41"
 
 
 def register_data_source(chip):
@@ -15,27 +15,9 @@ def register_data_source(chip):
     )
 
 
-def get_pdks():
+def setup_libs():
     '''
-    Returns a list of pdk names in lambdapdk
-    '''
-
-    from lambdapdk import asap7, freepdk45, sky130, gf180, ihp130, interposer
-
-    all_pdks = []
-    for pdk_mod in [asap7, freepdk45, sky130, gf180, ihp130, interposer]:
-        pdks = pdk_mod.setup()
-        if not isinstance(pdks, (list, tuple)):
-            pdks = [pdks]
-        for pdk in pdks:
-            all_pdks.append(pdk.design)
-
-    return set(all_pdks)
-
-
-def get_libs():
-    '''
-    Returns a list of libraries names in lambdapdk
+    Returns a list of libraries in lambdapdk
     '''
 
     from lambdapdk.asap7.libs import asap7sc7p5t, fakeram7, fakeio7
@@ -57,6 +39,59 @@ def get_libs():
         if not isinstance(libs, (list, tuple)):
             libs = [libs]
         for lib in libs:
-            all_libs.append(lib.design)
+            all_libs.append(lib)
+
+    return all_libs
+
+
+def setup_pdks():
+    '''
+    Returns a list of pdks in lambdapdk
+    '''
+
+    from lambdapdk import asap7, freepdk45, sky130, gf180, ihp130, interposer
+
+    all_pdks = []
+    for pdk_mod in [asap7, freepdk45, sky130, gf180, ihp130, interposer]:
+        pdks = pdk_mod.setup()
+        if not isinstance(pdks, (list, tuple)):
+            pdks = [pdks]
+        for pdk in pdks:
+            all_pdks.append(pdk)
+
+    return all_pdks
+
+
+def setup():
+    '''
+    Returns a list of all pdks and libraries in lambdapdk
+    '''
+
+    return [
+        *setup_pdks(),
+        *setup_libs()
+    ]
+
+
+def get_pdks():
+    '''
+    Returns a list of pdk names in lambdapdk
+    '''
+
+    all_pdks = []
+    for pdk in setup_pdks():
+        all_pdks.append(pdk.design)
+
+    return set(all_pdks)
+
+
+def get_libs():
+    '''
+    Returns a list of libraries names in lambdapdk
+    '''
+
+    all_libs = []
+    for lib in setup_libs():
+        all_libs.append(lib.design)
 
     return set(all_libs)

{lambdapdk-0.1.39 → lambdapdk-0.1.41}/lambdapdk/asap7/libs/asap7sc7p5t.py

@@ -46,9 +46,6 @@ def _setup_lib(libname, suffix):
     # site name
     lib.set('asic', 'site', libtype, 'asap7sc7p5t')
 
-    # clock buffers - remove once openroad driver supports it
-    lib.add('asic', 'cells', 'clkbuf', f"BUFx4_ASAP7_75t_{suffix}")
-
     # tie cells
     lib.add('asic', 'cells', 'tie', [f"TIEHIx1_ASAP7_75t_{suffix}",
                                      f"TIELOx1_ASAP7_75t_{suffix}"])
@@ -94,11 +91,11 @@ def _setup_lib(libname, suffix):
     lib.set('option', 'var', 'yosys_abc_clock_multiplier', "1")  # convert from ps -> ps
 
     cap_table = {  # BUFx2_ASAP7_75t_
-        'R': 0.506500,
-        'L': 0.519810,
-        'SL': 0.533411
+        'R': "2.308fF",
+        'L': "2.383fF",
+        'SL': "2.464fF"
     }
-    lib.set('option', 'var', 'yosys_abc_constraint_load', f"{4 * cap_table[suffix]}fF")
+    lib.set('option', 'var', 'yosys_abc_constraint_load', cap_table[suffix])
     lib.set('option', 'var', 'yosys_driver_cell', f"BUFx2_ASAP7_75t_{suffix}")
     lib.set('option', 'var', 'yosys_buffer_cell', f"BUFx2_ASAP7_75t_{suffix}")
     lib.set('option', 'var', 'yosys_buffer_input', "A")

{lambdapdk-0.1.39 → lambdapdk-0.1.41}/lambdapdk/freepdk45/libs/nangate45.py

@@ -73,6 +73,7 @@ def setup():
     # Techmap
     lib.add('option', 'file', 'yosys_techmap', libdir + '/techmap/yosys/cells_latch.v')
     lib.add('option', 'file', 'yosys_addermap', libdir + '/techmap/yosys/cells_adders.v')
+    lib.add('option', 'file', 'yosys_tbufmap', libdir + '/techmap/yosys/cells_tristatebuf.v')
 
     # Defaults for OpenROAD tool variables
     lib.set('option', 'var', 'openroad_place_density', '0.50')
@@ -87,7 +88,7 @@ def setup():
             libdir + '/apr/openroad/global_connect.tcl')
 
     lib.set('option', 'var', 'yosys_abc_clock_multiplier', "1000")  # convert from ns -> ps
-    lib.set('option', 'var', 'yosys_abc_constraint_load', "3.898fF")  # BUF_X1 = 0.974659 x 4
+    lib.set('option', 'var', 'yosys_abc_constraint_load', "3.899fF")  # BUF_X1 = 0.974659 x 4
     lib.set('option', 'var', 'yosys_driver_cell', "BUF_X4")
     lib.set('option', 'var', 'yosys_buffer_cell', "BUF_X1")
     lib.set('option', 'var', 'yosys_buffer_input', "A")

{lambdapdk-0.1.39 → lambdapdk-0.1.41}/lambdapdk/gf180/libs/gf180mcu.py

@@ -99,6 +99,7 @@ def setup():
         # Yosys techmap
         lib.add('option', 'file', 'yosys_techmap', libdir + '/techmap/yosys/cells_latch.v')
         lib.add('option', 'file', 'yosys_addermap', libdir + '/techmap/yosys/cells_adders.v')
+        lib.add('option', 'file', 'yosys_tbufmap', libdir + '/techmap/yosys/cells_tristatebuf.v')
 
         # Openroad specific files
         lib.set('option', 'file', 'openroad_pdngen',
@@ -112,11 +113,11 @@ def setup():
 
         lib.set('option', 'var', 'yosys_abc_clock_multiplier', "1000")  # convert from ns -> ps
 
-        cap_table = {  # __buf_1
-            '7t': 2.521,
-            '9t': 3.673
+        cap_table = {  # __buf_4
+            '7t': "0.038pF",
+            '9t': "0.056pF"
         }
-        lib.set('option', 'var', 'yosys_abc_constraint_load', f"{4 * cap_table[libtype]}fF")
+        lib.set('option', 'var', 'yosys_abc_constraint_load', cap_table[libtype])
         lib.set('option', 'var', 'yosys_driver_cell', f"gf180mcu_fd_sc_mcu{libtype}5v0__buf_4")
         lib.set('option', 'var', 'yosys_buffer_cell', f"gf180mcu_fd_sc_mcu{libtype}5v0__buf_4")
         lib.set('option', 'var', 'yosys_buffer_input', "I")

{lambdapdk-0.1.39 → lambdapdk-0.1.41}/lambdapdk/ihp130/libs/sg13g2_stdcell.py

@@ -56,10 +56,6 @@ def setup():
     lib.add('output', 'rtl', 'verilog',
             'ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v')
 
-    # clock buffers - remove once openroad driver supports it
-    lib.add('asic', 'cells', 'clkbuf', ["sg13g2_buf_2",
-                                        "sg13g2_buf_4"])
-
     # tie cells
     lib.add('asic', 'cells', 'tie', ["LOGIC1_X1",
                                      "LOGIC0_X1"])
@@ -92,6 +88,9 @@ def setup():
     lib.add('option', 'file', 'yosys_techmap',
             libdir + '/techmap/yosys/cells_latch.v',
             package='lambdapdk')
+    lib.add('option', 'file', 'yosys_tbufmap',
+            libdir + '/techmap/yosys/cells_tristatebuf.v',
+            package='lambdapdk')
 
     # Defaults for OpenROAD tool variables
     lib.set('option', 'var', 'openroad_place_density', '0.65')
@@ -110,7 +109,7 @@ def setup():
             package='lambdapdk')
 
     lib.set('option', 'var', 'yosys_abc_clock_multiplier', "1000")  # convert from ns -> ps
-    lib.set('option', 'var', 'yosys_abc_constraint_load', "6.0fF")  # BUF_X1 = 0.974659 x 4
+    lib.set('option', 'var', 'yosys_abc_constraint_load', "0.017pF")
     lib.set('option', 'var', 'yosys_driver_cell', "sg13g2_buf_4")
     lib.set('option', 'var', 'yosys_buffer_cell', "sg13g2_buf_4")
     lib.set('option', 'var', 'yosys_buffer_input', "A")

{lambdapdk-0.1.39 → lambdapdk-0.1.41}/lambdapdk/sky130/libs/sky130sc.py

@@ -150,6 +150,7 @@ def setup():
         # Yosys techmap
         # TODO: separate this out properly for the different libraries
         lib.add('option', 'file', 'yosys_techmap', libdir + '/techmap/yosys/cells_latch.v')
+        lib.add('option', 'file', 'yosys_tbufmap', libdir + '/techmap/yosys/cells_tristatebuf.v')
         if libtype == "hd":
             lib.add('option', 'file', 'yosys_addermap', libdir + '/techmap/yosys/cells_adders.v')
 
@@ -164,10 +165,10 @@ def setup():
         lib.set('option', 'var', 'yosys_abc_clock_multiplier', "1000")  # convert from ns -> ps
 
         cap_table = {
-            'hd': 1.872,
-            'hdll': 1.911
+            'hd': "0.011pF",
+            'hdll': "0.011pF"
         }
-        lib.set('option', 'var', 'yosys_abc_constraint_load', f"{4 * cap_table[libtype]}fF")
+        lib.set('option', 'var', 'yosys_abc_constraint_load', cap_table[libtype])
 
         lib.set('option', 'var', 'yosys_driver_cell', f"sky130_fd_sc_{libtype}__buf_4")
         lib.set('option', 'var', 'yosys_buffer_cell', f"sky130_fd_sc_{libtype}__buf_4")

{lambdapdk-0.1.39 → lambdapdk-0.1.41/lambdapdk.egg-info}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: lambdapdk
-Version: 0.1.39
+Version: 0.1.41
 Summary: Library of open source Process Design Kits
 Author: Zero ASIC
 License:                                  Apache License