lambdapdk 0.1.38__tar.gz → 0.1.40__tar.gz

{lambdapdk-0.1.38/lambdapdk.egg-info → lambdapdk-0.1.40}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: lambdapdk
-Version: 0.1.38
+Version: 0.1.40
 Summary: Library of open source Process Design Kits
 Author: Zero ASIC
 License:                                  Apache License
@@ -201,10 +201,10 @@ License-File: LICENSE
 Requires-Dist: siliconcompiler>=0.27.0
 Provides-Extra: test
 Requires-Dist: flake8==7.1.1; extra == "test"
-Requires-Dist: pytest==8.3.3; extra == "test"
+Requires-Dist: pytest==8.3.4; extra == "test"
 Requires-Dist: pytest-timeout==2.3.1; extra == "test"
-Requires-Dist: tclint==0.4.2; extra == "test"
-Requires-Dist: lambdalib==0.3.0; extra == "test"
+Requires-Dist: tclint==0.5.0; extra == "test"
+Requires-Dist: lambdalib==0.3.2; extra == "test"
 Requires-Dist: sc-leflib==0.4.0; extra == "test"
 Requires-Dist: Jinja2==3.1.4; extra == "test"
 

{lambdapdk-0.1.38 → lambdapdk-0.1.40}/lambdapdk/__init__.py

@@ -1,7 +1,7 @@
 import siliconcompiler.package as sc_package
 
 
-__version__ = "0.1.38"
+__version__ = "0.1.40"
 
 
 def register_data_source(chip):

{lambdapdk-0.1.38 → lambdapdk-0.1.40}/lambdapdk/asap7/__init__.py

@@ -111,6 +111,10 @@ def setup():
     pdk.set('pdk', process, 'pexmodel', 'openroad-openrcx', stackup, 'typical',
             pdkdir + '/pex/openroad/typical.rules')
 
+    # Relaxed routing rules
+    pdk.set('pdk', process, 'file', 'openroad', 'relax_routing_rules', stackup,
+            pdkdir + '/apr/openroad_relaxed_rules.tcl')
+
     # Hide the DIEAREA layer 235/*.
     pdk.add('pdk', process, 'var', 'klayout', 'hide_layers', stackup, '235/0')
     pdk.add('pdk', process, 'var', 'klayout', 'hide_layers', stackup, '235/5')

{lambdapdk-0.1.38 → lambdapdk-0.1.40}/lambdapdk/asap7/libs/asap7sc7p5t.py

@@ -46,16 +46,13 @@ def _setup_lib(libname, suffix):
     # site name
     lib.set('asic', 'site', libtype, 'asap7sc7p5t')
 
-    # clock buffers
-    lib.add('asic', 'cells', 'clkbuf', f"BUFx2_ASAP7_75t_{suffix}")
+    # clock buffers - remove once openroad driver supports it
+    lib.add('asic', 'cells', 'clkbuf', f"BUFx4_ASAP7_75t_{suffix}")
 
     # tie cells
     lib.add('asic', 'cells', 'tie', [f"TIEHIx1_ASAP7_75t_{suffix}",
                                      f"TIELOx1_ASAP7_75t_{suffix}"])
 
-    # hold cells
-    lib.add('asic', 'cells', 'hold', f"BUFx2_ASAP7_75t_{suffix}")
-
     # filler
     lib.add('asic', 'cells', 'filler', [f"FILLER_ASAP7_75t_{suffix}",
                                         f"FILLERxp5_ASAP7_75t_{suffix}"])
@@ -92,7 +89,6 @@ def _setup_lib(libname, suffix):
     lib.set('option', 'var', 'openroad_macro_place_halo', ['10', '10'])
     lib.set('option', 'var', 'openroad_macro_place_channel', ['12', '12'])
 
-    lib.set('option', 'var', 'openroad_cts_clock_buffer', f"BUFx4_ASAP7_75t_{suffix}")
     lib.set('option', 'var', 'openroad_cts_distance_between_buffers', "60")
 
     lib.set('option', 'var', 'yosys_abc_clock_multiplier', "1")  # convert from ps -> ps

{lambdapdk-0.1.38 → lambdapdk-0.1.40}/lambdapdk/freepdk45/libs/nangate45.py

@@ -45,15 +45,14 @@ def setup():
     lib.add('output', stackup, 'cdl', libdir + '/cdl/NangateOpenCellLibrary.cdl')
 
     # clock buffers
-    lib.add('asic', 'cells', 'clkbuf', "BUF_X4")
+    lib.set('asic', 'cells', 'clkbuf', ["CLKBUF_X1",
+                                        "CLKBUF_X2",
+                                        "CLKBUF_X3"])
 
     # tie cells
     lib.add('asic', 'cells', 'tie', ["LOGIC1_X1",
                                      "LOGIC0_X1"])
 
-    # hold cells
-    lib.add('asic', 'cells', 'hold', "BUF_X1")
-
     # filler
     lib.add('asic', 'cells', 'filler', ["FILLCELL_X1",
                                         "FILLCELL_X2",
@@ -74,6 +73,7 @@ def setup():
     # Techmap
     lib.add('option', 'file', 'yosys_techmap', libdir + '/techmap/yosys/cells_latch.v')
     lib.add('option', 'file', 'yosys_addermap', libdir + '/techmap/yosys/cells_adders.v')
+    lib.add('option', 'file', 'yosys_tbufmap', libdir + '/techmap/yosys/cells_tristatebuf.v')
 
     # Defaults for OpenROAD tool variables
     lib.set('option', 'var', 'openroad_place_density', '0.50')

{lambdapdk-0.1.38 → lambdapdk-0.1.40}/lambdapdk/gf180/libs/gf180mcu.py

@@ -99,6 +99,7 @@ def setup():
         # Yosys techmap
         lib.add('option', 'file', 'yosys_techmap', libdir + '/techmap/yosys/cells_latch.v')
         lib.add('option', 'file', 'yosys_addermap', libdir + '/techmap/yosys/cells_adders.v')
+        lib.add('option', 'file', 'yosys_tbufmap', libdir + '/techmap/yosys/cells_tristatebuf.v')
 
         # Openroad specific files
         lib.set('option', 'file', 'openroad_pdngen',
@@ -108,8 +109,6 @@ def setup():
         lib.set('option', 'file', 'openroad_tapcells',
                 libdir + '/apr/openroad/tapcell.tcl')
 
-        lib.set('option', 'var', 'openroad_cts_clock_buffer',
-                f"gf180mcu_fd_sc_mcu{libtype}5v0__clkbuf_8")
         lib.set('option', 'var', 'openroad_cts_distance_between_buffers', "100")
 
         lib.set('option', 'var', 'yosys_abc_clock_multiplier', "1000")  # convert from ns -> ps

{lambdapdk-0.1.38 → lambdapdk-0.1.40}/lambdapdk/ihp130/libs/sg13g2_stdcell.py

@@ -56,7 +56,7 @@ def setup():
     lib.add('output', 'rtl', 'verilog',
             'ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v')
 
-    # clock buffers
+    # clock buffers - remove once openroad driver supports it
     lib.add('asic', 'cells', 'clkbuf', ["sg13g2_buf_2",
                                         "sg13g2_buf_4"])
 
@@ -65,8 +65,9 @@ def setup():
                                      "LOGIC0_X1"])
 
     # hold cells
-    lib.add('asic', 'cells', 'hold', ["sg13g2_buf_1",
-                                      "sg13g2_buf_4"])
+    lib.add('asic', 'cells', 'hold', ["sg13g2_dlygate4sd1_1",
+                                      "sg13g2_dlygate4sd2_1",
+                                      "sg13g2_dlygate4sd3_1"])
 
     # filler
     lib.add('asic', 'cells', 'filler', ["sg13g2_fill_1",
@@ -81,9 +82,8 @@ def setup():
     # antenna
     lib.add('asic', 'cells', 'antenna', ["sg13g2_antennanp"])
 
-    # Stupid small cells
-    lib.add('asic', 'cells', 'dontuse', ["sg13g2_antennanp",
-                                         "sg13g2_lgcp_1",
+    # Dont use
+    lib.add('asic', 'cells', 'dontuse', ["sg13g2_lgcp_1",
                                          "sg13g2_sighold",
                                          "sg13g2_slgcp_1",
                                          "sg13g2_dfrbp_2"])
@@ -92,6 +92,9 @@ def setup():
     lib.add('option', 'file', 'yosys_techmap',
             libdir + '/techmap/yosys/cells_latch.v',
             package='lambdapdk')
+    lib.add('option', 'file', 'yosys_tbufmap',
+            libdir + '/techmap/yosys/cells_tristatebuf.v',
+            package='lambdapdk')
 
     # Defaults for OpenROAD tool variables
     lib.set('option', 'var', 'openroad_place_density', '0.65')

{lambdapdk-0.1.38 → lambdapdk-0.1.40}/lambdapdk/sky130/libs/sky130sc.py

@@ -104,19 +104,20 @@ def setup():
         lib.add('asic', 'cells', 'clkbuf', [f'sky130_fd_sc_{libtype}__clkbuf_1',
                                             f'sky130_fd_sc_{libtype}__clkbuf_2',
                                             f'sky130_fd_sc_{libtype}__clkbuf_4',
-                                            f'sky130_fd_sc_{libtype}__clkbuf_6',
                                             f'sky130_fd_sc_{libtype}__clkbuf_8',
-                                            f'sky130_fd_sc_{libtype}__clkbuf_12',
                                             f'sky130_fd_sc_{libtype}__clkbuf_16'])
+        if libtype == "hdll":
+            lib.add('asic', 'cells', 'clkbuf', [f'sky130_fd_sc_{libtype}__clkbuf_6',
+                                                f'sky130_fd_sc_{libtype}__clkbuf_12'])
 
         # hold cells
-        lib.add('asic', 'cells', 'hold', [f'sky130_fd_sc_{libtype}__buf_1',
-                                          f'sky130_fd_sc_{libtype}__buf_2',
-                                          f'sky130_fd_sc_{libtype}__buf_4',
-                                          f'sky130_fd_sc_{libtype}__buf_6',
-                                          f'sky130_fd_sc_{libtype}__buf_8',
-                                          f'sky130_fd_sc_{libtype}__buf_12',
-                                          f'sky130_fd_sc_{libtype}__buf_16'])
+        lib.add('asic', 'cells', 'hold', [f'sky130_fd_sc_{libtype}__dlygate4sd1_1',
+                                          f'sky130_fd_sc_{libtype}__dlygate4sd2_1',
+                                          f'sky130_fd_sc_{libtype}__dlygate4sd3_1'])
+        if libtype == "hd":
+            lib.add('asic', 'cells', 'hold', [f'sky130_fd_sc_{libtype}__dlymetal6s2s_1',
+                                              f'sky130_fd_sc_{libtype}__dlymetal6s4s_1',
+                                              f'sky130_fd_sc_{libtype}__dlymetal6s6s_1'])
 
         # filler
         lib.add('asic', 'cells', 'filler', [f'sky130_fd_sc_{libtype}__fill_1',
@@ -149,6 +150,7 @@ def setup():
         # Yosys techmap
         # TODO: separate this out properly for the different libraries
         lib.add('option', 'file', 'yosys_techmap', libdir + '/techmap/yosys/cells_latch.v')
+        lib.add('option', 'file', 'yosys_tbufmap', libdir + '/techmap/yosys/cells_tristatebuf.v')
         if libtype == "hd":
             lib.add('option', 'file', 'yosys_addermap', libdir + '/techmap/yosys/cells_adders.v')
 
@@ -160,8 +162,6 @@ def setup():
         lib.set('option', 'file', 'openroad_tapcells',
                 libdir + '/apr/openroad/tapcell.tcl')
 
-        lib.set('option', 'var', 'openroad_cts_clock_buffer', f"sky130_fd_sc_{libtype}__clkbuf_4")
-
         lib.set('option', 'var', 'yosys_abc_clock_multiplier', "1000")  # convert from ns -> ps
 
         cap_table = {

{lambdapdk-0.1.38 → lambdapdk-0.1.40/lambdapdk.egg-info}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: lambdapdk
-Version: 0.1.38
+Version: 0.1.40
 Summary: Library of open source Process Design Kits
 Author: Zero ASIC
 License:                                  Apache License
@@ -201,10 +201,10 @@ License-File: LICENSE
 Requires-Dist: siliconcompiler>=0.27.0
 Provides-Extra: test
 Requires-Dist: flake8==7.1.1; extra == "test"
-Requires-Dist: pytest==8.3.3; extra == "test"
+Requires-Dist: pytest==8.3.4; extra == "test"
 Requires-Dist: pytest-timeout==2.3.1; extra == "test"
-Requires-Dist: tclint==0.4.2; extra == "test"
-Requires-Dist: lambdalib==0.3.0; extra == "test"
+Requires-Dist: tclint==0.5.0; extra == "test"
+Requires-Dist: lambdalib==0.3.2; extra == "test"
 Requires-Dist: sc-leflib==0.4.0; extra == "test"
 Requires-Dist: Jinja2==3.1.4; extra == "test"
 

{lambdapdk-0.1.38 → lambdapdk-0.1.40}/lambdapdk.egg-info/requires.txt

@@ -2,9 +2,9 @@ siliconcompiler>=0.27.0
 
 [test]
 flake8==7.1.1
-pytest==8.3.3
+pytest==8.3.4
 pytest-timeout==2.3.1
-tclint==0.4.2
-lambdalib==0.3.0
+tclint==0.5.0
+lambdalib==0.3.2
 sc-leflib==0.4.0
 Jinja2==3.1.4

{lambdapdk-0.1.38 → lambdapdk-0.1.40}/pyproject.toml

@@ -28,10 +28,10 @@ timeout = "180"
 # Test dependencies.
 test = [
     "flake8 == 7.1.1",
-    "pytest == 8.3.3",
+    "pytest == 8.3.4",
     "pytest-timeout == 2.3.1",
-    "tclint == 0.4.2",
-    "lambdalib == 0.3.0",
+    "tclint == 0.5.0",
+    "lambdalib == 0.3.2",
     "sc-leflib == 0.4.0",
     "Jinja2 == 3.1.4"
 ]