lambdapdk 0.1.35__tar.gz → 0.1.37__tar.gz

{lambdapdk-0.1.35/lambdapdk.egg-info → lambdapdk-0.1.37}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: lambdapdk
-Version: 0.1.35
+Version: 0.1.37
 Summary: Library of open source Process Design Kits
 Author: Zero ASIC
 License:                                  Apache License
@@ -203,8 +203,8 @@ Provides-Extra: test
 Requires-Dist: flake8==7.1.1; extra == "test"
 Requires-Dist: pytest==8.3.3; extra == "test"
 Requires-Dist: pytest-timeout==2.3.1; extra == "test"
-Requires-Dist: tclint==0.4.1; extra == "test"
-Requires-Dist: lambdalib==0.2.10; extra == "test"
+Requires-Dist: tclint==0.4.2; extra == "test"
+Requires-Dist: lambdalib==0.3.0; extra == "test"
 Requires-Dist: sc-leflib==0.4.0; extra == "test"
 
 # Lambdapdk Introduction

{lambdapdk-0.1.35 → lambdapdk-0.1.37}/lambdapdk/__init__.py

@@ -1,7 +1,7 @@
 import siliconcompiler.package as sc_package
 
 
-__version__ = "0.1.35"
+__version__ = "0.1.37"
 
 
 def register_data_source(chip):

{lambdapdk-0.1.35 → lambdapdk-0.1.37}/lambdapdk/asap7/__init__.py

@@ -125,6 +125,6 @@ def setup():
 
 #########################
 if __name__ == "__main__":
-    pdk = setup(siliconcompiler.Chip('<pdk>'))
+    pdk = setup()
     register_data_source(pdk)
     pdk.check_filepaths()

{lambdapdk-0.1.35 → lambdapdk-0.1.37}/lambdapdk/asap7/libs/asap7sc7p5t.py

@@ -62,8 +62,8 @@ def _setup_lib(libname, suffix):
 
     # decap
     lib.add('asic', 'cells', 'decap', [f"DECAPx1_ASAP7_75t_{suffix}",
-                                       f"DECAPx1_ASAP7_75t_{suffix}",
-                                       f"DECAPx3_ASAP7_75t_{suffix}",
+                                       f"DECAPx2_ASAP7_75t_{suffix}",
+                                       f"DECAPx4_ASAP7_75t_{suffix}",
                                        f"DECAPx6_ASAP7_75t_{suffix}",
                                        f"DECAPx10_ASAP7_75t_{suffix}"])
 

{lambdapdk-0.1.35 → lambdapdk-0.1.37}/lambdapdk/freepdk45/__init__.py

@@ -103,6 +103,6 @@ def setup():
 
 #########################
 if __name__ == "__main__":
-    pdk = setup(siliconcompiler.Chip('<pdk>'))
+    pdk = setup()
     register_data_source(pdk)
     pdk.check_filepaths()

{lambdapdk-0.1.35 → lambdapdk-0.1.37}/lambdapdk/freepdk45/libs/nangate45.py

@@ -122,5 +122,5 @@ def setup():
 
 #########################
 if __name__ == "__main__":
-    lib = setup(siliconcompiler.Chip('<lib>'))
+    lib = setup()
     lib.write_manifest(f'{lib.top()}.json')

{lambdapdk-0.1.35 → lambdapdk-0.1.37}/lambdapdk/gf180/__init__.py

@@ -102,13 +102,7 @@ def setup():
             if layer == pdk.get('pdk', process, 'maxlayer', stackup):
                 break
 
-        if max_layer == 2:
-            pdk.set('pdk', process, 'var', 'openroad', 'rclayer_signal', stackup, 'Metal2')
-            pdk.set('pdk', process, 'var', 'openroad', 'rclayer_clock', stackup, 'Metal2')
-
-            pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_vertical', stackup, 'Metal2')
-            pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_horizontal', stackup, 'Metal1')
-        elif max_layer == 3:
+        if max_layer == 3:
             pdk.set('pdk', process, 'var', 'openroad', 'rclayer_signal', stackup, 'Metal2')
             pdk.set('pdk', process, 'var', 'openroad', 'rclayer_clock', stackup, 'Metal2')
 
@@ -137,6 +131,47 @@ def setup():
             pdk.set('pdk', process, 'pexmodel', 'openroad-openrcx', stackup, corner,
                     pdkdir + '/pex/openroad/' + base_name + '.rules')
 
+        # DRC
+        metal_level, _, metal_top = stackup.split('_')
+        drcs = {
+            "drc": pdkdir + '/setup/klayout/drc/gf180mcu.drc',
+            "drc_feol": pdkdir + '/setup/klayout/drc/gf180mcu.drc',
+            "drc_beol": pdkdir + '/setup/klayout/drc/gf180mcu.drc',
+            "antenna": pdkdir + '/setup/klayout/drc/gf180mcu_antenna.drc',
+            "density": pdkdir + '/setup/klayout/drc/gf180mcu_density.drc'
+        }
+        for drc, runset in drcs.items():
+            pdk.set('pdk', process, 'drc', 'runset', 'klayout', stackup, drc, runset)
+
+            key = f'drc_params:{drc}'
+            pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'input=<input>')
+            pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'topcell=<topcell>')
+            pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'report=<report>')
+            pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'thr=<threads>')
+            pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'run_mode=flat')
+            pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'offgrid=true')
+
+            if drc in ('drc', 'drc_feol', 'drc_beol'):
+                feol = 'true'
+                beol = 'true'
+                if drc == 'drc_feol':
+                    beol = 'false'
+                if drc == 'drc_beol':
+                    feol = 'false'
+                pdk.add('pdk', process, 'var', 'klayout', stackup, key,
+                        f'feol={feol}')
+                pdk.add('pdk', process, 'var', 'klayout', stackup, key,
+                        f'beol={beol}')
+
+            pdk.add('pdk', process, 'var', 'klayout', stackup, key,
+                    f'metal_top={metal_top}')
+            pdk.add('pdk', process, 'var', 'klayout', stackup, key,
+                    f'metal_level={metal_level}')
+            if max_layer == 3:
+                pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'mim_option=A')
+            elif max_layer == 4 or max_layer == 5:
+                pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'mim_option=B')
+
         pdk.add('pdk', process, 'var', 'klayout', 'hide_layers', stackup, 'Dualgate')
         pdk.add('pdk', process, 'var', 'klayout', 'hide_layers', stackup, 'V5_XTOR')
         pdk.add('pdk', process, 'var', 'klayout', 'hide_layers', stackup, 'PR_bndry')
@@ -146,6 +181,6 @@ def setup():
 
 #########################
 if __name__ == "__main__":
-    pdk = setup(siliconcompiler.Chip('<pdk>'))
+    pdk = setup()
     pdk.write_manifest(f'{pdk.top()}.json')
     pdk.check_filepaths()

{lambdapdk-0.1.35 → lambdapdk-0.1.37}/lambdapdk/gf180/libs/gf180mcu.py

@@ -155,7 +155,7 @@ def setup():
 
 #########################
 if __name__ == "__main__":
-    libs = setup(siliconcompiler.Chip('<lib>'))
+    libs = setup()
     for lib in libs:
         lib.write_manifest(f'{lib.top()}.json')
         lib.check_filepaths()

{lambdapdk-0.1.35 → lambdapdk-0.1.37}/lambdapdk/ihp130/__init__.py

@@ -4,7 +4,7 @@ import siliconcompiler
 from lambdapdk import register_data_source
 
 
-pdk_rev = '89c8038db331ccfdf6be488dfc4670cb62ba3c42'
+pdk_rev = '035037f6312851414e4bb5daa5a9d18975c768b3'
 
 
 def register_ihp130_data_source(chip):
@@ -118,6 +118,19 @@ def setup():
         pdk.set('pdk', process, 'pexmodel', 'openroad-openrcx', stackup, corner,
                 lpdkdir + '/pex/openroad/' + corner + '.rules', package='lambdapdk')
 
+    # DRC
+    drcs = {
+        "maximal": 'ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_maximal.lydrc',
+        "minimal": 'ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_minimal.lydrc'
+    }
+    for drc, runset in drcs.items():
+        pdk.set('pdk', process, 'drc', 'runset', 'klayout', stackup, drc, runset)
+
+        key = f'drc_params:{drc}'
+        pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'in_gds=<input>')
+        pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'cell=<topcell>')
+        pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'report_file=<report>')
+
     # Documentation
     pdk.set('pdk', process, 'doc', 'overview',
             'ihp-sg13g2/libs.doc/doc/SG13G2_os_process_spec.pdf')
@@ -129,5 +142,6 @@ def setup():
 
 #########################
 if __name__ == "__main__":
-    pdk = setup(siliconcompiler.Chip('<pdk>'))
+    pdk = setup()
     pdk.write_manifest(f'{pdk.top()}.json')
+    pdk.check_filepaths()

{lambdapdk-0.1.35 → lambdapdk-0.1.37}/lambdapdk/ihp130/libs/sg13g2_stdcell.py

@@ -70,7 +70,9 @@ def setup():
 
     # filler
     lib.add('asic', 'cells', 'filler', ["sg13g2_fill_1",
-                                        "sg13g2_fill_2"])
+                                        "sg13g2_fill_2",
+                                        "sg13g2_fill_4",
+                                        "sg13g2_fill_8"])
 
     # decap
     lib.add('asic', 'cells', 'decap', ["sg13g2_decap_4",
@@ -97,6 +99,7 @@ def setup():
     lib.set('option', 'var', 'openroad_pad_detail_place', '0')
     lib.set('option', 'var', 'openroad_macro_place_halo', ['40', '40'])
     lib.set('option', 'var', 'openroad_macro_place_channel', ['80', '80'])
+    lib.set('option', 'var', 'openroad_dpl_use_decap_fillers', False)
 
     lib.set('option', 'file', 'openroad_tapcells', libdir + '/apr/openroad/tapcell.tcl',
             package='lambdapdk')
@@ -131,5 +134,5 @@ def setup():
 
 #########################
 if __name__ == "__main__":
-    lib = setup(siliconcompiler.Chip('<lib>'))
+    lib = setup()
     lib.write_manifest(f'{lib.top()}.json')

{lambdapdk-0.1.35 → lambdapdk-0.1.37}/lambdapdk/sky130/__init__.py

@@ -119,5 +119,5 @@ def setup():
 
 #########################
 if __name__ == "__main__":
-    pdk = setup(siliconcompiler.Chip('<pdk>'))
+    pdk = setup()
     pdk.write_manifest(f'{pdk.top()}.json')

{lambdapdk-0.1.35 → lambdapdk-0.1.37/lambdapdk.egg-info}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: lambdapdk
-Version: 0.1.35
+Version: 0.1.37
 Summary: Library of open source Process Design Kits
 Author: Zero ASIC
 License:                                  Apache License
@@ -203,8 +203,8 @@ Provides-Extra: test
 Requires-Dist: flake8==7.1.1; extra == "test"
 Requires-Dist: pytest==8.3.3; extra == "test"
 Requires-Dist: pytest-timeout==2.3.1; extra == "test"
-Requires-Dist: tclint==0.4.1; extra == "test"
-Requires-Dist: lambdalib==0.2.10; extra == "test"
+Requires-Dist: tclint==0.4.2; extra == "test"
+Requires-Dist: lambdalib==0.3.0; extra == "test"
 Requires-Dist: sc-leflib==0.4.0; extra == "test"
 
 # Lambdapdk Introduction

{lambdapdk-0.1.35 → lambdapdk-0.1.37}/lambdapdk.egg-info/requires.txt

@@ -4,6 +4,6 @@ siliconcompiler>=0.27.0
 flake8==7.1.1
 pytest==8.3.3
 pytest-timeout==2.3.1
-tclint==0.4.1
-lambdalib==0.2.10
+tclint==0.4.2
+lambdalib==0.3.0
 sc-leflib==0.4.0

{lambdapdk-0.1.35 → lambdapdk-0.1.37}/pyproject.toml

@@ -30,8 +30,8 @@ test = [
     "flake8 == 7.1.1",
     "pytest == 8.3.3",
     "pytest-timeout == 2.3.1",
-    "tclint == 0.4.1",
-    "lambdalib == 0.2.10",
+    "tclint == 0.4.2",
+    "lambdalib == 0.3.0",
     "sc-leflib == 0.4.0"
 ]
 

{lambdapdk-0.1.35 → lambdapdk-0.1.37}/tests/test_lambda.py

@@ -1,4 +1,5 @@
 import pytest
+import os
 from siliconcompiler import Chip
 import lambdalib
 
@@ -16,7 +17,7 @@ from lambdapdk.ihp130.libs import sg13g2_stdcell, sg13g2_sram
     (gf180mcu, 'lambdapdk/gf180/libs/{lib_name}/lambda/auxlib'),
     (sg13g2_stdcell, 'lambdapdk/ihp130/libs/{lib_name}/lambda/auxlib')
     ])
-def test_la_auxlib(module, path):
+def test_la_auxlib(module, path, rootdir):
     libs = module.setup()
     if not isinstance(libs, list):
         libs = [libs]
@@ -24,7 +25,8 @@ def test_la_auxlib(module, path):
         lib_name = lib.design
         if "lambdalib" in lib_name:
             continue
-        assert lambdalib.check(path.format(lib_name=lib_name), 'auxlib')
+        assert lambdalib.check(
+            os.path.join(rootdir, path.format(lib_name=lib_name)), 'auxlib')
 
 
 @pytest.mark.parametrize('module,path', [
@@ -34,7 +36,7 @@ def test_la_auxlib(module, path):
     (gf180mcu, 'lambdapdk/gf180/libs/{lib_name}/lambda/stdlib'),
     (sg13g2_stdcell, 'lambdapdk/ihp130/libs/{lib_name}/lambda/stdlib')
     ])
-def test_la_stdlib(module, path):
+def test_la_stdlib(module, path, rootdir):
     libs = module.setup()
     if not isinstance(libs, list):
         libs = [libs]
@@ -42,7 +44,8 @@ def test_la_stdlib(module, path):
         lib_name = lib.design
         if "lambdalib" in lib_name:
             continue
-        assert lambdalib.check(path.format(lib_name=lib_name), 'stdlib')
+        assert lambdalib.check(
+            os.path.join(rootdir, path.format(lib_name=lib_name)), 'stdlib')
 
 
 @pytest.mark.parametrize('path', [
@@ -52,8 +55,9 @@ def test_la_stdlib(module, path):
     'lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda',
     'lambdapdk/ihp130/libs/sg13g2_sram/lambda',
     ])
-def test_la_ramlib(path):
-    assert lambdalib.check(path, 'ramlib')
+def test_la_ramlib(path, rootdir):
+    assert lambdalib.check(
+        os.path.join(rootdir, path), 'ramlib')
 
 
 @pytest.mark.parametrize('path', [
@@ -61,8 +65,9 @@ def test_la_ramlib(path):
     'lambdapdk/gf180/libs/gf180mcu_fd_io/lambda',
     'lambdapdk/asap7/libs/fakeio7/lambda',
     ])
-def test_la_iolib(path):
-    assert lambdalib.check(path, 'iolib')
+def test_la_iolib(path, rootdir):
+    assert lambdalib.check(
+        os.path.join(rootdir, path), 'iolib')
 
 
 @pytest.mark.parametrize('module', [