lambdapdk 0.1.31__tar.gz → 0.1.32__tar.gz

{lambdapdk-0.1.31/lambdapdk.egg-info → lambdapdk-0.1.32}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: lambdapdk
-Version: 0.1.31
+Version: 0.1.32
 Summary: Library of open source Process Design Kits
 Author: Zero ASIC
 License:                                  Apache License
@@ -201,10 +201,10 @@ License-File: LICENSE
 Requires-Dist: siliconcompiler>=0.27.0
 Provides-Extra: test
 Requires-Dist: flake8==7.1.1; extra == "test"
-Requires-Dist: pytest==8.3.2; extra == "test"
+Requires-Dist: pytest==8.3.3; extra == "test"
 Requires-Dist: pytest-timeout==2.3.1; extra == "test"
-Requires-Dist: tclint==0.3.2; extra == "test"
-Requires-Dist: lambdalib==0.2.9; extra == "test"
+Requires-Dist: tclint==0.4.0; extra == "test"
+Requires-Dist: lambdalib==0.2.10; extra == "test"
 Requires-Dist: sc-leflib==0.4.0; extra == "test"
 
 # Lambdapdk Introduction
@@ -220,6 +220,7 @@ Supported PDKs:
 * [FreePDK45](lambdapdk/freepdk45/base/README.md)
 * [Skywater130](lambdapdk/sky130/base/README.md)
 * [Global Foundries 180](lambdapdk/gf180/README.md)
+* [IHP 180](https://github.com/IHP-GmbH/IHP-Open-PDK)
 
 # License
 

{lambdapdk-0.1.31 → lambdapdk-0.1.32}/README.md

@@ -11,6 +11,7 @@ Supported PDKs:
 * [FreePDK45](lambdapdk/freepdk45/base/README.md)
 * [Skywater130](lambdapdk/sky130/base/README.md)
 * [Global Foundries 180](lambdapdk/gf180/README.md)
+* [IHP 180](https://github.com/IHP-GmbH/IHP-Open-PDK)
 
 # License
 

{lambdapdk-0.1.31 → lambdapdk-0.1.32}/lambdapdk/__init__.py

@@ -1,7 +1,7 @@
 import siliconcompiler.package as sc_package
 
 
-__version__ = "0.1.31"
+__version__ = "0.1.32"
 
 
 def register_data_source(chip):
@@ -20,10 +20,10 @@ def get_pdks():
     Returns a list of pdk names in lambdapdk
     '''
 
-    from lambdapdk import asap7, freepdk45, sky130, gf180
+    from lambdapdk import asap7, freepdk45, sky130, gf180, ihp130
 
     all_pdks = []
-    for pdk_mod in [asap7, freepdk45, sky130, gf180]:
+    for pdk_mod in [asap7, freepdk45, sky130, gf180, ihp130]:
         pdks = pdk_mod.setup()
         if not isinstance(pdks, (list, tuple)):
             pdks = [pdks]
@@ -38,17 +38,19 @@ def get_libs():
     Returns a list of libraries names in lambdapdk
     '''
 
-    from lambdapdk.asap7.libs import asap7sc7p5t, fakeram7
+    from lambdapdk.asap7.libs import asap7sc7p5t, fakeram7, fakeio7
     from lambdapdk.freepdk45.libs import nangate45, fakeram45
     from lambdapdk.sky130.libs import sky130sc, sky130io, sky130sram
     from lambdapdk.gf180.libs import gf180mcu, gf180io, gf180sram
+    from lambdapdk.ihp130.libs import sg13g2_stdcell, sg13g2_sram
 
     all_libs = []
     for lib_mod in [
-            asap7sc7p5t, fakeram7,
+            asap7sc7p5t, fakeram7, fakeio7,
             nangate45, fakeram45,
             sky130sc, sky130io, sky130sram,
-            gf180mcu, gf180io, gf180sram]:
+            gf180mcu, gf180io, gf180sram,
+            sg13g2_stdcell, sg13g2_sram]:
         libs = lib_mod.setup()
         if not isinstance(libs, (list, tuple)):
             libs = [libs]

lambdapdk-0.1.32/lambdapdk/ihp130/__init__.py

@@ -0,0 +1,133 @@
+
+import os
+import siliconcompiler
+from lambdapdk import register_data_source
+
+
+pdk_rev = '89c8038db331ccfdf6be488dfc4670cb62ba3c42'
+
+
+def register_ihp130_data_source(chip):
+    chip.register_source(
+        'ihp130',
+        path='git+https://github.com/IHP-GmbH/IHP-Open-PDK',
+        ref=pdk_rev)
+
+
+####################################################
+# PDK Setup
+####################################################
+def setup():
+    '''
+    130nm BiCMOS Open Source PDK, dedicated for Analog/Digital, Mixed Signal and RF Design
+
+    IHP Open Source PDK project goal is to provide a fully open source Process Design Kit and
+    related data, which can be used to create manufacturable designs at IHP's facility.
+
+    SG13G2 is a high performance BiCMOS technology with a 0.13 μm CMOS process.
+    It contains bipolar devices based on SiGe:C npn-HBT's with up to 350 GHz transition frequency
+    (fT) and 450 GHz oscillation frequency (fmax).
+    This process provides 2 gate oxides:
+    A thin gate oxide for the 1.2 V digital logic and a thick oxide for a 3.3 V supply voltage.
+    For both modules NMOS, PMOS and isolated NMOS transistors are offered.
+    Further passive components like poly silicon resistors and MIM capacitors are available.
+    The backend option offers 5 thin metal layers, two thick metal layers (2 and 3 μm thick) and
+    a MIM layer.
+
+    Sources:
+
+    * https://github.com/IHP-GmbH/IHP-Open-PDK
+    '''
+
+    foundry = 'Leibniz-Institut für innovative Mikroelektronik'
+    process = 'ihp130'
+    stackup = '5M2TL'
+
+    node = 130
+    # TODO: dummy numbers, only matter for cost estimation
+    wafersize = 300
+    hscribe = 0.1
+    vscribe = 0.1
+    edgemargin = 2
+
+    lpdkdir = os.path.join('lambdapdk', 'ihp130', 'base')
+
+    pdk = siliconcompiler.PDK(process, package='ihp130')
+    register_ihp130_data_source(pdk)
+    register_data_source(pdk)
+
+    # process name
+    pdk.set('pdk', process, 'foundry', foundry)
+    pdk.set('pdk', process, 'node', node)
+    pdk.set('pdk', process, 'version', pdk_rev)
+    pdk.set('pdk', process, 'stackup', stackup)
+    pdk.set('pdk', process, 'wafersize', wafersize)
+    pdk.set('pdk', process, 'edgemargin', edgemargin)
+    pdk.set('pdk', process, 'scribe', (hscribe, vscribe))
+
+    # APR Setup
+    # TODO: remove libtype
+    for tool in ('openroad', 'klayout', 'magic'):
+        # Add unithd for backwards compatibility
+        pdk.set('pdk', process, 'aprtech', tool, stackup, '9t', 'lef',
+                'ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_tech.lef')
+
+    pdk.set('pdk', process, 'minlayer', stackup, 'Metal2')
+    pdk.set('pdk', process, 'maxlayer', stackup, 'Metal5')
+
+    # DRC Runsets
+#     pdk.set('pdk', process, 'drc', 'runset', 'magic', stackup, 'basic',
+#             pdkdir + '/setup/magic/sky130A.tech')
+
+    # LVS Runsets
+#     pdk.set('pdk', process, 'lvs', 'runset', 'netgen', stackup, 'basic',
+#             pdkdir + '/setup/netgen/lvs_setup.tcl')
+
+    # Layer map and display file
+    pdk.set('pdk', process, 'layermap', 'klayout', 'def', 'klayout', stackup,
+            'ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt')
+    pdk.set('pdk', process, 'display', 'klayout', stackup,
+            'ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyp')
+
+    pdk.set('pdk', process, 'layermap', 'klayout', 'def', 'gds', stackup,
+            'ihp-sg13g2/libs.tech/klayout/tech/sg13g2.map')
+
+    # Openroad global routing grid derating
+    openroad_layer_adjustments = {
+        'Metal1': 0.05,
+        'Metal2': 0.05,
+        'Metal3': 0.05,
+        'Metal4': 0.05,
+        'Metal5': 0.05,
+        'TopMetal1': 0.00,
+        'TopMetal2': 0.00,
+    }
+    for layer, adj in openroad_layer_adjustments.items():
+        pdk.set('pdk', process, 'var', 'openroad', f'{layer}_adjustment', stackup, str(adj))
+
+    pdk.set('pdk', process, 'var', 'openroad', 'rclayer_signal', stackup, 'Metal2')
+    pdk.set('pdk', process, 'var', 'openroad', 'rclayer_clock', stackup, 'Metal5')
+
+    pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_vertical', stackup, 'Metal3')
+    pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_horizontal', stackup, 'Metal2')
+
+    # PEX
+    for corner in ["typical"]:
+        pdk.set('pdk', process, 'pexmodel', 'openroad', stackup, corner,
+                lpdkdir + '/pex/openroad/' + corner + '.tcl', package='lambdapdk')
+        pdk.set('pdk', process, 'pexmodel', 'openroad-openrcx', stackup, corner,
+                lpdkdir + '/pex/openroad/' + corner + '.rules', package='lambdapdk')
+
+    # Documentation
+    pdk.set('pdk', process, 'doc', 'overview',
+            'ihp-sg13g2/libs.doc/doc/SG13G2_os_process_spec.pdf')
+    pdk.set('pdk', process, 'doc', 'drc_rules',
+            'ihp-sg13g2/libs.doc/doc/SG13G2_os_layout_rules.pdf')
+
+    return pdk
+
+
+#########################
+if __name__ == "__main__":
+    pdk = setup(siliconcompiler.Chip('<pdk>'))
+    pdk.write_manifest(f'{pdk.top()}.json')

lambdapdk-0.1.32/lambdapdk/ihp130/libs/sg13g2_sram.py

@@ -0,0 +1,46 @@
+from siliconcompiler import Chip, Library
+from lambdapdk import register_data_source
+from lambdapdk.ihp130 import register_ihp130_data_source
+
+
+def setup():
+    libs = []
+    stackup = '5M2TL'
+
+    for config in ('1024x64', '2048x64', '256x48', '256x64', '512x64', '64x64'):
+        mem_name = f'RM_IHPSG13_1P_{config}_c2_bm_bist'
+        lib = Library(mem_name, package='ihp130')
+        register_ihp130_data_source(lib)
+        register_data_source(lib)
+        path_base = 'ihp-sg13g2/libs.ref/sg13g2_sram'
+        lib.add('output', stackup, 'lef', f'{path_base}/lef/{mem_name}.lef')
+        lib.add('output', stackup, 'gds', f'{path_base}/gds/{mem_name}.gds')
+        lib.add('output', stackup, 'cdl', f'{path_base}/spice/{mem_name}.cdl')
+
+        lib.add('output', 'typ', 'nldm', f'{path_base}/lib/{mem_name}_typ_1p20V_25C.lib')
+        lib.add('output', 'slow', 'nldm', f'{path_base}/lib/{mem_name}_slow_1p08V_125C.lib')
+        lib.add('output', 'fast', 'nldm', f'{path_base}/lib/{mem_name}_fast_1p32V_m55C.lib')
+
+        lib.add('output', 'rtl', 'verilog', f'{path_base}/verilog/{mem_name}.v')
+        lib.add('output', 'rtl', 'verilog',
+                f'{path_base}/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v')
+
+        lib.set('option', 'file', 'openroad_pdngen',
+                'lambdapdk/ihp130/libs/sg13g2_sram/pdngen.tcl',
+                package='lambdapdk')
+
+        libs.append(lib)
+
+    lambda_lib = Library('lambdalib_sg13g2_sram', package='lambdapdk')
+    register_data_source(lambda_lib)
+    lambda_lib.add('option', 'ydir', 'lambdapdk/ihp130/libs/sg13g2_sram/lambda')
+
+    libs.append(lambda_lib)
+
+    return libs
+
+
+#########################
+if __name__ == "__main__":
+    for lib in setup(Chip('<lib>')):
+        lib.write_manifest(f'{lib.top()}.json')

lambdapdk-0.1.32/lambdapdk/ihp130/libs/sg13g2_stdcell.py

@@ -0,0 +1,135 @@
+import os
+import siliconcompiler
+from lambdapdk import register_data_source
+from lambdapdk.ihp130 import register_ihp130_data_source
+
+
+def setup():
+    '''
+    Nangate open standard cell library for FreePDK45.
+    '''
+    libname = 'sg13g2_stdcell'
+    process = 'ihp130'
+    stackup = '5M2TL'
+    libtype = '9t'
+    version = 'r1p0'
+
+    lib = siliconcompiler.Library(libname, package='ihp130')
+    register_ihp130_data_source(lib)
+    register_data_source(lib)
+
+    libdir = os.path.join('lambdapdk', process, 'libs', libname)
+
+    # version
+    lib.set('package', 'version', version)
+
+    # list of stackups supported
+    lib.set('option', 'stackup', stackup)
+
+    # list of pdks supported
+    lib.set('option', 'pdk', process)
+
+    # footprint/type/sites
+    lib.set('asic', 'libarch', libtype)
+    lib.set('asic', 'site', libtype, 'CoreSite')
+
+    # timing
+    lib.add('output', 'typ', 'nldm',
+            'ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p20V_25C.lib')
+    lib.add('output', 'fast', 'nldm',
+            'ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_fast_1p32V_m40C.lib')
+    lib.add('output', 'slow', 'nldm',
+            'ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_slow_1p08V_125C.lib')
+
+    # lef
+    lib.add('output', stackup, 'lef',
+            'ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_stdcell.lef')
+
+    # gds
+    lib.add('output', stackup, 'gds',
+            'ihp-sg13g2/libs.ref/sg13g2_stdcell/gds/sg13g2_stdcell.gds')
+
+    # cdl
+    lib.add('output', stackup, 'cdl',
+            'ihp-sg13g2/libs.ref/sg13g2_stdcell/cdl/sg13g2_stdcell.cdl')
+
+    lib.add('output', 'rtl', 'verilog',
+            'ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v')
+
+    # clock buffers
+    lib.add('asic', 'cells', 'clkbuf', ["sg13g2_buf_2",
+                                        "sg13g2_buf_4"])
+
+    # tie cells
+    lib.add('asic', 'cells', 'tie', ["LOGIC1_X1",
+                                     "LOGIC0_X1"])
+
+    # hold cells
+    lib.add('asic', 'cells', 'hold', ["sg13g2_buf_1",
+                                      "sg13g2_buf_4"])
+
+    # filler
+    lib.add('asic', 'cells', 'filler', ["sg13g2_fill_1",
+                                        "sg13g2_fill_2"])
+
+    # decap
+    lib.add('asic', 'cells', 'decap', ["sg13g2_decap_4",
+                                       "sg13g2_decap_8"])
+
+    # antenna
+    lib.add('asic', 'cells', 'antenna', ["sg13g2_antennanp"])
+
+    # Stupid small cells
+    lib.add('asic', 'cells', 'dontuse', ["sg13g2_antennanp",
+                                         "sg13g2_lgcp_1",
+                                         "sg13g2_sighold",
+                                         "sg13g2_slgcp_1",
+                                         "sg13g2_dfrbp_2"])
+
+    # Techmap
+    lib.add('option', 'file', 'yosys_techmap',
+            libdir + '/techmap/yosys/cells_latch.v',
+            package='lambdapdk')
+
+    # Defaults for OpenROAD tool variables
+    lib.set('option', 'var', 'openroad_place_density', '0.65')
+    lib.set('option', 'var', 'openroad_pad_global_place', '0')
+    lib.set('option', 'var', 'openroad_pad_detail_place', '0')
+    lib.set('option', 'var', 'openroad_macro_place_halo', ['40', '40'])
+    lib.set('option', 'var', 'openroad_macro_place_channel', ['80', '80'])
+
+    lib.set('option', 'file', 'openroad_tapcells', libdir + '/apr/openroad/tapcell.tcl',
+            package='lambdapdk')
+    lib.set('option', 'file', 'openroad_pdngen', libdir + '/apr/openroad/pdngen.tcl',
+            package='lambdapdk')
+    lib.set('option', 'file', 'openroad_global_connect',
+            libdir + '/apr/openroad/global_connect.tcl',
+            package='lambdapdk')
+
+    lib.set('option', 'var', 'yosys_abc_clock_multiplier', "1000")  # convert from ns -> ps
+    lib.set('option', 'var', 'yosys_abc_constraint_load', "6.0fF")  # BUF_X1 = 0.974659 x 4
+    lib.set('option', 'var', 'yosys_driver_cell', "sg13g2_buf_4")
+    lib.set('option', 'var', 'yosys_buffer_cell', "sg13g2_buf_4")
+    lib.set('option', 'var', 'yosys_buffer_input', "A")
+    lib.set('option', 'var', 'yosys_buffer_output', "X")
+    for tool in ('yosys', 'openroad'):
+        lib.set('option', 'var', f'{tool}_tiehigh_cell', "sg13g2_tiehi")
+        lib.set('option', 'var', f'{tool}_tiehigh_port', "L_HI")
+        lib.set('option', 'var', f'{tool}_tielow_cell', "sg13g2_tielo")
+        lib.set('option', 'var', f'{tool}_tielow_port', "L_LO")
+
+    libs = [lib]
+    for libtype in ('stdlib', 'auxlib'):
+        lambda_lib = siliconcompiler.Library(f'lambdalib_{libtype}_{libname}',
+                                             package='lambdapdk')
+        register_data_source(lambda_lib)
+        lambda_lib.add('option', 'ydir', libdir + f'/lambda/{libtype}')
+        libs.append(lambda_lib)
+
+    return libs
+
+
+#########################
+if __name__ == "__main__":
+    lib = setup(siliconcompiler.Chip('<lib>'))
+    lib.write_manifest(f'{lib.top()}.json')

{lambdapdk-0.1.31 → lambdapdk-0.1.32/lambdapdk.egg-info}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: lambdapdk
-Version: 0.1.31
+Version: 0.1.32
 Summary: Library of open source Process Design Kits
 Author: Zero ASIC
 License:                                  Apache License
@@ -201,10 +201,10 @@ License-File: LICENSE
 Requires-Dist: siliconcompiler>=0.27.0
 Provides-Extra: test
 Requires-Dist: flake8==7.1.1; extra == "test"
-Requires-Dist: pytest==8.3.2; extra == "test"
+Requires-Dist: pytest==8.3.3; extra == "test"
 Requires-Dist: pytest-timeout==2.3.1; extra == "test"
-Requires-Dist: tclint==0.3.2; extra == "test"
-Requires-Dist: lambdalib==0.2.9; extra == "test"
+Requires-Dist: tclint==0.4.0; extra == "test"
+Requires-Dist: lambdalib==0.2.10; extra == "test"
 Requires-Dist: sc-leflib==0.4.0; extra == "test"
 
 # Lambdapdk Introduction
@@ -220,6 +220,7 @@ Supported PDKs:
 * [FreePDK45](lambdapdk/freepdk45/base/README.md)
 * [Skywater130](lambdapdk/sky130/base/README.md)
 * [Global Foundries 180](lambdapdk/gf180/README.md)
+* [IHP 180](https://github.com/IHP-GmbH/IHP-Open-PDK)
 
 # License
 

{lambdapdk-0.1.31 → lambdapdk-0.1.32}/lambdapdk.egg-info/SOURCES.txt

@@ -18,6 +18,9 @@ lambdapdk/gf180/__init__.py
 lambdapdk/gf180/libs/gf180io.py
 lambdapdk/gf180/libs/gf180mcu.py
 lambdapdk/gf180/libs/gf180sram.py
+lambdapdk/ihp130/__init__.py
+lambdapdk/ihp130/libs/sg13g2_sram.py
+lambdapdk/ihp130/libs/sg13g2_stdcell.py
 lambdapdk/sky130/__init__.py
 lambdapdk/sky130/libs/sky130io.py
 lambdapdk/sky130/libs/sky130sc.py

{lambdapdk-0.1.31 → lambdapdk-0.1.32}/lambdapdk.egg-info/requires.txt

@@ -2,8 +2,8 @@ siliconcompiler>=0.27.0
 
 [test]
 flake8==7.1.1
-pytest==8.3.2
+pytest==8.3.3
 pytest-timeout==2.3.1
-tclint==0.3.2
-lambdalib==0.2.9
+tclint==0.4.0
+lambdalib==0.2.10
 sc-leflib==0.4.0

{lambdapdk-0.1.31 → lambdapdk-0.1.32}/pyproject.toml

@@ -22,16 +22,16 @@ version = {attr = "lambdapdk.__version__"}
 
 [tool.pytest.ini_options]
 testpaths = "tests"
-timeout = "60"
+timeout = "180"
 
 [project.optional-dependencies]
 # Test dependencies.
 test = [
     "flake8 == 7.1.1",
-    "pytest == 8.3.2",
+    "pytest == 8.3.3",
     "pytest-timeout == 2.3.1",
-    "tclint == 0.3.2",
-    "lambdalib == 0.2.9",
+    "tclint == 0.4.0",
+    "lambdalib == 0.2.10",
     "sc-leflib == 0.4.0"
 ]
 
@@ -40,6 +40,7 @@ exclude = [
     'build',
     'scripts/build',
     'dist',
+    '.venv/',
     # scripts from other repos
     'lambdapdk/asap7/base/apr/example_innovus.tcl',
     'lambdapdk/sky130/base/setup/netgen/lvs_setup.tcl',

{lambdapdk-0.1.31 → lambdapdk-0.1.32}/tests/test_getters.py

@@ -2,14 +2,15 @@ import pytest
 from siliconcompiler import Chip
 import lambdapdk
 
-from lambdapdk import asap7, freepdk45, sky130, gf180
-from lambdapdk.asap7.libs import asap7sc7p5t, fakeram7
+from lambdapdk import asap7, freepdk45, sky130, gf180, ihp130
+from lambdapdk.asap7.libs import asap7sc7p5t, fakeram7, fakeio7
 from lambdapdk.freepdk45.libs import nangate45, fakeram45
 from lambdapdk.sky130.libs import sky130sc, sky130io, sky130sram
 from lambdapdk.gf180.libs import gf180mcu, gf180io, gf180sram
+from lambdapdk.ihp130.libs import sg13g2_stdcell, sg13g2_sram
 
 
-@pytest.mark.parametrize('pdk', [asap7, freepdk45, sky130, gf180])
+@pytest.mark.parametrize('pdk', [asap7, freepdk45, sky130, gf180, ihp130])
 def test_pdk(pdk):
     chip = Chip('<pdk>')
     chip.use(pdk)
@@ -19,10 +20,11 @@ def test_pdk(pdk):
 
 
 @pytest.mark.parametrize('lib', [
-    asap7sc7p5t, fakeram7,  # asap7
+    asap7sc7p5t, fakeram7, fakeio7,  # asap7
     nangate45, fakeram45,  # freepdk45
     sky130sc, sky130io, sky130sram,  # sky130
-    gf180mcu, gf180io, gf180sram  # gf180
+    gf180mcu, gf180io, gf180sram,  # gf180
+    sg13g2_stdcell, sg13g2_sram  # ihp130
     ])
 def test_lib(lib):
     chip = Chip('<lib>')

{lambdapdk-0.1.31 → lambdapdk-0.1.32}/tests/test_lambda.py

@@ -6,13 +6,15 @@ from lambdapdk.asap7.libs import asap7sc7p5t, fakeram7
 from lambdapdk.freepdk45.libs import nangate45, fakeram45
 from lambdapdk.gf180.libs import gf180mcu, gf180io, gf180sram
 from lambdapdk.sky130.libs import sky130sc, sky130io, sky130sram
+from lambdapdk.ihp130.libs import sg13g2_stdcell, sg13g2_sram
 
 
 @pytest.mark.parametrize('module,path', [
     (asap7sc7p5t, 'lambdapdk/asap7/libs/{lib_name}/lambda/auxlib'),
     (nangate45, 'lambdapdk/freepdk45/libs/{lib_name}/lambda/auxlib'),
     (sky130sc, 'lambdapdk/sky130/libs/{lib_name}/lambda/auxlib'),
-    (gf180mcu, 'lambdapdk/gf180/libs/{lib_name}/lambda/auxlib')
+    (gf180mcu, 'lambdapdk/gf180/libs/{lib_name}/lambda/auxlib'),
+    (sg13g2_stdcell, 'lambdapdk/ihp130/libs/{lib_name}/lambda/auxlib')
     ])
 def test_la_auxlib(module, path):
     libs = module.setup()
@@ -29,7 +31,8 @@ def test_la_auxlib(module, path):
     (asap7sc7p5t, 'lambdapdk/asap7/libs/{lib_name}/lambda/stdlib'),
     (nangate45, 'lambdapdk/freepdk45/libs/{lib_name}/lambda/stdlib'),
     (sky130sc, 'lambdapdk/sky130/libs/{lib_name}/lambda/stdlib'),
-    (gf180mcu, 'lambdapdk/gf180/libs/{lib_name}/lambda/stdlib')
+    (gf180mcu, 'lambdapdk/gf180/libs/{lib_name}/lambda/stdlib'),
+    (sg13g2_stdcell, 'lambdapdk/ihp130/libs/{lib_name}/lambda/stdlib')
     ])
 def test_la_stdlib(module, path):
     libs = module.setup()
@@ -47,6 +50,7 @@ def test_la_stdlib(module, path):
     'lambdapdk/freepdk45/libs/fakeram45/lambda',
     'lambdapdk/sky130/libs/sky130sram/lambda',
     'lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda',
+    'lambdapdk/ihp130/libs/sg13g2_sram/lambda',
     ])
 def test_la_ramlib(path):
     assert lambdalib.check(path, 'ramlib')
@@ -55,6 +59,7 @@ def test_la_ramlib(path):
 @pytest.mark.parametrize('path', [
     'lambdapdk/sky130/libs/sky130io/lambda',
     'lambdapdk/gf180/libs/gf180mcu_fd_io/lambda',
+    'lambdapdk/asap7/libs/fakeio7/lambda',
     ])
 def test_la_iolib(path):
     assert lambdalib.check(path, 'iolib')
@@ -64,7 +69,8 @@ def test_la_iolib(path):
     asap7sc7p5t, fakeram7,
     nangate45, fakeram45,
     gf180mcu, gf180io, gf180sram,
-    sky130sc, sky130io, sky130sram
+    sky130sc, sky130io, sky130sram,
+    sg13g2_stdcell, sg13g2_sram
 ])
 def test_lambdalib_is_present(module):
     chip = Chip('<lib>')

{lambdapdk-0.1.31 → lambdapdk-0.1.32}/tests/test_paths.py

@@ -2,14 +2,16 @@ import pytest
 from siliconcompiler import Chip
 import os
 
-from lambdapdk import asap7, freepdk45, sky130, gf180
-from lambdapdk.asap7.libs import asap7sc7p5t, fakeram7
+from lambdapdk import asap7, freepdk45, sky130, gf180, ihp130
+from lambdapdk.asap7.libs import asap7sc7p5t, fakeram7, fakeio7
 from lambdapdk.freepdk45.libs import nangate45, fakeram45
 from lambdapdk.sky130.libs import sky130sc, sky130io, sky130sram
 from lambdapdk.gf180.libs import gf180mcu, gf180io, gf180sram
+from lambdapdk.ihp130.libs import sg13g2_stdcell
 
 
-@pytest.mark.parametrize('pdk', [asap7, freepdk45, sky130, gf180])
+@pytest.mark.parametrize('pdk', [
+    asap7, freepdk45, sky130, gf180, ihp130])
 def test_pdk_paths(pdk):
     chip = Chip('<pdk>')
     chip.use(pdk)
@@ -17,10 +19,11 @@ def test_pdk_paths(pdk):
 
 
 @pytest.mark.parametrize('lib', [
-    asap7sc7p5t, fakeram7,  # asap7
+    asap7sc7p5t, fakeram7, fakeio7,  # asap7
     nangate45, fakeram45,  # freepdk45
     sky130sc, sky130io, sky130sram,  # sky130
-    gf180mcu, gf180io, gf180sram  # gf180
+    gf180mcu, gf180io, gf180sram,  # gf180
+    sg13g2_stdcell  # ihp130
     ])
 def test_lib_paths(lib):
     chip = Chip('<lib>')