labview-fpga-hdl-tools 2.0.0.dev8__tar.gz → 2.0.0.dev9__tar.gz

{labview_fpga_hdl_tools-2.0.0.dev8 → labview_fpga_hdl_tools-2.0.0.dev9}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.3
 Name: labview-fpga-hdl-tools
-Version: 2.0.0.dev8
+Version: 2.0.0.dev9
 Summary: LabVIEW FPGA HDL Tools
 License: MIT
 Author: Salvador Santolucito
@@ -21,11 +21,17 @@ Description-Content-Type: text/markdown
 
 # LabVIEW FPGA HDL Tools
 
-Pre-release command-line tools (`nihdl`) for building customized FPGA designs
+Command-line tools (`nihdl`) for building customized FPGA designs
 for use with the ni/flexrio repository. They move, generate, and process the
 files needed to take a top-level HDL design to a LabVIEW FPGA bitfile through
 either of two compile flows (see below).
 
+> **Customizing a FlexRIO board? Start at [flexrio-custom](https://github.com/ni/flexrio-custom), not here.**
+> That repo is the front door — supported devices, machine setup, and the step-by-step
+> exercises. **This page is the tool reference** for the `nihdl` toolchain (commands,
+> settings, and the concepts behind them); use it to look things up while following the
+> flexrio-custom workflows.
+
 ## The two compile flows
 
 `nihdl` supports two ways to turn a top-level HDL design into a LabVIEW FPGA
@@ -128,7 +134,12 @@ step-by-step status with warnings and errors also shown inline; the end summary
 still appears, so verbose is additive to the default. See the
 [Command Reference](docs/CommandReference.md#output-and-verbosity) for details.
 
-## Quickstart: the Vivado compile flow
+## Quickstart: the Vivado compile flow (tool-only)
+
+> **Using `flexrio-custom`?** Follow its
+> [Getting Started exercises](https://github.com/ni/flexrio-custom/blob/main/docs/GettingStarted.md)
+> instead — they are the canonical command sequence for that repo. This quickstart is for
+> driving `nihdl` standalone (installed via `pip`, outside a flexrio-custom checkout).
 
 Run these from your target folder (the one with `nihdlsettings.py`), with the
 Python environment active (run `nisetup` once per terminal — see

{labview_fpga_hdl_tools-2.0.0.dev8 → labview_fpga_hdl_tools-2.0.0.dev9}/README.md

@@ -1,10 +1,16 @@
 # LabVIEW FPGA HDL Tools
 
-Pre-release command-line tools (`nihdl`) for building customized FPGA designs
+Command-line tools (`nihdl`) for building customized FPGA designs
 for use with the ni/flexrio repository. They move, generate, and process the
 files needed to take a top-level HDL design to a LabVIEW FPGA bitfile through
 either of two compile flows (see below).
 
+> **Customizing a FlexRIO board? Start at [flexrio-custom](https://github.com/ni/flexrio-custom), not here.**
+> That repo is the front door — supported devices, machine setup, and the step-by-step
+> exercises. **This page is the tool reference** for the `nihdl` toolchain (commands,
+> settings, and the concepts behind them); use it to look things up while following the
+> flexrio-custom workflows.
+
 ## The two compile flows
 
 `nihdl` supports two ways to turn a top-level HDL design into a LabVIEW FPGA
@@ -107,7 +113,12 @@ step-by-step status with warnings and errors also shown inline; the end summary
 still appears, so verbose is additive to the default. See the
 [Command Reference](docs/CommandReference.md#output-and-verbosity) for details.
 
-## Quickstart: the Vivado compile flow
+## Quickstart: the Vivado compile flow (tool-only)
+
+> **Using `flexrio-custom`?** Follow its
+> [Getting Started exercises](https://github.com/ni/flexrio-custom/blob/main/docs/GettingStarted.md)
+> instead — they are the canonical command sequence for that repo. This quickstart is for
+> driving `nihdl` standalone (installed via `pip`, outside a flexrio-custom checkout).
 
 Run these from your target folder (the one with `nihdlsettings.py`), with the
 Python environment active (run `nisetup` once per terminal — see

{labview_fpga_hdl_tools-2.0.0.dev8 → labview_fpga_hdl_tools-2.0.0.dev9}/labview_fpga_hdl_tools/gen_labview_target_plugin.py

@@ -227,6 +227,26 @@ def _create_clocklist_structure():
     return clock_list_top
 
 
+def _normalize_clock_domain_name(clock_domain_name):
+    """Return the canonical LabVIEW clock-domain name used in generated XML.
+
+    LabVIEW FPGA resource and clock names use dot-separated paths. CSV LVName
+    values use backslashes for hierarchy, so any hierarchical clock-domain
+    reference must be normalized before it is written to XML or compared to a
+    clock row defined elsewhere in the CSV.
+    """
+    return clock_domain_name.strip().replace("\\", ".")
+
+
+def _collect_defined_input_clock_domains(rows):
+    """Collect canonical clock-domain names defined by input clock rows."""
+    return {
+        _normalize_clock_domain_name(row["LVName"])
+        for row in rows
+        if row["SignalType"].lower() == "clock" and row["Direction"].lower() == "input"
+    }
+
+
 def _generate_xml_from_csv(csv_path, boardio_output_path, clock_output_path):
     """Generate boardio XML and clock XML files from CSV data.
 
@@ -254,9 +274,10 @@ def _generate_xml_from_csv(csv_path, boardio_output_path, clock_output_path):
 
         with open(csv_path, "r", newline="", encoding="utf-8") as csvfile:
             reader = csv.DictReader(csvfile)
+            rows = list(reader)
+            defined_input_clock_domains = _collect_defined_input_clock_domains(rows)
 
-            for row in reader:
-                row_count += 1
+            for row_count, row in enumerate(rows, start=1):
                 lv_name = row["LVName"]
                 hdl_name = row["HDLName"]
                 direction = row["Direction"]
@@ -266,6 +287,11 @@ def _generate_xml_from_csv(csv_path, boardio_output_path, clock_output_path):
                 zero_sync_regs = row["ZeroSyncRegs"]
                 output_readback = row["OutputReadback"]
                 required_clock_domain = row["RequiredClockDomain"]
+                normalized_required_clock_domain = (
+                    _normalize_clock_domain_name(required_clock_domain)
+                    if required_clock_domain
+                    else ""
+                )
 
                 # Replace the '\' in the names with '.' to create a dot-separated hierarchy
                 # that is used to make a resource folder hierarchy in the BoardIO XML.  The
@@ -317,9 +343,22 @@ def _generate_xml_from_csv(csv_path, boardio_output_path, clock_output_path):
                     )
                     ET.SubElement(io_resource, "VHDLName").text = hdl_name
 
-                    if required_clock_domain:
+                    if normalized_required_clock_domain:
+                        if (
+                            normalized_required_clock_domain not in defined_input_clock_domains
+                            and ("." in required_clock_domain or "\\" in required_clock_domain)
+                        ):
+                            valid_clock_domains = ", ".join(sorted(defined_input_clock_domains))
+                            error = (
+                                f"Row {row_count}: RequiredClockDomain='"
+                                f"{required_clock_domain}' for signal '{lv_name}' does not match "
+                                f"any input clock LVName defined in this CSV after the '\\' to '.' "
+                                f"name conversion. Use one of: {valid_clock_domains}"
+                            )
+                            validation_errors.append(error)
+
                         ET.SubElement(io_resource, "RequiredClockDomain").text = (
-                            required_clock_domain
+                            normalized_required_clock_domain
                         )
 
                     if use_in_scl:

{labview_fpga_hdl_tools-2.0.0.dev8 → labview_fpga_hdl_tools-2.0.0.dev9}/pyproject.toml

@@ -4,7 +4,7 @@ build-backend = "poetry.core.masonry.api"
 
 [tool.poetry]
 name = "labview-fpga-hdl-tools"
-version = "2.0.0.dev8"
+version = "2.0.0.dev9"
 description = "LabVIEW FPGA HDL Tools"
 authors = [
   "Salvador Santolucito <salvador.santolucito@gmail.com>"