labview-fpga-hdl-tools 2.0.0.dev6__tar.gz → 2.0.0.dev8__tar.gz

{labview_fpga_hdl_tools-2.0.0.dev6 → labview_fpga_hdl_tools-2.0.0.dev8}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.3
 Name: labview-fpga-hdl-tools
-Version: 2.0.0.dev6
+Version: 2.0.0.dev8
 Summary: LabVIEW FPGA HDL Tools
 License: MIT
 Author: Salvador Santolucito

{labview_fpga_hdl_tools-2.0.0.dev6 → labview_fpga_hdl_tools-2.0.0.dev8}/labview_fpga_hdl_tools/create_modelsim_project.py

@@ -472,51 +472,23 @@ def create_modelsim_project(overwrite=False, config=None):
 
     if config.skip_modelsim:
         reporter.detail(
-            "\nSKIP MODELSIM: Validation successful, skipping ModelSim project creation"
+            "\nSKIP MODELSIM: skipping ModelSim compilation "
+            "(will still validate sources and generate scripts)"
         )
-        return 0
 
-    # Step 0: Generate all configured VHDL from Mako templates (the
+    # Step 1: Generate all configured VHDL from Mako templates (the
     # PkgNiHdlSettings single-source-of-truth package and any other generated
-    # design sources). The simulation flow validates that every listed source
-    # file exists, so this must run before gathering source files.
-    reporter.detail("\nStep 0: Generating VHDL from templates...")
+    # design sources). These appear in the source lists validated below and need
+    # no ModelSim tools, so this runs in skip_modelsim (validation-only) mode too.
+    reporter.detail("\nStep 1: Generating VHDL from templates...")
     if generate_vhdl.gen_generated_vhdl(config=config) != 0:
         return 1
 
-    modelsim_install = config.modelsim_tools_folder
-    vlib_path = _get_modelsim_tool(modelsim_install, "vlib")
-    vcom_path = _get_modelsim_tool(modelsim_install, "vcom")
-
-    # Step 1: Create modelsim.ini
-    reporter.detail("\nStep 1: Creating modelsim.ini...")
-    ini_path = _create_modelsim_ini(modelsim_install, project_dir)
-
-    # Step 2: Add Xilinx simulation library mappings
-    xilinx_sim_lib = config.xilinx_sim_lib_folder
-    if xilinx_sim_lib:
-        reporter.detail("\nStep 2: Adding Xilinx simulation library mappings...")
-        # Ensure the Xilinx libraries exist before mapping them into the .ini.
-        # This is idempotent: once compiled it is a cheap no-op (and does not
-        # even require Vivado). Imported locally to avoid a circular import,
-        # since compile_modelsim_lib imports helpers from this module.
-        from labview_fpga_hdl_tools import compile_modelsim_lib
-
-        if compile_modelsim_lib.compile_modelsim_lib(config=config) != 0:
-            return 1
-        _add_xilinx_library_mappings(ini_path, xilinx_sim_lib)
-    else:
-        reporter.detail(
-            "\nStep 2: Skipping Xilinx library mappings (XilinxSimLibFolder not configured)"
-        )
-
-    # Step 3: Create work library
-    reporter.detail("\nStep 3: Creating work library...")
-    _run_modelsim_tool(vlib_path, ["work"], cwd=project_dir)
-    reporter.detail("  Created work library")
-
-    # Step 4: Gather VHDL source files
-    reporter.detail("\nStep 4: Gathering VHDL source files...")
+    # Step 2: Gather VHDL source files and validate that every listed file
+    # exists. Tool-independent, so this is the core project-integrity check that
+    # runs in skip_modelsim mode as well (it catches broken file lists / missing
+    # sources on a runner without ModelSim installed).
+    reporter.detail("\nStep 2: Gathering VHDL source files...")
 
     # ModelSim compiles its own file lists only (no fallback to the Vivado lists).
     file_lists = config.modelsim_file_lists
@@ -545,19 +517,63 @@ def create_modelsim_project(overwrite=False, config=None):
     reporter.detail(f"  Found {len(std_files)} standard VHDL files")
     reporter.detail(f"  Found {len(vhdl2008_files)} VHDL-2008 files")
 
-    # Step 5: Compile with vcom -autoorder (automatic dependency resolution)
-    reporter.detail("\nStep 5: Compiling VHDL files...")
+    # Step 3: Generate the load/sim .do scripts. These are static text scripts,
+    # so they are produced in skip_modelsim mode too. This is what lets a
+    # validation-only sim-modelsim confirm the project without ModelSim.
+    reporter.detail("\nStep 3: Generating simulation scripts...")
+    _generate_load_do_file(project_dir, entity_name)
+    _generate_sim_do_file(project_dir, entity_name)
+
+    # Everything below requires the ModelSim tools (vlib/vcom) and compiles the
+    # design. In skip_modelsim (validation-only) mode we stop here: settings,
+    # generated VHDL, source files, and .do scripts have all been validated or
+    # generated without needing ModelSim installed.
+    if config.skip_modelsim:
+        reporter.success(
+            "\nSKIP MODELSIM: Validation successful "
+            "(sources found, simulation scripts generated); skipping ModelSim compilation."
+        )
+        return 0
+
+    modelsim_install = config.modelsim_tools_folder
+    vlib_path = _get_modelsim_tool(modelsim_install, "vlib")
+    vcom_path = _get_modelsim_tool(modelsim_install, "vcom")
+
+    # Step 4: Create modelsim.ini
+    reporter.detail("\nStep 4: Creating modelsim.ini...")
+    ini_path = _create_modelsim_ini(modelsim_install, project_dir)
+
+    # Step 5: Add Xilinx simulation library mappings
+    xilinx_sim_lib = config.xilinx_sim_lib_folder
+    if xilinx_sim_lib:
+        reporter.detail("\nStep 5: Adding Xilinx simulation library mappings...")
+        # Ensure the Xilinx libraries exist before mapping them into the .ini.
+        # This is idempotent: once compiled it is a cheap no-op (and does not
+        # even require Vivado). Imported locally to avoid a circular import,
+        # since compile_modelsim_lib imports helpers from this module.
+        from labview_fpga_hdl_tools import compile_modelsim_lib
+
+        if compile_modelsim_lib.compile_modelsim_lib(config=config) != 0:
+            return 1
+        _add_xilinx_library_mappings(ini_path, xilinx_sim_lib)
+    else:
+        reporter.detail(
+            "\nStep 5: Skipping Xilinx library mappings (XilinxSimLibFolder not configured)"
+        )
+
+    # Step 6: Create work library
+    reporter.detail("\nStep 6: Creating work library...")
+    _run_modelsim_tool(vlib_path, ["work"], cwd=project_dir)
+    reporter.detail("  Created work library")
+
+    # Step 7: Compile with vcom -autoorder (automatic dependency resolution)
+    reporter.detail("\nStep 7: Compiling VHDL files...")
     try:
         _compile_vhdl_files(vcom_path, project_dir, std_files, vhdl2008_files, ini_path)
     except RuntimeError as e:
         reporter.error(f"\nCompilation failed: {e}")
         return 1
 
-    # Step 6: Generate .do files
-    reporter.detail("\nStep 6: Generating simulation scripts...")
-    _generate_load_do_file(project_dir, entity_name)
-    _generate_sim_do_file(project_dir, entity_name)
-
     total_files = len(std_files) + len(vhdl2008_files)
     reporter.success(f"\nModelSim project created successfully!")
     reporter.detail(f"  Directory: {project_dir}")

{labview_fpga_hdl_tools-2.0.0.dev6 → labview_fpga_hdl_tools-2.0.0.dev8}/labview_fpga_hdl_tools/install_dependencies.py

@@ -80,6 +80,36 @@ def _get_commit_hash(repo_path):
         return None
 
 
+def _get_installed_version(repo_name, repo_path, deps_dir):
+    """Return the currently installed version of a cloned dependency, or None.
+
+    Prefers the version recorded in the ``.dep-info`` marker file, falling back
+    to ``git describe`` for repos cloned before markers were introduced.
+    """
+    for marker in sorted(deps_dir.glob(f"{repo_name}-*{_DEP_INFO_SUFFIX}")):
+        try:
+            for line in marker.read_text(encoding="utf-8").splitlines():
+                if line.startswith("Version:"):
+                    return line.split(":", 1)[1].strip()
+        except OSError:
+            continue
+
+    try:
+        result = subprocess.run(
+            ["git", "-C", str(repo_path), "describe", "--tags", "--always"],
+            capture_output=True,
+            text=True,
+            check=True,
+        )
+        described = result.stdout.strip()
+        if described:
+            return _normalize_tag(described)
+    except (subprocess.CalledProcessError, OSError):
+        pass
+
+    return None
+
+
 def _write_dep_marker(repo, repo_name, tag, requested, repo_url, repo_path, deps_dir):
     """Write a version marker file next to a cloned dependency.
 
@@ -354,14 +384,22 @@ def _clone_repo_at_tag(repo, tag_or_spec, base_dir, delete_allowed=False, allow_
 
     # Check if already exists and prompt user
     if repo_path.exists():
-        reporter.detail(f"  [INFO] Repository {repo_name} already exists at {repo_path}")
+        installed_version = _get_installed_version(repo_name, repo_path, base_dir)
+        present_desc = (
+            f"{repo_name} version {installed_version}" if installed_version else repo_name
+        )
+        reporter.detail(f"  [INFO] {present_desc} already present at {repo_path}")
 
         if delete_allowed:
             response = "y"
             reporter.detail(f"    Auto-deleting and re-cloning (--delete flag set)")
         else:
             try:
-                response = input(f"    Delete and re-clone? (y/N): ").strip().lower()
+                response = (
+                    input(f"    {present_desc} already present. Delete and re-clone? (y/N): ")
+                    .strip()
+                    .lower()
+                )
             except EOFError:
                 # Non-interactive/CI run: there is no stdin to prompt on. Default
                 # to the safe "keep existing clone" choice instead of crashing;
@@ -397,7 +435,7 @@ def _clone_repo_at_tag(repo, tag_or_spec, base_dir, delete_allowed=False, allow_
             text=True,
             check=True,
         )
-        reporter.success(f"  [OK] Successfully cloned {repo_name}")
+        reporter.success(f"  [OK] Installed {repo_name} version {_normalize_tag(tag)}")
         _write_dep_marker(repo, repo_name, tag, tag_or_spec, repo_url, repo_path, base_dir)
         return True
 

{labview_fpga_hdl_tools-2.0.0.dev6 → labview_fpga_hdl_tools-2.0.0.dev8}/labview_fpga_hdl_tools/launch_modelsim.py

@@ -20,15 +20,16 @@ def _validate_ini(config):
     missing_settings = []
     invalid_paths = []
 
-    if not config.modelsim_tools_folder:
-        missing_settings.append("ModelSimSettings.ModelSimToolsFolder")
-    else:
-        vsim_exe = _get_vsim_executable(config.modelsim_tools_folder)
-        if not vsim_exe or not os.path.exists(vsim_exe):
-            invalid_paths.append(
-                f"ModelSimSettings.ModelSimToolsFolder - vsim not found under: "
-                f"{config.modelsim_tools_folder}"
-            )
+    if not config.skip_modelsim:
+        if not config.modelsim_tools_folder:
+            missing_settings.append("ModelSimSettings.ModelSimToolsFolder")
+        else:
+            vsim_exe = _get_vsim_executable(config.modelsim_tools_folder)
+            if not vsim_exe or not os.path.exists(vsim_exe):
+                invalid_paths.append(
+                    f"ModelSimSettings.ModelSimToolsFolder - vsim not found under: "
+                    f"{config.modelsim_tools_folder}"
+                )
 
     if not common.get_modelsim_entity(config):
         missing_settings.append("ModelSimSettings.ModelSimEntity (set via set_modelsim_top_entity)")

{labview_fpga_hdl_tools-2.0.0.dev6 → labview_fpga_hdl_tools-2.0.0.dev8}/labview_fpga_hdl_tools/sim_modelsim.py

@@ -21,15 +21,16 @@ def _validate_ini(config):
     missing_settings = []
     invalid_paths = []
 
-    if not config.modelsim_tools_folder:
-        missing_settings.append("ModelSimSettings.ModelSimToolsFolder")
-    else:
-        vsim_exe = _get_vsim_executable(config.modelsim_tools_folder)
-        if not vsim_exe or not os.path.exists(vsim_exe):
-            invalid_paths.append(
-                f"ModelSimSettings.ModelSimToolsFolder - vsim not found under: "
-                f"{config.modelsim_tools_folder}"
-            )
+    if not config.skip_modelsim:
+        if not config.modelsim_tools_folder:
+            missing_settings.append("ModelSimSettings.ModelSimToolsFolder")
+        else:
+            vsim_exe = _get_vsim_executable(config.modelsim_tools_folder)
+            if not vsim_exe or not os.path.exists(vsim_exe):
+                invalid_paths.append(
+                    f"ModelSimSettings.ModelSimToolsFolder - vsim not found under: "
+                    f"{config.modelsim_tools_folder}"
+                )
 
     if not common.get_modelsim_entity(config):
         missing_settings.append("ModelSimSettings.ModelSimEntity (set via set_modelsim_top_entity)")

{labview_fpga_hdl_tools-2.0.0.dev6 → labview_fpga_hdl_tools-2.0.0.dev8}/pyproject.toml

@@ -4,7 +4,7 @@ build-backend = "poetry.core.masonry.api"
 
 [tool.poetry]
 name = "labview-fpga-hdl-tools"
-version = "2.0.0.dev6"
+version = "2.0.0.dev8"
 description = "LabVIEW FPGA HDL Tools"
 authors = [
   "Salvador Santolucito <salvador.santolucito@gmail.com>"