labview-fpga-hdl-tools 2.0.0.dev3__tar.gz → 2.0.0.dev5__tar.gz

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/PKG-INFO

@@ -1,19 +1,19 @@
 Metadata-Version: 2.3
 Name: labview-fpga-hdl-tools
-Version: 2.0.0.dev3
+Version: 2.0.0.dev5
 Summary: LabVIEW FPGA HDL Tools
 License: MIT
 Author: Salvador Santolucito
 Author-email: salvador.santolucito@gmail.com
-Requires-Python: >=3.9,<4.0
+Requires-Python: >=3.10,<3.15
 Classifier: License :: OSI Approved :: MIT License
 Classifier: Programming Language :: Python :: 3
-Classifier: Programming Language :: Python :: 3.9
 Classifier: Programming Language :: Python :: 3.10
 Classifier: Programming Language :: Python :: 3.11
 Classifier: Programming Language :: Python :: 3.12
 Classifier: Programming Language :: Python :: 3.13
 Requires-Dist: click (>=8.1.8,<8.2)
+Requires-Dist: defusedxml (>=0.7.1)
 Requires-Dist: mako (>=1.3.10)
 Requires-Dist: packaging (>=21.0)
 Requires-Dist: tomli (>=1.1.0) ; python_version < "3.11"
@@ -39,6 +39,12 @@ run Vivado in the end — they differ in what compiles the bitfile:
   target (`gen-target` → `install-target`), then write a VI and let LabVIEW FPGA
   compile the bitfile (it runs Vivado under the hood).
 
+> **Host-side note:** to communicate with the compiled `.lvbitx` from a LabVIEW FPGA
+> host VI, open it with **Open Dynamic Bitfile Reference** (wire in the bitfile path and
+> a matching FPGA Interface Dynamic Refnum) — the standard **Open FPGA VI Reference**
+> node does **not** work with these custom targets. See
+> [Vivado Compile Flow → Opening the bitfile from a LabVIEW FPGA host VI](docs/VivadoCompileFlow.md#opening-the-bitfile-from-a-labview-fpga-host-vi).
+
 In short: in the **Vivado flow** you drive Vivado; in the **LabVIEW FPGA flow**
 LabVIEW FPGA drives Vivado for you. See
 [Theory of Operation](docs/TheoryOfOperation.md) for the full story.
@@ -48,9 +54,13 @@ LabVIEW FPGA drives Vivado for you. See
 | Doc | What's in it |
 | --- | --- |
 | [Theory of Operation](docs/TheoryOfOperation.md) | The architecture, the supported workflows, and how the pieces fit together. Start here. |
+| [Vivado Compile Flow](docs/VivadoCompileFlow.md) | End-to-end walkthrough: extend the HDL, generate a Vivado project, and compile a `.lvbitx` directly in Vivado. |
+| [LabVIEW FPGA Target and Compile Flow](docs/LabVIEWFpgaTargetFlow.md) | End-to-end walkthrough: build and install a custom LabVIEW FPGA target, then compile in LabVIEW FPGA. |
+| [ModelSim Simulation Flow](docs/ModelSimSimulationFlow.md) | End-to-end walkthrough: build the Xilinx sim libraries, create the ModelSim project, and run a testbench. |
 | [Command Reference](docs/CommandReference.md) | Every `nihdl` command, its options, the command flow, and per-command required settings. |
 | [Settings Reference](docs/SettingsReference.md) | The `nihdlsettings.py` model: hooks, context, `--set` overrides, and the full list of setters. |
 | [LVTargetCustomIO Reference](docs/LVTargetCustomIO-Reference.md) | The custom I/O CSV format used to define HDL ↔ LabVIEW FPGA signals. |
+| [Generated VHDL](docs/GeneratedVHDL.md) | What VHDL the tools generate (window wrappers, `PkgNiHdlSettings`) and why — single-sourcing the facts shared by the HDL and the LabVIEW FPGA target. |
 | [Window Netlist and Constraints](docs/WindowNetlistAndConstraints.md) | How the LabVIEW Window netlist is produced/consumed and how XDC constraints are processed for each compile flow (including the `current_instance` scoping rules). |
 
 ## Prerequisites
@@ -66,8 +76,8 @@ You need the external tools your flow uses:
 - **ModelSim** — only for simulation (`gen-modelsim`, `sim-modelsim`,
   `launch-modelsim`, `compile-modelsim-lib`). `compile-modelsim-lib` also needs
   Vivado to compile the Xilinx simulation libraries.
-- **Git** and **Python** — the tools support Python 3.9+; CI tests on 3.9 and
-  3.11 (3.11 is also used for static analysis).
+- **Git** and **Python** — the tools support Python 3.10–3.14; CI tests on
+  3.10 through 3.14 (3.11 is also used for static analysis).
 
 ### Installing the tools
 
@@ -142,6 +152,8 @@ nihdl compile-vivado
 
 Open the project interactively at any point with `nihdl launch-vivado`.
 
+> **Full walkthrough:** [Vivado Compile Flow](docs/VivadoCompileFlow.md).
+
 ### The LabVIEW FPGA compile flow (custom target)
 
 To expose your HDL to LabVIEW FPGA as a custom target, define your I/O in the
@@ -151,23 +163,26 @@ To expose your HDL to LabVIEW FPGA as a custom target, define your I/O in the
 # Generate target support files (BoardIO/Clock XML, Window VHDL, plugin content)
 nihdl gen-target
 
-# Install the generated plugin into your LabVIEW FPGA install
+# Close ALL LabVIEW instances, then install the generated plugin into your LabVIEW FPGA install
 nihdl install-target
 ```
 
+> **Close LabVIEW around `install-target`.** Close all LabVIEW instances before running it, and
+> (re)start LabVIEW afterward — LabVIEW only scans for target plugins at startup.
+
+> **Full walkthrough:** [LabVIEW FPGA Target and Compile Flow](docs/LabVIEWFpgaTargetFlow.md).
+
 ### Simulating with ModelSim
 
 ```bash
-# Create the ModelSim project and compile all VHDL (vcom -autoorder -2008)
-# When XilinxSimLibFolder is configured, this also compiles the Xilinx
-# simulation libraries (unisim, secureip, ...) on the first run, which can
-# take several minutes. Run it standalone with: nihdl compile-modelsim-lib
-nihdl gen-modelsim
-
-# Launch the GUI, or run headless with --batch
-nihdl launch-modelsim
+# Create the ModelSim project and compile all VHDL, then run the testbench
+nihdl gen-modelsim --overwrite
+nihdl sim-modelsim        # or: nihdl launch-modelsim  (GUI; --batch for headless)
 ```
 
+> **Full walkthrough:** [ModelSim Simulation Flow](docs/ModelSimSimulationFlow.md)
+> — including the Xilinx simulation libraries and how the pass/fail verdict works.
+
 For the complete command list, options, and required settings, see the
 [Command Reference](docs/CommandReference.md).
 

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/README.md

@@ -18,6 +18,12 @@ run Vivado in the end — they differ in what compiles the bitfile:
   target (`gen-target` → `install-target`), then write a VI and let LabVIEW FPGA
   compile the bitfile (it runs Vivado under the hood).
 
+> **Host-side note:** to communicate with the compiled `.lvbitx` from a LabVIEW FPGA
+> host VI, open it with **Open Dynamic Bitfile Reference** (wire in the bitfile path and
+> a matching FPGA Interface Dynamic Refnum) — the standard **Open FPGA VI Reference**
+> node does **not** work with these custom targets. See
+> [Vivado Compile Flow → Opening the bitfile from a LabVIEW FPGA host VI](docs/VivadoCompileFlow.md#opening-the-bitfile-from-a-labview-fpga-host-vi).
+
 In short: in the **Vivado flow** you drive Vivado; in the **LabVIEW FPGA flow**
 LabVIEW FPGA drives Vivado for you. See
 [Theory of Operation](docs/TheoryOfOperation.md) for the full story.
@@ -27,9 +33,13 @@ LabVIEW FPGA drives Vivado for you. See
 | Doc | What's in it |
 | --- | --- |
 | [Theory of Operation](docs/TheoryOfOperation.md) | The architecture, the supported workflows, and how the pieces fit together. Start here. |
+| [Vivado Compile Flow](docs/VivadoCompileFlow.md) | End-to-end walkthrough: extend the HDL, generate a Vivado project, and compile a `.lvbitx` directly in Vivado. |
+| [LabVIEW FPGA Target and Compile Flow](docs/LabVIEWFpgaTargetFlow.md) | End-to-end walkthrough: build and install a custom LabVIEW FPGA target, then compile in LabVIEW FPGA. |
+| [ModelSim Simulation Flow](docs/ModelSimSimulationFlow.md) | End-to-end walkthrough: build the Xilinx sim libraries, create the ModelSim project, and run a testbench. |
 | [Command Reference](docs/CommandReference.md) | Every `nihdl` command, its options, the command flow, and per-command required settings. |
 | [Settings Reference](docs/SettingsReference.md) | The `nihdlsettings.py` model: hooks, context, `--set` overrides, and the full list of setters. |
 | [LVTargetCustomIO Reference](docs/LVTargetCustomIO-Reference.md) | The custom I/O CSV format used to define HDL ↔ LabVIEW FPGA signals. |
+| [Generated VHDL](docs/GeneratedVHDL.md) | What VHDL the tools generate (window wrappers, `PkgNiHdlSettings`) and why — single-sourcing the facts shared by the HDL and the LabVIEW FPGA target. |
 | [Window Netlist and Constraints](docs/WindowNetlistAndConstraints.md) | How the LabVIEW Window netlist is produced/consumed and how XDC constraints are processed for each compile flow (including the `current_instance` scoping rules). |
 
 ## Prerequisites
@@ -45,8 +55,8 @@ You need the external tools your flow uses:
 - **ModelSim** — only for simulation (`gen-modelsim`, `sim-modelsim`,
   `launch-modelsim`, `compile-modelsim-lib`). `compile-modelsim-lib` also needs
   Vivado to compile the Xilinx simulation libraries.
-- **Git** and **Python** — the tools support Python 3.9+; CI tests on 3.9 and
-  3.11 (3.11 is also used for static analysis).
+- **Git** and **Python** — the tools support Python 3.10–3.14; CI tests on
+  3.10 through 3.14 (3.11 is also used for static analysis).
 
 ### Installing the tools
 
@@ -121,6 +131,8 @@ nihdl compile-vivado
 
 Open the project interactively at any point with `nihdl launch-vivado`.
 
+> **Full walkthrough:** [Vivado Compile Flow](docs/VivadoCompileFlow.md).
+
 ### The LabVIEW FPGA compile flow (custom target)
 
 To expose your HDL to LabVIEW FPGA as a custom target, define your I/O in the
@@ -130,23 +142,26 @@ To expose your HDL to LabVIEW FPGA as a custom target, define your I/O in the
 # Generate target support files (BoardIO/Clock XML, Window VHDL, plugin content)
 nihdl gen-target
 
-# Install the generated plugin into your LabVIEW FPGA install
+# Close ALL LabVIEW instances, then install the generated plugin into your LabVIEW FPGA install
 nihdl install-target
 ```
 
+> **Close LabVIEW around `install-target`.** Close all LabVIEW instances before running it, and
+> (re)start LabVIEW afterward — LabVIEW only scans for target plugins at startup.
+
+> **Full walkthrough:** [LabVIEW FPGA Target and Compile Flow](docs/LabVIEWFpgaTargetFlow.md).
+
 ### Simulating with ModelSim
 
 ```bash
-# Create the ModelSim project and compile all VHDL (vcom -autoorder -2008)
-# When XilinxSimLibFolder is configured, this also compiles the Xilinx
-# simulation libraries (unisim, secureip, ...) on the first run, which can
-# take several minutes. Run it standalone with: nihdl compile-modelsim-lib
-nihdl gen-modelsim
-
-# Launch the GUI, or run headless with --batch
-nihdl launch-modelsim
+# Create the ModelSim project and compile all VHDL, then run the testbench
+nihdl gen-modelsim --overwrite
+nihdl sim-modelsim        # or: nihdl launch-modelsim  (GUI; --batch for headless)
 ```
 
+> **Full walkthrough:** [ModelSim Simulation Flow](docs/ModelSimSimulationFlow.md)
+> — including the Xilinx simulation libraries and how the pass/fail verdict works.
+
 For the complete command list, options, and required settings, see the
 [Command Reference](docs/CommandReference.md).
 

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/labview_fpga_hdl_tools/__main__.py

@@ -1,5 +1,6 @@
 #!/usr/bin/env python3
 """LVFPGAHDLTools - Command-line interface for LabVIEW FPGA HDL Tools."""
+
 # Copyright (c) 2025 National Instruments Corporation
 #
 # SPDX-License-Identifier: MIT
@@ -11,7 +12,7 @@ import traceback
 import click
 
 # Import main functions from all the tool modules
-from . import (
+from labview_fpga_hdl_tools import (
     __version__,
     check_syntax,
     command_hooks,
@@ -32,7 +33,7 @@ from . import (
     process_constraints,
     sim_modelsim,
 )
-from .reporting import reporter
+from labview_fpga_hdl_tools.reporting import reporter
 
 
 class SectionGroup(click.Group):

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/labview_fpga_hdl_tools/check_syntax.py

@@ -8,8 +8,9 @@
 import os
 import subprocess
 
-from . import common
-from .reporting import reporter
+from labview_fpga_hdl_tools import common
+from labview_fpga_hdl_tools.command_config import CommandConfiguration
+from labview_fpga_hdl_tools.reporting import reporter
 
 
 def _generate_check_syntax_tcl(config, output_path):
@@ -178,7 +179,7 @@ def check_syntax(config=None):
         int: 0 for success, 1 for error
     """
     if config is None:
-        config = common.CommandConfiguration()
+        config = CommandConfiguration()
 
     try:
         _validate_ini(config)

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/labview_fpga_hdl_tools/common.py

@@ -14,8 +14,7 @@ from typing import Optional
 
 from mako.template import Template
 
-from .command_config import CommandConfiguration, resolve_path  # noqa: F401
-from .reporting import reporter
+from labview_fpga_hdl_tools.reporting import reporter
 
 
 def handle_long_path(path):
@@ -599,7 +598,7 @@ def render_mako_template(template_path, output_path, **kwargs):
         output_path (str): Path where the rendered output will be written
         **kwargs: Template variables to substitute
     """
-    template = Template(filename=template_path, input_encoding="utf-8")
+    template = Template(filename=template_path, input_encoding="utf-8")  # nosec B702
     rendered = str(template.render(**kwargs))
 
     # Mako preserves \r\n from template files on Windows. Normalize to \n

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/labview_fpga_hdl_tools/compile_modelsim_lib.py

@@ -21,9 +21,10 @@ import os
 import subprocess
 import sys
 
-from . import common
-from .create_modelsim_project import _find_modelsim_executable
-from .reporting import reporter
+from labview_fpga_hdl_tools import common
+from labview_fpga_hdl_tools.command_config import CommandConfiguration
+from labview_fpga_hdl_tools.create_modelsim_project import _find_modelsim_executable
+from labview_fpga_hdl_tools.reporting import reporter
 
 # Libraries built when nihdlsettings.py does not specify an explicit scope.
 _DEFAULT_XILINX_SIM_LIBRARIES = ["unisim", "secureip"]
@@ -250,7 +251,7 @@ def compile_modelsim_lib(config=None, force=False):
         int: 0 for success, 1 for error.
     """
     if config is None:
-        config = common.CommandConfiguration()
+        config = CommandConfiguration()
 
     out_folder = config.xilinx_sim_lib_folder
     if not out_folder:

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/labview_fpga_hdl_tools/compile_project.py

@@ -8,8 +8,9 @@
 import os
 import subprocess
 
-from . import common
-from .reporting import reporter
+from labview_fpga_hdl_tools import common
+from labview_fpga_hdl_tools.command_config import CommandConfiguration
+from labview_fpga_hdl_tools.reporting import reporter
 
 
 def _generate_compile_project_tcl(config, output_path):
@@ -187,7 +188,7 @@ def compile_project(config=None):
         int: 0 for success, 1 for error
     """
     if config is None:
-        config = common.CommandConfiguration()
+        config = CommandConfiguration()
 
     try:
         _validate_ini(config)

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/labview_fpga_hdl_tools/create_lvbitx.py

@@ -7,8 +7,8 @@
 import os  # For file and directory operations
 import subprocess  # For executing external programs
 
-from . import common  # For shared utilities across tools
-from .reporting import reporter
+from labview_fpga_hdl_tools.command_config import CommandConfiguration
+from labview_fpga_hdl_tools.reporting import reporter
 
 # createBitfile.exe lives at this path relative to a LabVIEW install root.
 _CREATEBITFILE_RELPATH = os.path.join("vi.lib", "rvi", "CDR", "createBitfile.exe")
@@ -114,7 +114,7 @@ def _create_lv_bitfile(config=None):
 
     # Load configuration
     if config is None:
-        config = common.CommandConfiguration()
+        config = CommandConfiguration()
 
     # Determine path to CodeGenerationResults.lvtxt from TheWindow folder
     if not config.lv_window_netlist_folder:

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/labview_fpga_hdl_tools/create_modelsim_project.py

@@ -11,8 +11,9 @@ import shutil
 import stat
 import subprocess
 
-from . import common, generate_vhdl
-from .reporting import reporter
+from labview_fpga_hdl_tools import common, generate_vhdl
+from labview_fpga_hdl_tools.command_config import CommandConfiguration
+from labview_fpga_hdl_tools.reporting import reporter
 
 
 def _validate_ini(config):
@@ -426,7 +427,7 @@ def create_modelsim_project(overwrite=False, config=None):
     - .do files for GUI and batch simulation
     """
     if config is None:
-        config = common.CommandConfiguration()
+        config = CommandConfiguration()
 
     try:
         _validate_ini(config)
@@ -499,7 +500,7 @@ def create_modelsim_project(overwrite=False, config=None):
         # This is idempotent: once compiled it is a cheap no-op (and does not
         # even require Vivado). Imported locally to avoid a circular import,
         # since compile_modelsim_lib imports helpers from this module.
-        from . import compile_modelsim_lib
+        from labview_fpga_hdl_tools import compile_modelsim_lib
 
         if compile_modelsim_lib.compile_modelsim_lib(config=config) != 0:
             return 1

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/labview_fpga_hdl_tools/create_vivado_project.py

@@ -23,8 +23,9 @@ import subprocess
 from collections import defaultdict
 from enum import Enum
 
-from . import common, generate_vhdl, process_constraints
-from .reporting import reporter
+from labview_fpga_hdl_tools import common, generate_vhdl, process_constraints
+from labview_fpga_hdl_tools.command_config import CommandConfiguration
+from labview_fpga_hdl_tools.reporting import reporter
 
 # Windows MAX_PATH. When the generated TCL adds a source file, Vivado resolves the
 # file's add_files path (which is relative to the TCL folder) against the Vivado
@@ -810,7 +811,7 @@ def create_project(overwrite=False, update=False, config=None):
     """
     # Load configuration with optional custom config path
     if config is None:
-        config = common.CommandConfiguration()
+        config = CommandConfiguration()
 
     result = _run_create_project_steps(overwrite, update, config)
 

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/labview_fpga_hdl_tools/gen_labview_target_plugin.py

@@ -22,14 +22,17 @@ import re
 import shutil  # For file copying operations
 import stat
 import xml.etree.ElementTree as ET  # For XML generation and manipulation # noqa: N817
-from xml.dom.minidom import parseString  # For pretty-formatted XML output
 
+from defusedxml.minidom import parseString  # For safe pretty-formatted XML output
 from mako.template import Template  # For template-based file generation  # type: ignore
 
-from . import common  # For shared utilities across tools
-from . import generate_vhdl  # For generated VHDL file generation
-from . import process_constraints  # For shared constraint macro replacement
-from .reporting import reporter
+from labview_fpga_hdl_tools import common  # For shared utilities across tools
+from labview_fpga_hdl_tools import generate_vhdl  # For generated VHDL file generation
+from labview_fpga_hdl_tools import (
+    process_constraints,  # For shared constraint macro replacement
+)
+from labview_fpga_hdl_tools.command_config import CommandConfiguration
+from labview_fpga_hdl_tools.reporting import reporter
 
 # Constants
 BOARDIO_WRAPPER_NAME = "BoardIO"  # Top-level wrapper name in the BoardIO XML hierarchy
@@ -507,7 +510,7 @@ def _generate_target_xml(
             # Render template
             try:
                 with open(template_path, "r", encoding="utf-8") as f:
-                    template = Template(f.read())
+                    template = Template(f.read())  # nosec B702
 
                 render_kwargs = {
                     "include_board_io": include_board_io,
@@ -750,7 +753,7 @@ def gen_lv_target_support(config=None):
     """Generate target support files."""
     # Load configuration
     if config is None:
-        config = common.CommandConfiguration()
+        config = CommandConfiguration()
     has_validation_errors = False
     validation_errors = []
     register_space_warnings = []

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/labview_fpga_hdl_tools/generate_vhdl.py

@@ -23,8 +23,9 @@ import os  # For file and directory operations
 
 from mako.template import Template  # For template-based file generation  # type: ignore
 
-from . import common  # For shared utilities across tools
-from .reporting import reporter
+from labview_fpga_hdl_tools import common  # For shared utilities across tools
+from labview_fpga_hdl_tools.command_config import CommandConfiguration
+from labview_fpga_hdl_tools.reporting import reporter
 
 
 def _ensure_text(value):
@@ -241,7 +242,7 @@ def _render_generated_vhdl(template_paths, output_folder, context):
             reporter.detail(f"Processing template: {template_path} -> {output_path}")
 
             with open(template_path, "r", encoding="utf-8") as f:
-                template = Template(f.read())
+                template = Template(f.read())  # nosec B702
 
             output_text = template.render(**context)
 
@@ -303,7 +304,7 @@ def gen_generated_vhdl(config=None):
     """
     # Load configuration
     if config is None:
-        config = common.CommandConfiguration()
+        config = CommandConfiguration()
 
     if not config.generated_vhdl_templates:
         # Nothing to generate; not an error.

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/labview_fpga_hdl_tools/get_window_netlist.py

@@ -10,8 +10,9 @@ import os
 import shutil
 import subprocess
 
-from . import common
-from .reporting import reporter
+from labview_fpga_hdl_tools import common
+from labview_fpga_hdl_tools.command_config import CommandConfiguration
+from labview_fpga_hdl_tools.reporting import reporter
 
 # Generated flat wrapper file produced by the GetWindowNetlist TCL script.
 _WINDOW_FLAT_WRAPPER_FILE = "TheLvWindowFlatWrapper.v"
@@ -305,7 +306,7 @@ def get_window(config=None):
     """Main entry point for the script."""
     # Load configuration
     if config is None:
-        config = common.CommandConfiguration()
+        config = CommandConfiguration()
 
     # Validate that all required settings are present
     try:

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/labview_fpga_hdl_tools/install_dependencies.py

@@ -52,7 +52,7 @@ except ModuleNotFoundError:
 from packaging.specifiers import SpecifierSet
 from packaging.version import InvalidVersion, Version
 
-from .reporting import reporter
+from labview_fpga_hdl_tools.reporting import reporter
 
 # Suffix for the per-dependency version marker files written next to each
 # cloned repo. Mirrors the discoverability of Python's "<pkg>-<ver>.dist-info"

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/labview_fpga_hdl_tools/install_labview_target_plugin.py

@@ -8,8 +8,9 @@ import os  # For file and directory operations
 import shutil  # For file copying and directory removal
 import sys  # For command-line arguments and error handling
 
-from . import common  # For shared utilities across tools
-from .reporting import reporter
+from labview_fpga_hdl_tools import common  # For shared utilities across tools
+from labview_fpga_hdl_tools.command_config import CommandConfiguration
+from labview_fpga_hdl_tools.reporting import reporter
 
 
 def _is_admin():
@@ -26,8 +27,30 @@ def _is_admin():
 
 
 def _run_as_admin():
-    """Re-launch the command with administrator privileges."""
+    """Re-launch the command with administrator privileges.
+
+    Security notes:
+    - Elevation spawns a *separate* short-lived process via UAC; the elevated
+      privileges live and die with that child process. The elevated instance
+      performs the install and then exits, so admin rights are never retained
+      by any process after installation completes.
+    - Re-launch through the current Python interpreter (``sys.executable``, an
+      absolute, trusted path) running the tool as a module (``-m
+      labview_fpga_hdl_tools``). We deliberately do NOT re-invoke ``sys.argv[0]``
+      (the console-script launcher, e.g. nihdl.exe): those launcher stubs are
+      resolved for the *current* user's environment (venv / pyenv shims) and do
+      not reliably re-bootstrap their interpreter under the elevated (admin)
+      account, so the elevated child would exit without doing any work. Passing
+      a bare program name (e.g. "nihdl") is likewise avoided because Windows
+      would resolve it against the working directory / PATH in the elevated
+      context, allowing an attacker-planted binary to run as admin
+      (CWE-426/CWE-427, untrusted search path).
+    - The elevated child is launched with its working directory pinned to the
+      current working directory so it discovers the same ``nihdlsettings.py``
+      the user invoked against (config is resolved relative to the cwd).
+    """
     import ctypes
+    import subprocess
     import sys
 
     # Skip on non-Windows platforms
@@ -35,19 +58,21 @@ def _run_as_admin():
         reporter.detail("Admin elevation only supported on Windows")
         return
 
-    # When running via pip-installed entry point
-    if sys.argv[0].endswith("nihdl") or sys.argv[0].endswith("nihdl.exe"):
-        command = "nihdl"
-        arguments = " ".join(sys.argv[1:])
-    else:
-        command = sys.executable
-        arguments = f'"{sys.argv[0]}" {" ".join(sys.argv[1:])}'
+    # Re-launch via the real interpreter running the package as a module. This
+    # is both trusted (absolute interpreter path, module named explicitly) and
+    # robust across launchers (venv exe, pyenv shim, editable install).
+    command = os.path.abspath(sys.executable)
+    arguments = subprocess.list2cmdline(["-m", "labview_fpga_hdl_tools", *sys.argv[1:]])
+
+    # Pin the elevated child's working directory to the current directory so it
+    # finds the same nihdlsettings.py the user invoked against.
+    working_dir = os.getcwd()
 
     reporter.detail("Requesting administrator privileges...")
 
     # Execute with elevation
     result = ctypes.windll.shell32.ShellExecuteW(  # type: ignore
-        None, "runas", command, arguments, None, 1
+        None, "runas", command, arguments, working_dir, 1
     )
 
     # Check if the elevation was successful
@@ -55,7 +80,8 @@ def _run_as_admin():
         reporter.error(f"Error elevating privileges. Error code: {result}")
         sys.exit(1)
 
-    # The original process should exit after launching the elevated one
+    # The original (non-elevated) process exits after launching the elevated
+    # one, so no admin privileges are held by a lingering process.
     reporter.detail("Elevated process launched. This process will now exit.")
     sys.exit(0)
 
@@ -121,7 +147,7 @@ def install_lv_target_support(config=None):
     """
     # Load configuration
     if config is None:
-        config = common.CommandConfiguration()
+        config = CommandConfiguration()
 
     # Validate that all required settings are present
     try:
@@ -141,6 +167,14 @@ def install_lv_target_support(config=None):
 
     # If we need admin and don't have it, relaunch with elevated privileges
     if needs_admin and not _is_admin():
+        # Always-visible notice: the actual install runs in a separate elevated
+        # process (a UAC prompt will appear). Without this, the command appears
+        # to do nothing because the elevated child owns the success output.
+        reporter.success(
+            f"Installing '{config.lv_target_name}' to '{install_folder}' requires "
+            "administrator rights. Approve the Windows UAC prompt; the install "
+            "completes in a separate elevated window."
+        )
         _run_as_admin()
         return  # Exit current instance as the elevated instance will continue
 
@@ -181,6 +215,11 @@ def install_lv_target_support(config=None):
         reporter.success(
             f"Successfully installed LabVIEW Target '{config.lv_target_name}' to {install_folder}"
         )
+        reporter.success(
+            "Reminder: close ALL open LabVIEW instances before installing, and (re)start "
+            "LabVIEW afterward. LabVIEW FPGA only scans for target plugins at startup, so a "
+            "running instance will not see this newly installed or updated target."
+        )
 
     except PermissionError:
         reporter.error("Error: Permission denied. Administrator privileges are required.")

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/labview_fpga_hdl_tools/launch_modelsim.py

@@ -9,9 +9,10 @@ import os
 import platform
 import subprocess
 
-from . import common
-from .create_modelsim_project import _get_vsim_executable
-from .reporting import reporter
+from labview_fpga_hdl_tools import common
+from labview_fpga_hdl_tools.command_config import CommandConfiguration
+from labview_fpga_hdl_tools.create_modelsim_project import _get_vsim_executable
+from labview_fpga_hdl_tools.reporting import reporter
 
 
 def _validate_ini(config):
@@ -38,7 +39,7 @@ def _validate_ini(config):
 def launch_modelsim(batch=False, config=None):
     """Launch ModelSim using settings from nihdlsettings.py."""
     if config is None:
-        config = common.CommandConfiguration()
+        config = CommandConfiguration()
 
     try:
         _validate_ini(config)

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/labview_fpga_hdl_tools/launch_vivado.py

@@ -9,8 +9,9 @@ import os
 import platform
 import subprocess
 
-from . import common
-from .reporting import reporter
+from labview_fpga_hdl_tools import common
+from labview_fpga_hdl_tools.command_config import CommandConfiguration
+from labview_fpga_hdl_tools.reporting import reporter
 
 
 def _validate_ini(config):
@@ -50,7 +51,7 @@ def launch_vivado(config=None):
     """Launch Vivado using settings from nihdlsettings.py."""
     # Load configuration from nihdlsettings.py
     if config is None:
-        config = common.CommandConfiguration()
+        config = CommandConfiguration()
 
     # Validate that all required settings are present and paths exist
     try:

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/labview_fpga_hdl_tools/migrate_clip.py

@@ -21,8 +21,11 @@ import sys
 import traceback
 import xml.etree.ElementTree as ET  # noqa: N817
 
-from . import common
-from .reporting import reporter
+import defusedxml.ElementTree as DefusedET
+
+from labview_fpga_hdl_tools import common
+from labview_fpga_hdl_tools.command_config import CommandConfiguration
+from labview_fpga_hdl_tools.reporting import reporter
 
 INVALID_LV_DATA_TYPE = "INVALID_LV_DATA_TYPE"
 
@@ -181,7 +184,7 @@ def _generate_board_io_csv_from_clip_xml(input_xml_path, clip_output_csv):
 
         # Parse XML
         try:
-            tree = ET.parse(input_xml_path)
+            tree = DefusedET.parse(input_xml_path)
             root = tree.getroot()
         except ET.ParseError as e:
             sys.exit(f"Error parsing XML file: {e}")
@@ -369,7 +372,7 @@ def _generate_clip_to_window_signals(input_xml_path, output_vhdl_path):
 
         # Parse XML
         try:
-            tree = ET.parse(input_xml_path)
+            tree = DefusedET.parse(input_xml_path)
             root = tree.getroot()
         except ET.ParseError as e:
             reporter.error(f"Error parsing XML file: {e}")
@@ -637,7 +640,7 @@ def migrate_clip(config=None):
     """Main program entry point."""
     # Load configuration
     if config is None:
-        config = common.CommandConfiguration()
+        config = CommandConfiguration()
     validation_errors = []
 
     # Validate that all required settings are present

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/labview_fpga_hdl_tools/process_constraints.py

@@ -13,8 +13,8 @@ into user-provided template files, replacing macro tokens.
 import os
 import re
 
-from . import common
-from .reporting import reporter
+from labview_fpga_hdl_tools.command_config import CommandConfiguration
+from labview_fpga_hdl_tools.reporting import reporter
 
 # ---------------------------------------------------------------------------
 # TG/TNM constraint conversion helpers
@@ -435,6 +435,6 @@ def process_constraints(config=None):
         int: 0 on success.
     """
     if config is None:
-        config = common.CommandConfiguration()
+        config = CommandConfiguration()
     process_constraints_template(config)
     return 0

{labview_fpga_hdl_tools-2.0.0.dev3 → labview_fpga_hdl_tools-2.0.0.dev5}/labview_fpga_hdl_tools/sim_modelsim.py

@@ -10,9 +10,10 @@ import subprocess
 import sys
 import time
 
-from . import common
-from .create_modelsim_project import _get_vsim_executable
-from .reporting import reporter
+from labview_fpga_hdl_tools import common
+from labview_fpga_hdl_tools.command_config import CommandConfiguration
+from labview_fpga_hdl_tools.create_modelsim_project import _get_vsim_executable
+from labview_fpga_hdl_tools.reporting import reporter
 
 
 def _validate_ini(config):
@@ -50,7 +51,7 @@ def sim_modelsim(do_file=None, config=None):
         int: 0 on success, non-zero on failure.
     """
     if config is None:
-        config = common.CommandConfiguration()
+        config = CommandConfiguration()
 
     try:
         _validate_ini(config)

labview_fpga_hdl_tools-2.0.0.dev5/pyproject.toml

@@ -0,0 +1,75 @@
+[build-system]
+requires = ["poetry-core>=1.8"]
+build-backend = "poetry.core.masonry.api"
+
+[tool.poetry]
+name = "labview-fpga-hdl-tools"
+version = "2.0.0.dev5"
+description = "LabVIEW FPGA HDL Tools"
+authors = [
+  "Salvador Santolucito <salvador.santolucito@gmail.com>"
+]
+readme = "README.md"
+license = "MIT"
+include = [
+  { path = "labview_fpga_hdl_tools/host_interfaces/**", format = "sdist" }
+]
+
+[tool.poetry.dependencies]
+# Supports the Python versions in their maintenance window (3.10-3.14).
+python = ">=3.10,<3.15"
+mako = ">=1.3.10"
+click = ">=8.1.8,<8.2"
+packaging = ">=21.0"
+# Hardens XML parsing against XXE / entity-expansion attacks (used instead of xml.etree/minidom).
+defusedxml = ">=0.7.1"
+tomli = {version = ">=1.1.0", python = "<3.11"}
+
+[tool.poetry.group.test.dependencies]
+# >=9.0.3 fixes insecure /tmp/pytest-of-{user} tmpdir handling (CVE); requires Python >=3.10.
+pytest = ">=9.0.3"
+
+[tool.poetry.group.lint.dependencies]
+bandit = { version = ">=1.7", extras = ["toml"] }
+# 0.5.x bundles flake8-tidy-imports (bans relative imports) and a pkg_resources-free
+# flake8-import-order (>=0.19.2), which is required for setuptools >= 81.
+ni-python-styleguide = ">=0.5.1"
+# Pinned directly (transitive via ni-python-styleguide) so security updates can be applied.
+# Capped < 26 because ni-python-styleguide 0.5.x requires black < 26.0; 25.12.0 needs Python >= 3.10.
+black = ">=25.12.0,<26"
+# flake8-black < 0.4.0 crashes (BLK900) on black >= 25.9.0 due to a decode_bytes API change.
+flake8-black = ">=0.4.0"
+# Transitive via bandit/pbr and ni-python-styleguide. Bumped to the latest to clear the
+# setuptools sdist Unicode-normalization advisory (fixed in 83.0.0); 83 dropped pkg_resources,
+# which is why ni-python-styleguide 0.5.x (pkg_resources-free import-order) is required.
+setuptools = ">=83.0.0"
+mypy = ">=1.0"
+pyright = { version = ">=1.1.400", extras = ["nodejs"] }
+
+[tool.poetry.scripts]
+nihdl = "labview_fpga_hdl_tools.__main__:main"
+
+[tool.mypy]
+packages = ["labview_fpga_hdl_tools"]
+python_version = "3.10"
+warn_return_any = true
+warn_unused_configs = true
+disallow_untyped_defs = false
+disallow_incomplete_defs = false
+
+[[tool.mypy.overrides]]
+module = "mako.*"
+ignore_missing_imports = true
+
+[[tool.mypy.overrides]]
+module = "defusedxml.*"
+ignore_missing_imports = true
+
+[tool.bandit]
+exclude_dirs = ["tests"]
+# Reviewed low-severity informational tests, safe by construction:
+#   B404/B603/B607 - subprocess is invoked with argument lists (never shell=True), so there is
+#     no shell-injection surface; executable paths are resolved from trusted configuration.
+#   B405 - xml.etree is used only for XML generation / ParseError handling; all XML parsing
+#     uses defusedxml (see the B314/B318 remediations).
+skips = ["B404", "B603", "B607", "B405"]

labview_fpga_hdl_tools-2.0.0.dev3/pyproject.toml

@@ -1,50 +0,0 @@
-[build-system]
-requires = ["poetry-core>=1.8"]
-build-backend = "poetry.core.masonry.api"
-
-[tool.poetry]
-name = "labview-fpga-hdl-tools"
-version = "2.0.0.dev3"
-description = "LabVIEW FPGA HDL Tools"
-authors = [
-  "Salvador Santolucito <salvador.santolucito@gmail.com>"
-]
-readme = "README.md"
-license = "MIT"
-include = [
-  { path = "labview_fpga_hdl_tools/host_interfaces/**", format = "sdist" }
-]
-
-[tool.poetry.dependencies]
-python = ">=3.9,<4.0"
-mako = ">=1.3.10"
-click = ">=8.1.8,<8.2"
-packaging = ">=21.0"
-tomli = {version = ">=1.1.0", python = "<3.11"}
-
-[tool.poetry.group.test.dependencies]
-pytest = ">=7.2"
-
-[tool.poetry.group.lint.dependencies]
-bandit = { version = ">=1.7", extras = ["toml"] }
-ni-python-styleguide = ">=0.4.1"
-mypy = ">=1.0"
-pyright = { version = ">=1.1.400", extras = ["nodejs"] }
-
-[tool.poetry.scripts]
-nihdl = "labview_fpga_hdl_tools.__main__:main"
-
-[tool.mypy]
-packages = ["labview_fpga_hdl_tools"]
-python_version = "3.9"
-warn_return_any = true
-warn_unused_configs = true
-disallow_untyped_defs = false
-disallow_incomplete_defs = false
-
-[[tool.mypy.overrides]]
-module = "mako.*"
-ignore_missing_imports = true
-
-[tool.bandit]
-exclude_dirs = ["tests"]