labview-fpga-hdl-tools 2.0.0.dev0__tar.gz → 2.0.0.dev1__tar.gz

{labview_fpga_hdl_tools-2.0.0.dev0 → labview_fpga_hdl_tools-2.0.0.dev1}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.3
 Name: labview-fpga-hdl-tools
-Version: 2.0.0.dev0
+Version: 2.0.0.dev1
 Summary: LabVIEW FPGA HDL Tools
 License: MIT
 Author: Salvador Santolucito

{labview_fpga_hdl_tools-2.0.0.dev0 → labview_fpga_hdl_tools-2.0.0.dev1}/labview_fpga_hdl_tools/create_vivado_project.py

@@ -25,6 +25,27 @@ from enum import Enum
 from . import common, generate_vhdl, process_constraints
 from .reporting import reporter
 
+# Windows MAX_PATH. When the generated TCL adds a source file, Vivado resolves the
+# file's add_files path (which is relative to the TCL folder) against the Vivado
+# project folder -- its working directory -- WITHOUT collapsing the leading ".."
+# segments. On Windows that raw, non-normalized string is bounded by MAX_PATH.
+# Empirically a resolved length of 260 fails with "[Vivado 12-172] File or
+# Directory ... does not exist" even though the file exists; 259 is the longest
+# that works.
+VIVADO_MAX_PATH_LEN = 260
+
+# Copy a source file into objects/gatheredfiles once its Vivado-resolved path would
+# reach this length. This sits just below VIVADO_MAX_PATH_LEN so a normal install
+# never trips the hard failure, while leaving as much room as possible so that
+# dependency files shipped at their real paths are added in place rather than
+# copied. The dependency path shortening in the flexrio build (build.py
+# DEPS_MAX_REL_PATH_LEN) is sized to keep normal installs under this limit.
+VIVADO_SAFE_MAX_PATH_LEN = 255
+
+# Non-Windows platforms are not affected by MAX_PATH; use a generous limit that
+# effectively only guards against pathological path lengths.
+POSIX_MAX_PATH_LEN = 4096
+
 
 def _has_spaces(file_path):
     """Checks if the given file path contains spaces.
@@ -211,17 +232,25 @@ def _find_and_log_duplicates(file_list):
     return unique_file_list
 
 
-def _copy_long_path_files(file_list):
-    """Copies files to the "objects/gatheredfiles" folder.
+def _copy_long_path_files(file_list, vivado_project_dir, tcl_base_dir):
+    """Copies files that would exceed Vivado's path limit into "objects/gatheredfiles".
+
+    Vivado does not use a source file's absolute path to decide whether it can open
+    it. The generated TCL adds each file with a path that is relative to the TCL
+    folder, and Vivado resolves that relative path against the Vivado project folder
+    (its working directory) WITHOUT collapsing the leading ".." segments. On Windows
+    that raw, non-normalized string is bounded by the 260-char MAX_PATH limit, so it
+    -- not the shorter normalized absolute path -- is what determines whether Vivado
+    reports "[Vivado 12-172] File or Directory ... does not exist".
 
-    The function handles:
-    - Creating the target directory if needed
-    - Handling Windows long paths for deep directory structures
-    - Setting proper file permissions
-    - Error reporting for failed copy operations
+    This function reproduces that exact resolution to decide which files must be
+    copied to a short local path before being added to the project.
 
     Args:
         file_list (list): Original list of file paths
+        vivado_project_dir (str): Absolute path of the Vivado project folder, which
+            Vivado uses as its working directory when the generated TCL runs
+        tcl_base_dir (str): Folder that the add_files paths are made relative to
 
     Returns:
         list: Updated file list with long path files moved to local paths
@@ -237,29 +266,28 @@ def _copy_long_path_files(file_list):
         # Store original file path before modification
         original_file = file
         absolute_file_path = os.path.abspath(original_file)
-        try:
-            relative_file_path = os.path.relpath(absolute_file_path, os.getcwd())
-        except ValueError:
-            relative_file_path = original_file
 
-        # Handle long paths on Windows
+        # Reproduce the path length Vivado will actually see. On Windows this is the
+        # non-normalized "<project folder>\<relative add_files path>" string that is
+        # subject to MAX_PATH; elsewhere the generous absolute-path limit applies.
+        if os.name == "nt":
+            tcl_relative_path = os.path.relpath(absolute_file_path, tcl_base_dir)
+            vivado_path_len = len(vivado_project_dir) + len(os.sep) + len(tcl_relative_path)
+            path_len_limit = VIVADO_SAFE_MAX_PATH_LEN
+        else:
+            vivado_path_len = len(absolute_file_path)
+            path_len_limit = POSIX_MAX_PATH_LEN
+
+        # Handle long source paths on Windows so the copy itself can read them.
         if os.name == "nt":
             file = f"\\\\?\\{absolute_file_path}"
             target_folder_long = f"\\\\?\\{os.path.abspath(target_folder)}"
         else:
             target_folder_long = target_folder
 
-        # Vivado has a problem with adding long file paths to the project,
-        # so we check if the file path is too long and if so we copy it
-        # to a local folder and add it from there instead. We check both
-        # the absolute path and the relative path because Vivado might be
-        # using either one when processing the TCL script, and we want to
-        # ensure that we catch all cases where the path length could be
-        # an issue.
-        max_path = 200 if os.name == "nt" else 4096
-
-        # Check if the absolute or relative path is longer than max_path characters.
-        if len(absolute_file_path) > max_path or len(relative_file_path) > max_path:
+        # Copy the file to a short local path when Vivado's resolved path would be
+        # too long. Files at short paths are added from their original location.
+        if vivado_path_len > path_len_limit:
             target_path = os.path.join(target_folder_long, os.path.basename(file))
             if os.path.exists(target_path):
                 os.chmod(target_path, 0o777)  # Make the file writable
@@ -267,7 +295,10 @@ def _copy_long_path_files(file_list):
                 shutil.copy2(file, target_path)
                 new_file_list.append(target_path)
                 reporter.warn(f"WARNING: Long path file {original_file}")
-                reporter.detail(f"         was copied into the objects/gatheredfiles folder.")
+                reporter.detail(
+                    f"         (Vivado path length {vivado_path_len} exceeds the safe "
+                    f"limit of {path_len_limit}) was copied into the objects/gatheredfiles folder."
+                )
                 reporter.detail(
                     f"         You must run 'nihdl create-project --update' to pull in any changes to the source file."
                 )
@@ -592,9 +623,12 @@ def _create_project(mode: ProjectMode, config):
 
     # Copy long path files to the gatheredfiles folder
     # Returns the file list with the files from old long path locations having
-    # new locations in gatheredfiles
-    file_list = _copy_long_path_files(file_list)
-    vhdl2008_file_list = _copy_long_path_files(vhdl2008_file_list)
+    # new locations in gatheredfiles. The Vivado project folder and TCL folder are
+    # needed to reproduce the exact path length Vivado resolves at add_files time.
+    tcl_base_dir = os.path.join(current_dir, "TCL")
+    vivado_project_dir = os.path.join(current_dir, config.vivado_project_folder)
+    file_list = _copy_long_path_files(file_list, vivado_project_dir, tcl_base_dir)
+    vhdl2008_file_list = _copy_long_path_files(vhdl2008_file_list, vivado_project_dir, tcl_base_dir)
 
     # Override default LV generated files with extracted window files
     if config.lv_window_netlist_folder:

{labview_fpga_hdl_tools-2.0.0.dev0 → labview_fpga_hdl_tools-2.0.0.dev1}/labview_fpga_hdl_tools/gen_labview_target_plugin.py

@@ -38,6 +38,10 @@ DOCUMENT_ROOT_PREFIX = (
 
 # Data type prototypes mapping - used to map LabVIEW data types to their FPGA representations
 # The {direction} placeholder is replaced with Input/OutputWithoutReadback based on signal direction
+#
+# LV FPGA supported prototypes are documented here -
+#         src/lvfpga/source/LabVIEW/resource/RVI/FPGATargetXML/niLvFpgaTargetNecessities.xml
+#
 DATA_TYPE_PROTOTYPES = {
     "FXP": DOCUMENT_ROOT_PREFIX
     + "FXPDigital{direction}{output_readback}{zero_sync_regs}",  # Fixed-point numeric type
@@ -61,6 +65,49 @@ DATA_TYPE_PROTOTYPES = {
     + "i64Digital{direction}{output_readback}{zero_sync_regs}",  # Signed 64-bit integer
 }
 
+# The BoardIO prototype name is assembled as:
+#   <type>Digital<direction><output_readback><zero_sync_regs>
+# Not every permutation of the CSV Direction / OutputReadback / ZeroSyncRegs
+# columns corresponds to a prototype that LabVIEW FPGA publishes. These sets
+# capture the supported suffixes (everything after "<type>Digital") so that
+# unsupported combinations are reported as validation errors instead of being
+# written out as unusable prototypes.
+#
+# Every supported data type allows these combinations:
+_BASE_PROTOTYPE_SUFFIXES = frozenset(
+    {
+        "Input",
+        "InputZeroDefaultSyncRegisters",
+        "OutputWithReadback",
+        "OutputWithReadbackZeroDefaultSyncRegisters",
+        "OutputWithoutReadback",
+    }
+)
+
+# Only Boolean and FXP additionally support a zero-default-sync-register form of
+# the without-readback output. The integer port types (U8-U64, I8-I64) do not.
+_TYPES_SUPPORTING_WITHOUT_READBACK_ZERO_SYNC = frozenset({"Boolean", "FXP"})
+
+
+def _get_supported_prototype_suffixes(data_type_name):
+    """Return the set of supported prototype suffixes for a CSV DataType.
+
+    The suffix is the portion of the prototype name after ``<type>Digital``
+    (i.e. ``<direction><output_readback><zero_sync_regs>``). This encodes which
+    Direction / OutputReadback / ZeroSyncRegs permutations map to a real
+    LabVIEW FPGA prototype for the given data type.
+
+    Args:
+        data_type_name (str): DataType base name (e.g. ``Boolean``, ``U8``, ``FXP``).
+
+    Returns:
+        set[str]: Supported prototype-name suffixes for the data type.
+    """
+    suffixes = set(_BASE_PROTOTYPE_SUFFIXES)
+    if data_type_name in _TYPES_SUPPORTING_WITHOUT_READBACK_ZERO_SYNC:
+        suffixes.add("OutputWithoutReadbackZeroDefaultSyncRegisters")
+    return suffixes
+
 
 def _parse_register_offset(offset_text):
     """Parse a register offset string as an integer.
@@ -286,10 +333,14 @@ def _generate_xml_from_csv(csv_path, boardio_output_path, clock_output_path):
                         "true": "ZeroDefaultSyncRegisters",
                         "false": "",
                     }.get(zero_sync_regs.lower())
-                    if io_zero_sync_regs is None and zero_sync_regs:
-                        error = f"Row {row_count}: Invalid ZeroSyncRegs '{zero_sync_regs}' for signal '{lv_name}'. Must be 'TRUE' or 'FALSE'."
-                        validation_errors.append(error)
-                        io_zero_sync_regs = "INVALID_SYNC_REGS"
+                    if io_zero_sync_regs is None:
+                        if zero_sync_regs:
+                            error = f"Row {row_count}: Invalid ZeroSyncRegs '{zero_sync_regs}' for signal '{lv_name}'. Must be 'TRUE' or 'FALSE'."
+                            validation_errors.append(error)
+                            io_zero_sync_regs = "INVALID_SYNC_REGS"
+                        else:
+                            # An empty cell is treated as FALSE (no suffix appended).
+                            io_zero_sync_regs = ""
 
                     # Validate output readback setting for outputs
                     if io_direction == "Output":
@@ -308,25 +359,54 @@ def _generate_xml_from_csv(csv_path, boardio_output_path, clock_output_path):
                     data_type_name = data_type.split("(")[0] if "(" in data_type else data_type
 
                     if data_type_name in DATA_TYPE_PROTOTYPES:
-                        prototype = DATA_TYPE_PROTOTYPES[data_type_name].format(
-                            direction=io_direction,
-                            zero_sync_regs=io_zero_sync_regs,
-                            output_readback=io_output_readback,
+                        # The prototype name is assembled from the direction,
+                        # readback, and sync-register tokens. Not every
+                        # permutation corresponds to a prototype that LabVIEW
+                        # FPGA publishes, so reject unsupported combinations
+                        # instead of emitting an unusable prototype.
+                        prototype_suffix = f"{io_direction}{io_output_readback}{io_zero_sync_regs}"
+                        supported_suffixes = _get_supported_prototype_suffixes(data_type_name)
+                        tokens_valid = (
+                            io_direction in ("Input", "Output")
+                            and io_output_readback in ("", "WithReadback", "WithoutReadback")
+                            and io_zero_sync_regs in ("", "ZeroDefaultSyncRegisters")
                         )
-                        io_resource.set("prototype", prototype)
-
-                        # Handle FXP attributes
-                        if data_type_name == "FXP" and "(" in data_type:
-                            try:
-                                parts = data_type.split("(")[1].split(")")[0].split(",")
-                                io_resource.set("wordLength", parts[0])
-                                io_resource.set("integerWordLength", parts[1])
-                                io_resource.set(
-                                    "unsigned",
-                                    "true" if "Unsigned" in data_type else "false",
-                                )
-                            except Exception as e:
-                                reporter.error(f"Error parsing FXP parameters for {lv_name}: {e}")
+
+                        if tokens_valid and prototype_suffix not in supported_suffixes:
+                            error = (
+                                f"Row {row_count}: DataType='{data_type}' with "
+                                f"Direction='{direction}', OutputReadback='{output_readback}', "
+                                f"and ZeroSyncRegs='{zero_sync_regs}' for signal '{lv_name}' "
+                                f"does not map to a supported LabVIEW FPGA prototype. The integer "
+                                f"port types (U8-U64, I8-I64) have no WithoutReadback output with "
+                                f"ZeroSyncRegs=TRUE; set OutputReadback=TRUE or ZeroSyncRegs=FALSE. "
+                                f"See the DataType compatibility table in "
+                                f"docs/LVTargetCustomIO-Reference.md for all valid combinations."
+                            )
+                            validation_errors.append(error)
+                            io_resource.set("prototype", "UNSUPPORTED_PROTOTYPE_COMBINATION")
+                        else:
+                            prototype = DATA_TYPE_PROTOTYPES[data_type_name].format(
+                                direction=io_direction,
+                                zero_sync_regs=io_zero_sync_regs,
+                                output_readback=io_output_readback,
+                            )
+                            io_resource.set("prototype", prototype)
+
+                            # Handle FXP attributes
+                            if data_type_name == "FXP" and "(" in data_type:
+                                try:
+                                    parts = data_type.split("(")[1].split(")")[0].split(",")
+                                    io_resource.set("wordLength", parts[0])
+                                    io_resource.set("integerWordLength", parts[1])
+                                    io_resource.set(
+                                        "unsigned",
+                                        "true" if "Unsigned" in data_type else "false",
+                                    )
+                                except Exception as e:
+                                    reporter.error(
+                                        f"Error parsing FXP parameters for {lv_name}: {e}"
+                                    )
                     else:
                         # Add validation error for invalid signal type
                         error = f"Row {row_count}: Invalid signal type '{data_type}' for signal '{lv_name}'. Valid types: {', '.join(DATA_TYPE_PROTOTYPES.keys())}"
@@ -755,6 +835,10 @@ def gen_lv_target_support(config=None):
         fpga_files_folder,
         process_constraints.build_custom_constraints_content(config.custom_constraints),
     )
+    process_constraints.wrap_from_to_constraints_macro_in_folder(
+        fpga_files_folder,
+        config.entity_path_to_window_wrapper,
+    )
 
     _copy_menu_files(config.lv_target_plugin_output_folder, config.lv_target_menus_folder)
 

{labview_fpga_hdl_tools-2.0.0.dev0 → labview_fpga_hdl_tools-2.0.0.dev1}/labview_fpga_hdl_tools/process_constraints.py

@@ -176,6 +176,60 @@ def replace_custom_constraints_in_xdc_folder(folder, custom_constraints_content)
             reporter.detail(f"Replaced macro_GitHubCustomConstraints in {filename}")
 
 
+_FROM_TO_CONSTRAINTS_MACRO_RE = re.compile(
+    r"^([ \t]*)(#LabVIEWFPGA_Macro[ \t]+macro_fromToConstraints)[ \t]*$",
+    re.IGNORECASE | re.MULTILINE,
+)
+
+
+def wrap_from_to_constraints_macro_in_folder(folder, entity_path_to_window_wrapper):
+    """Wrap the from-to-constraints macro with current_instance scoping in constraint files.
+
+    In the LabVIEW FPGA target plugin flow, LabVIEW FPGA replaces
+    ``#LabVIEWFPGA_Macro macro_fromToConstraints`` with the generated window From/To timing
+    constraints when a VI is compiled against the custom target. Those constraints
+    reference cells relative to the window wrapper instance, so the macro must be wrapped
+    with ``current_instance`` scoping (mirroring the FROM_TO handling in
+    ``process_constraints_template``). Without it, instance-relative constraints fail to
+    match cells inside the window when the window VHDL is encrypted.
+
+    Scans every ``.xdc`` and ``.xdc_template`` file in *folder* and wraps the
+    from-to-constraints macro line, leaving the macro token itself intact for LabVIEW FPGA
+    to replace later.
+
+    Args:
+        folder (str): Directory containing constraint files to process.
+        entity_path_to_window_wrapper (str | None): Hierarchical path to the window wrapper
+            instance. If falsy, no wrapping is performed.
+    """
+    if not os.path.isdir(folder) or not entity_path_to_window_wrapper:
+        return
+
+    def _wrap(match):
+        indent = match.group(1)
+        token = match.group(2)
+        return (
+            f"{indent}set TopInstance0 [current_instance .]\n"
+            f"{indent}current_instance {entity_path_to_window_wrapper}\n"
+            f"{indent}{token}\n"
+            f"{indent}current_instance -quiet\n"
+            f"{indent}current_instance $TopInstance0"
+        )
+
+    for filename in os.listdir(folder):
+        lowered = filename.lower()
+        if not (lowered.endswith(".xdc") or lowered.endswith(".xdc_template")):
+            continue
+        filepath = os.path.join(folder, filename)
+        with open(filepath, "r", encoding="utf-8") as f:
+            content = f.read()
+        new_content, count = _FROM_TO_CONSTRAINTS_MACRO_RE.subn(_wrap, content)
+        if count > 0:
+            with open(filepath, "w", encoding="utf-8") as f:
+                f.write(new_content)
+            reporter.detail(f"Wrapped macro_fromToConstraints with current_instance in {filename}")
+
+
 def process_constraints_template(config):
     """Process XDC constraint template files.
 

{labview_fpga_hdl_tools-2.0.0.dev0 → labview_fpga_hdl_tools-2.0.0.dev1}/pyproject.toml

@@ -4,7 +4,7 @@ build-backend = "poetry.core.masonry.api"
 
 [tool.poetry]
 name = "labview-fpga-hdl-tools"
-version = "2.0.0.dev0"
+version = "2.0.0.dev1"
 description = "LabVIEW FPGA HDL Tools"
 authors = [
   "Salvador Santolucito <salvador.santolucito@gmail.com>"