jitxexamples 2.0.0__tar.gz → 2.1.0__tar.gz

{jitxexamples-2.0.0 → jitxexamples-2.1.0}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.5
 Name: jitxexamples
-Version: 2.0.0
+Version: 2.1.0
 Summary: Library of example JITX components, substrates, and demo designs
 Project-URL: Homepage, https://jitx.com
 Project-URL: Documentation, https://docs.jitx.com

{jitxexamples-2.0.0 → jitxexamples-2.1.0}/README.md

@@ -69,10 +69,14 @@ at the repo root (published to the docs site), not here.
 Substrates define reusable PCB construction details. `generic_20layer.py` provides `Generic_Substrate`, a generic 20-layer stackup with dielectric/conductor materials, fabrication constraints, and via classes that designs can use directly or specialize.
 
 ### Pattern definitions (`src/jitxexamples/patterns/`)
-Patterns are small modules that each show one technique, written to be read; each ends in a design that translates with `jitx design build --dry`. `fenced_pour_outline.py` fences an arbitrary closed outline (an antipad, an RF cavity, a BGA breakout) with vias: a `Tag`, a `design_constraint(...).fence_via(...)` rule on the substrate, and a tagged `Pour` inside a `FencedOutline` circuit whose `GND` port connects to the board's ground net. A `KeepOut` over the same outline, which keeps pours and auto-placed vias out of the opening, is optional; the module adds one. Its design target is `jitxexamples.patterns.fenced_pour_outline.fenced_pour_outline_design`. To see the fence, run a full build (`jitx design build <target>`, which needs the runtime) and open the board with `jitx ui open --board --design <target>`.
+Patterns are small modules that each show one technique, written to be read; each ends in a design that translates with `jitx design build --dry`. `fenced_pour_outline.py` fences an arbitrary closed outline (an antipad, an RF cavity, a BGA breakout) with vias: a `Tag`, a `design_constraint(...).fence_via(...)` rule on the substrate, and a tagged `Pour` inside a `FencedOutline` circuit whose `GND` port connects to the board's ground net. A `KeepOut` over the same outline, which keeps pours and auto-placed vias out of the opening, is optional; the module adds one. Its design target is `jitxexamples.patterns.fenced_pour_outline.fenced_pour_outline_design`. To see the fence, run a full build (`jitx design build <target>`, which needs the runtime) and open the board with `jitx ui open --board --design <target>`. The module also has `CavityRing`, a closed ring turned inwards (a negative `offset`) so its vias land in a ground cavity pour's own copper, with a same-net anchor via; its target is `jitxexamples.patterns.fenced_pour_outline.cavity_ring_design`. `fence_count_range` gives the via counts to accept along an outline before a build is checked.
+
+The `layout_*` modules each show one design-rule technique on jitx 4.6. Each has offline tests and a runtime test, gated by `JITX_PATTERN_RUNTIME=1`, that measures the computed copper. Pours and vias: `layout_default_rules` (board defaults for trace width, clearance and pad relief, checked against the fab floors, with rules on power and ground net tags at a higher priority), `layout_thermal_classes` (relief per pad class chosen from the measured pad size, plus a direct connect on an exposed pad and an untagged part that joins its pour solidly because no relief rule matches it), `layout_heavy_copper_layer` (floors for one heavy inner layer with `OnLayer` on the priority ladder, with `heavy_layer_index` to find the layer and `heavy_layer_rules` to write the floors and the copies of the net-tag rules), `layout_stitched_pour` (a `stitch_via` rule on a pour tag, its pitch checked against the via and the fab, and `expected_stitch_sites` for the sites a build must fill) and `layout_edge_and_cutout` (pour pullback from the board edge with `IsBoardEdge`, and from cutouts, outline holes and via drills with `IsHole`). Routing: `layout_cpwg_two_row_fence` (a grounded coplanar line with two rows of fence vias, fenced through its routing structure, with functions for the coplanar gap, the row positions and counts, and the rows that reach the pour), `layout_qfn_escape` (a power trace stepped down to fit a QFN pad, with `escape_width` deriving the width from the pad, the nearest other pad and a chosen escape clearance), `layout_bga_escape` (a power trace stepped down to pass between BGA balls, with the width read from the balls), `layout_diff_pair_escape` (two differential pairs necked down at a fine-pitch device and held apart in the run, by tags on the routes), `layout_sensitive_net_clearance` (a clearance between the tags on an RF net and a switch-node net: the switch-node pour pulls back from the RF line while a GND pour stays at its default clearance) and `layout_routing_structure_by_tag` (routing structures applied by tag, with a neck structure on the escape).
 
 The `si_*` modules each show one signal-integrity constraint on jitx 4.6, on plain nets with code routes that close the path, and their docstrings paste the design-issues output they produced: `si_point_to_point` (timing and loss with a `TerminatingPinModel`), `si_series_part` (a `BridgingPinModel` through a series part), `si_via_model` (a via with `models`), `si_diff_pair` (intra-pair skew), `si_bundle_skew` (skew across pairs with `ConstrainReferenceDifference`), `si_daisy_chain` (an ordered chain with `>>`), `si_via_structure` (a via structure from `jitxlib.via_structures`) and `si_signal_constraint` (a `SignalConstraint` subclass); `si_parts` holds their fictional parts. The `pin_*` modules show SI constraints on pin-assigned paths: `pin_lane_polarity` (lane choice and P/N inversion on a provider that is one end of the path) and `pin_series_array` (channel choice through a pass-through part, both sides in one mapping). The `jitx-interconnect-constraints` and `jitx-pin-assignment` skills point at them as worked patterns.
 
+The code-layout modules each build a piece of physical layout in code: `code_route_basics` (code routes on one layer: a plain route, a `Route.Sketch` detour past a via column, and `Route.Config` overrides for trace width, trace space and a destination target, one of which tapers the trace into its pad), `serpentine_sections` (length-matched sections on four differential pairs, each a chain of code routes through `PairInsertion` and `PairPoint` control points whose section between the two `PairPoint`s may meander, each pair under its own serpentine or deskew rule), `wilkinson_tree` (a fenced 1:4 Wilkinson divider tree built from one 1:2 cell, with code routes from an input connector to four outputs and a timing constraint that matches the four paths; each line leaves its pad straight to a `RoutePoint`, and each that turns bends around a tagged ground copper square, and each divider body is fenced like a trace by a fence pour equal to its copper), `rf_connector_launch` (an SMA end launch into a fenced grounded coplanar line: a straight exit to a `RoutePoint` on the pad's axis, a small tagged ground copper square past it whose clearance rule to the line sets the bend radius, and a hyperbolic cutout in the ground under the centre pad), `hex_bga_escape` (two differential pairs out of a hex-grid BGA, split at a `PairPoint` at the ball field's edge so a tagged neck structure runs through the field and the full structure outside it), `qfn_thermal_and_power_fanout` (a grid of thermal vias in the RP2040's exposed pad with a matching soldermask and paste opening, and its `IOVDD` pins fanned out through escapes, trunks and vias to a 3.3 V plane) and `board_ground_pours` (a `GND` pour on every copper layer, all held by one through `GND` anchor via and pulled back from the board edge by an `IsBoardEdge` rule). Each has offline tests and a runtime test, gated by `JITX_PATTERN_RUNTIME=1`, that builds the design and measures the realized copper; run the runtime tests with a JITX runtime started at the repository root.
+
 ### Protocol definitions (`src/jitxexamples/protocols/`)
 High-speed protocols that `jitxlib.protocols` does not ship: port bundles plus a `SignalConstraint` whose skew limits cite their source and its scope in the module docstring. Each protocol module has a worked example beside it named `<protocol>_example.py`, a `SampleDesign` that nets a fictional controller to a real memory part and applies the constraint without `>>`. Today that is `memory/lpddr4.py` (Micron MT53E1G32D2FW-046 WT:B, an LPDDR4X/LPDDR4 part, target `jitxexamples.protocols.memory.lpddr4_example.LPDDR4ExampleDesign`) and `memory/ddr4.py` (Micron MT40A1G16TB-062E:F, target `jitxexamples.protocols.memory.ddr4_example.DDR4ExampleDesign`). The examples are not routed, so the design issues (each example's docstring shows the `issues(satisfied=True)` call) list each constrained path as `Unconnected Topology` until the board is routed.
 

{jitxexamples-2.0.0 → jitxexamples-2.1.0}/jumpstart-kits/js0-setup/JS0_Environment_Setup.md

@@ -177,7 +177,7 @@ Devin session (or ask it to reload/list skills) and verify with:
 ```text
 List the available skills related to JITX. Confirm whether you can see @jitx,
 @jitx-component-modeler, @jitx-circuit-builder, @jitx-substrate-modeler,
-@jitx-physical-layout, @jitx-interconnect-constraints, @jitx-pin-assignment,
+@jitx-code-layout, @jitx-interconnect-constraints, @jitx-pin-assignment,
 @jitx-code-review, and @jitx-mechanical.
 ```
 

jitxexamples-2.1.0/jumpstart-kits/js4-si-constraints/JS4_SI-Constraints_Runbook.md

@@ -0,0 +1,125 @@
+<!--
+JITX SI Constraints Runbook (JS4) · rev 3.0 · 2026-11-03
+Give this file to your AI coding agent (Claude Code, Codex / GPT, or Devin) and tell it to follow
+the file. Complete JS0 and JS1 Part 1 first, then START A NEW AGENT SESSION: a skills install only
+takes effect in a session started after it.
+-->
+
+# JITX SI Constraints Runbook (JS4)
+
+Each step below is a request, written the way you would ask an agent for the work. Follow them in
+order; at a **[HUMAN]** step, stop and wait for me. Drive `jitx-interconnect-constraints` for the
+constraints and the base `jitx` skill for the project. The ground truth is AMD UG863, *Versal
+Adaptive SoC PCB Design User Guide*, its LPDDR4/4x timing constraint rules and physical design
+rules: <https://docs.amd.com/r/en-US/ug863-versal-pcb-design>. Cite its revision wherever you use
+it. If you cannot read those tables, tell me what you tried and ask me for them. Where it leaves a
+choice, make it and tell me what you chose. Don't open
+`jitxexamples.jumpstart_kits.js4_si_constraints`, even where a skill offers it as an example: it is
+a finished answer to this task.
+
+**Prerequisites:** JS0 and JS1 Part 1 are done, and you have the `board.py` JS1 Part 1 produced;
+Python 3.12+; you can fetch from amd.com.
+
+Every part comes from the `jitxexamples` package; model none, and leave the FPGA's pin offer as it
+is:
+
+- `jumpstart_kits.vp1002_lpddr4x`: `circuit.VP1002LPDDR4X`, the JS1 VP1002 offering one x32
+  LPDDR4X interface, `bundles.VersalLPDDR4X`, with the pin swaps AMD allows, and
+  `pinout.LPDDR4X_X32`, the pins it offers. JITX picks the pins when the board is routed.
+- `components.memories.MT53E1G32D2FW_046_WT_B.MT53E1G32D2FW_046_WT_B`, the Micron memory.
+- `protocols.memory.lpddr4`: the `LPDDR4` bundles and `LPDDR4Constraint`, a reusable constraint
+  whose `LPDDR4ConstraintParams` defaults come from a different guide, UG583.
+- `jumpstart_kits.vp1002_lpddr4x.package_delays.SYNTHETIC_CSV`, the path of the FPGA's package delay
+  file, with columns named after Vivado's I/O ports export (UG899 Appendix A): one row per pin of
+  memory triplet M0, with its minimum and maximum delay in ps, both legs of a P/N pair alike. Its
+  values are synthetic estimates, not AMD data; say so wherever you report a delay that includes
+  them. Its `Pin Number` is the ball: map it to an FPGA port with `ball_to_rc` from
+  `jumpstart_kits.js1_stackup_components.versal_fpga.tools.generate_pinout` and the FPGA's
+  `ball_assignments()`, and check one: ball AT20 is `IO_L8P_N2P4_M0P70_701`.
+
+## Steps
+
+**0 · Preflight.**
+Tell me this runbook's revision, from the comment at the top, and confirm
+`jitx-interconnect-constraints` is invocable.
+
+**1 · Project.**
+Set up a new JITX project for this board in an empty directory, with `jitxexamples` as a dependency
+and my JS1 Part 1 `board.py` copied in, and build the seeded design.
+
+**2 · Connect.**
+Place the VP1002 and the Micron on my JS1 board and substrate, require the FPGA's interface and net
+it to the memory with plain nets, each channel's one CKE to both of the memory's CKE balls. Build
+it.
+
+**3 · [HUMAN] Constraint plan.**
+First tell me, in a few sentences, what a JITX timing constraint measures along a path and where
+each part of that measurement comes from. Then show me every UG863 LPDDR4/4x timing and physical
+rule in a table: its value, and how you will express it in JITX or why you won't. Turn the 3600 mil
+trace length rule into a delay from the substrate's own velocity: about 525 ps on the JS1
+striplines. Name the routing structures against UG863's impedance targets, and the closest with the
+gap if none is in range. Say how you will count package delay and via delay, quoting what UG863 says
+about package delay. A `TerminatingPinModel` adds its pin's package delay to every path on that pin,
+delay limits included, so with the pin models step 4 asks for, package delay counts toward the 3600
+mil limit: say so, and what that leaves for the trace with the file's delays. Flag where the FPGA's
+offer differs from the table. Wait for my approval.
+
+**4 · Constraints.**
+Write the approved rules as one reusable constraint for this link that takes the routing structures
+and the limits as arguments and builds on `LPDDR4Constraint`, and apply it. Give each FPGA pin in
+the package delay file a `TerminatingPinModel` at the midpoint of its minimum and maximum, reading
+the file by column name and skipping rows with no delay, as a full export lists every pin; leave
+the memory's pins without one.
+Build, and check the issues.
+Expect 66 skews (per channel the CK pair, two CKE, two CS and six CA; per byte the DQS pair, DQS
+to CK, DMI and eight DQ) and 56 delay limits. Unrouted, each sits in its own `Unassigned Pin on
+Path` group, except that each CKE ball's skew and delay share one group reporting that ball's path
+unrouted (`No path for signal constraint`, or a `Signal path` line ending `is not routed yet`): 118
+`NOT MET` groups, then `met Satisfied`, the routing check. Map any other count to these. On jitx
+4.6.0 the report may name a path's FPGA end through a net on the required bundle, as in
+`RESET_n.ch[0].ca[0]`; the path is still that signal's.
+
+**5 · Verify.**
+Give the JS1 microvias you will route through a delay model, on subclasses in this project, not in
+`board.py`: the time across the via's dielectric from the middle of its top copper to the middle of
+its bottom copper, D·√Dk / c, from the substrate's own thicknesses and Dk, with no loss. Then write
+a verification design that code-routes one channel B byte lane, its CK pair, its CKE (FPGA pin to
+one CKE ball, on to the other) and one CA bit, on the inner striplines through those microvias in
+the pads. Expect 15 Skew and 12 Time lines and no `Using placeholder model` line; report each
+against its limit, how much of each Time and each Skew is package delay, and what UG863's layout
+rules would flag. Don't match lengths.
+
+Then run the skills' checks and `jitx-code-review`, fix what they find apart from unrouted paths,
+and report each result.
+
+**6 · [HUMAN] Change a requirement.**
+Invite me to change a requirement, suggesting: *"Our SI team wants DQ and DMI within ±50 ps of DQS.
+Change that limit and show me where the routed paths stand."* Change only that limit, in one place,
+rebuild the verification design, and show me the new limit as the report prints it and each routed
+DQ and DMI skew against it, from the new report: the router may lay the routes differently. Then
+run step 5's checks again.
+
+## Done when
+
+- The design binds my JS1 substrate, uses `VP1002LPDDR4X`'s pin offer unchanged, and nets the
+  interface to the memory with plain nets, one CKE per channel to both CKE balls.
+- The step 3 table covers every UG863 LPDDR4/4x timing and physical rule with its revision, each
+  applied or left out with a reason; the 3600 mil rule is a delay derived from the substrate's
+  velocity; the impedance gap is reported, with no width invented. Step 3 stopped before any
+  constraint was written.
+- The constraint is one reusable class or function that takes the structures and limits as
+  arguments, and the shipping design reports its 66 skews and 56 delay limits, unmeasured, in 118
+  `NOT MET` groups.
+- Each FPGA pin in the package delay file carries a `TerminatingPinModel` at the midpoint of its
+  minimum and maximum, read from the file by column name; the memory's pins carry none. Every report
+  of a delay that includes them says the values are synthetic.
+- The microvias the verification design routes through carry a delay model from the substrate's
+  thicknesses and Dk, and `board.py` is unchanged.
+- The verification design reports 15 Skew lines and 12 Time lines and no placeholder model, each set
+  against its limit.
+- `pyright` passes with zero suppressions; `pytest` passes for any tests you wrote; `jitx design
+  find` shows no import failures; every design builds; and `jitx-code-review` leaves no CRITICAL
+  finding (every result reported, with the reason for each WARNING kept), after step 5 and again
+  after step 6.
+- After step 6 exactly one limit has changed, and the verification design reports each DQ and DMI
+  skew against ±50 ps.

jitxexamples-2.1.0/jumpstart-kits/js4-si-constraints/README.md

@@ -0,0 +1,113 @@
+# JS4: SI Constraints
+
+**Shortcut:** {download}`Download the runbook <JS4_SI-Constraints_Runbook.md>`, give it to your AI
+coding agent, and tell it to follow the file.
+
+Turn a vendor's layout guide into signal-integrity constraints by prompting an agent that drives
+`jitx-interconnect-constraints`. The agent reads AMD UG863's LPDDR4/4x rules for the link from the
+JS1 VP1002 FPGA to a Micron MT53E1G32D2FW LPDDR4X memory and writes the timing rules and the trace
+length rule as one reusable constraint: skew limits, the length rule turned into a delay limit
+through the stackup's own velocity, routing structures and reference planes. It gives the FPGA's
+pins package delays from a supplied file of synthetic estimates (not AMD data) and the board's
+microvias a delay model, then code-routes one byte lane, a clock, the clock enable and an address
+bit, and JITX measures each routed path against its limits.
+
+## What you learn
+
+A timing constraint in JITX is a limit on a path, written in code. It names the path from one pin
+to another through the nets, and a limit on that path's delay or on the difference between two
+paths' delays. JITX adds up everything on the path: the package delay inside each end pin, given as
+a pin model; each trace, from its routing structure's velocity on the layer it runs on; each via,
+from its delay model; and any part the path passes through, from that part's pin model. The issue
+report sets each routed path's sum against its limit.
+
+Because the constraint is code, its limits are arguments. In this kit the agent writes UG863's rules
+once, as one constraint for this link. A tighter requirement from your SI team is one changed value
+and a rebuild (gate 2 below). A revision of UG863 that changes only limits changes numbers, not
+code. The next board with this link, or another stackup, takes the same constraint with its own
+routing structures. The package delays come from a file, so a new export changes an input, not the
+constraint; the via models are code on the stackup's own materials, so a new stackup needs its own.
+The interface is the example; what you learn is how to capture a guide's timing rules once and carry
+them from board to board.
+
+## What the kit supplies and leaves out
+
+UG863 says "Include adaptive SoC package delays for all skew calculations", and "Include package
+delay in routing constraints when determining signal trace lengths unless otherwise specified". It
+takes the delays from Vivado's per-pin export, at the midpoint of each pin's minimum and maximum.
+AMD publishes them only through Vivado, and the VP1002's were not available for this kit, so the
+kit supplies a package delay file with the export's column names whose values are synthetic
+estimates, not AMD data; both legs of each differential pair get the same value. The agent turns it
+into the pin models.
+
+A pin model adds its delay to every path on that pin, the delay limit included, so this kit counts
+package delay toward the 3600 mil rule, which UG863's table calls a PCB trace length. That is the
+conservative reading: it leaves the trace about 2280 to 2940 mil on the length-limited pins with
+these estimates. The other reading holds the trace alone to 3600 mil, and needs each path's limit
+raised by its own pin's package delay, which is not known until JITX assigns the pins. The agent
+shows you the reading it applies, and what it leaves for the trace, at gate 1. On your own board,
+export the real delays from Vivado, check their column names, and point the same code at that file.
+
+The via delay model is first order: the time to cross the dielectric from the middle of one copper
+layer to the middle of the next, from the stackup's own thicknesses and Dk. It leaves out the pad
+and antipad, so it is a floor on each via's delay, not a characterization. The agent puts it on
+JS4's own copies of the JS1 microvias; your JS1 `board.py` stays as it is.
+
+Some of UG863 stays outside the constraint. Spacing, via counts and which layer a group runs on are
+layout rules for a layout review. JS4 does not match lengths: the verification routes stay as
+routed, so some miss their limits, and a skew between two different FPGA pins includes their
+package delays' difference, synthetic here. A miss shows the check working, not a fault for the
+agent to fix.
+
+The FPGA comes from the `jitxexamples` package with its LPDDR4X pin swaps already offered, so JITX
+picks its pins when the board is routed; [JS3](../js3-pin-assignment/) teaches that part. JS4
+exports no XDC, and validating the FPGA pins in Vivado stays your step.
+
+## Before you start
+
+- Finish [JS0](../js0-setup/) and [JS1 Part 1](../js1-stackup-components/part1-stackup/). The
+  design uses the substrate you built there.
+- Start a new agent session. A skills install only takes effect in a session started after it.
+- Allow about two hours of agent time, plus the time you spend at the two decisions below.
+- Have your JS1 Part 1 `board.py` at hand. Your agent needs network access to amd.com.
+- To compare this run with your current flow afterward, note now roughly how long it takes your
+  team to get a memory interface's layout-guide rules into the layout tool's constraints, and how
+  long a changed limit takes to reach the constraints and the check
+  against the routed board. During the run, time it, and time gate 2 from your request to the
+  agent's report.
+
+## What the agent asks of you
+
+Two `[HUMAN]` gates stop for you:
+
+1. **Approve the constraint plan.** The agent shows you every UG863 LPDDR4/4x rule beside how it
+   will express it in JITX, or why it won't, with the routing structures it will use, the gap to
+   UG863's impedance targets, how it will model package and via delay, and the one clock enable per
+   channel the FPGA offers where UG863 lists two for a dual-rank memory. You approve before it
+   writes any constraint.
+2. **Change a requirement.** Ask for a tighter limit (the runbook suggests DQ and DMI within ±50 ps
+   of DQS). The agent changes that one value, rebuilds, and shows you the new limit in the report
+   and each routed DQ and DMI path's verdict against it.
+
+## After the run
+
+You can now write a layout guide's timing and length rules as constraints that JITX measures on the
+routed board, with the package and via delays on the path. Set gate 2's time against the same change
+in your current flow, through to the check against the routed board; that comparison counts for more
+than the whole run's time against your note, since a first run includes learning. Length matching,
+the step toward meeting these limits, is outside this kit. Then write the constraints for an
+interface from one of your own boards, from its vendor's layout guide and your own package delay
+export, and time it against the same note: that second run is the fairer measure.
+
+## Files
+
+- [The runbook](JS4_SI-Constraints_Runbook.md), to read here;
+  {download}`download it <JS4_SI-Constraints_Runbook.md>` to give to your agent. It names the AMD
+  guide the agent fetches.
+- The synthetic package delay file, `package_delays_synthetic.csv`, ships inside the `jitxexamples`
+  package next to
+  [`jumpstart_kits.vp1002_lpddr4x.package_delays`](https://github.com/JITx-Inc/jitx-examples/tree/main/src/jitxexamples/jumpstart_kits/vp1002_lpddr4x),
+  which generates it and says how.
+- The reference solution, module
+  [`jitxexamples.jumpstart_kits.js4_si_constraints`](https://github.com/JITx-Inc/jitx-examples/tree/main/src/jitxexamples/jumpstart_kits/js4_si_constraints)
+  in the `jitxexamples` package (`pip install jitxexamples`).

{jitxexamples-2.0.0 → jitxexamples-2.1.0}/lint.log

@@ -1,4 +1,4 @@
 cmd [1] | ruff check .
 All checks passed!
 cmd [2] | ruff format --check --diff .
-227 files already formatted
+269 files already formatted

jitxexamples-2.1.0/src/jitxexamples/components/connectors/wurth_elektronik_60312202114514.py

@@ -0,0 +1,142 @@
+"""
+60312202114514 / WR-SMA end launch jack
+=======================================
+
+This module provides a component definition for the Würth Elektronik
+60312202114514, a WR-SMA 50 ohm end launch jack with a flat centre tab, for a
+1.6 mm board.
+
+The land pattern comes from the recommended land pattern of the Würth
+datasheet drawing, revision 001.001. All dimensions are in mm:
+
+- centre pad 0.61 +/-0.05 wide and at least 1.97 long, from the board end;
+- ground pads 9.9 +/-0.05 outer and 7.1 +/-0.05 inner overall width, 5.0
+  +/-0.05 long, on the top and on the bottom of the board.
+
+The land pattern has no ground vias. The drawing gives the part as 50 ohm from
+DC to 18 GHz, with VSWR 1.2 and insertion loss 0.14 dB at most up to
+12.4 GHz, and notes that "The VSWR in application varies decisively according
+to PCB layout".
+
+The land pattern's frame is the frame of the vendor's HFSS model
+(``HFSS_MODEL_URL``): x = 0 is the body face, which sits on the board edge,
++x runs into the board along the centre pad, and the pads are centred on
+y = 0. Place the part with its origin on the board edge and its +x axis
+pointing into the board.
+
+The courtyard, on the top and on the bottom, covers what sits on the board:
+the pads, and the shell's ground tabs, which the vendor model puts at x 0 to
+4.76 within the body's 9.52 mm width. It starts at the board edge, since the
+body behind the face hangs off the board.
+"""
+
+from __future__ import annotations
+
+from jitx.component import Component
+from jitx.feature import Courtyard
+from jitx.landpattern import Landpattern, PadMapping
+from jitx.layerindex import Side
+from jitx.net import Port
+from jitx.shapes.composites import rectangle
+from jitxlib.landpatterns.pads import SMDPad
+from jitxlib.symbols.box import BoxSymbol
+
+CENTER_PAD_WIDTH = 0.61
+"""Datasheet recommended land pattern: centre pad 0.61 +/-0.05 wide."""
+
+CENTER_PAD_LENGTH = 1.97
+"""Datasheet recommended land pattern: centre pad 1.97 minimum from the PCB
+end."""
+
+GROUND_OUTER = 9.9
+"""Datasheet recommended land pattern: ground pads 9.9 +/-0.05 outer overall
+width."""
+
+GROUND_INNER = 7.1
+"""Datasheet recommended land pattern: ground pads 7.1 +/-0.05 inner overall
+width."""
+
+GROUND_LENGTH = 5.0
+"""Datasheet recommended land pattern: ground pads 5.0 +/-0.05 long, top and
+bottom."""
+
+BODY_WIDTH = 9.52
+"""Datasheet: body 9.52 by 7.92; the vendor model spans y -4.76 to 4.76, so
+9.52 is the width across the board edge."""
+
+TAB_REACH = 4.76
+"""Vendor model (``HFSS_MODEL_URL``): the shell's ground tabs reach x = 4.76
+into the board."""
+
+COURTYARD_EXCESS = 0.25
+"""Courtyard margin beyond the pads and tabs, in mm, as the Molex and
+Weidmuller connectors in this package use."""
+
+HFSS_MODEL_URL = (
+    "https://www.we-online.com/components/products/download/"
+    "ANSYS_60312202114514%20%28rev25a%29.a3dcomp"
+)
+"""The vendor's HFSS 3D component (``.a3dcomp``) for this part, rev25a,
+kept for later use: nothing in this repository downloads or reads it yet.
+The file was recorded by 2026-11-05 as 390,182 bytes, with the SHA-256 in
+``HFSS_MODEL_SHA256``; check a download against both. Its native frame is
+the land pattern's frame: x = 0 at the body face on the board edge, +x into
+the board, and z = 0 on the top copper."""
+
+HFSS_MODEL_SHA256 = "54cdf702be7343e09a787fa0de413e77984569b4b6bcdddee27d8adccfc90959"
+"""SHA-256 of the rev25a file at ``HFSS_MODEL_URL``, to check a download
+against."""
+
+_GROUND_PAD_WIDTH = (GROUND_OUTER - GROUND_INNER) / 2
+_GROUND_PAD_Y = (GROUND_OUTER + GROUND_INNER) / 4
+
+
+class WurthLaunchLandpattern(Landpattern):
+    """The centre pad, and a ground pad on each side of it on the top and on
+    the bottom of the board, each with a soldermask opening and paste, and a
+    courtyard on each side."""
+
+    def __init__(self) -> None:
+        self.sig = SMDPad(rectangle(CENTER_PAD_LENGTH, CENTER_PAD_WIDTH)).at(
+            CENTER_PAD_LENGTH / 2, 0.0
+        )
+        self.gnd = [
+            SMDPad(rectangle(GROUND_LENGTH, _GROUND_PAD_WIDTH)).at(
+                GROUND_LENGTH / 2, y, on=side
+            )
+            for side in (Side.Top, Side.Bottom)
+            for y in (_GROUND_PAD_Y, -_GROUND_PAD_Y)
+        ]
+        reach = max(GROUND_LENGTH, TAB_REACH) + COURTYARD_EXCESS
+        half = max(GROUND_OUTER, BODY_WIDTH) / 2 + COURTYARD_EXCESS
+        self.courtyard = [
+            Courtyard(rectangle(reach, 2 * half).at(reach / 2, 0.0), side=side)
+            for side in (Side.Top, Side.Bottom)
+        ]
+
+
+class Wurth60312202114514(Component):
+    """Würth Elektronik WR-SMA 60312202114514, 50 ohm end launch jack, flat
+    tab, for a 1.6 mm board."""
+
+    manufacturer = "Würth Elektronik"
+    mpn = "60312202114514"
+    datasheet = (
+        "https://www.we-online.com/components/products/datasheet/60312202114514.pdf"
+    )
+    reference_designator_prefix = "J"
+
+    sig = Port()
+    """The centre pin."""
+    gnd = Port()
+    """The shell: all four ground pads."""
+
+    def __init__(self) -> None:
+        self.landpattern = WurthLaunchLandpattern()
+        self.symbol = BoxSymbol()
+        self.mappings = [
+            PadMapping({self.sig: self.landpattern.sig, self.gnd: self.landpattern.gnd})
+        ]
+
+
+Device: type[Wurth60312202114514] = Wurth60312202114514

{jitxexamples-2.0.0 → jitxexamples-2.1.0}/src/jitxexamples/components/power_switchmode/texas_instruments_TPS62933DRLR.py

@@ -400,13 +400,13 @@ class TPS62933DRLRCircuit(Circuit):
         BstTag().assign(self.BST_MID)
 
         # Design rule constraints
-        # 0.5mm clearance for SW_NODE (switch node needs clearance from other nets)
+        # 0.25mm clearance for SW_NODE (switch node needs clearance from other nets)
         self.sw_clearance_rule = design_constraint(SwTag(), True).clearance(0.25)
 
-        # 0.5mm clearance for BST_MID (bootstrap node needs clearance from other nets)
+        # 0.25mm clearance for BST_MID (bootstrap node needs clearance from other nets)
         self.bst_clearance_rule = design_constraint(BstTag(), True).clearance(0.25)
 
-        # 1.0mm trace width for VIN and VOUT power nets
+        # 0.25mm trace width for VIN and VOUT power nets
         self.power_trace_rule = design_constraint(PowerNetTag()).trace_width(0.25)
 
 

{jitxexamples-2.0.0 → jitxexamples-2.1.0}/src/jitxexamples/demos/si_bga_optimization/bga_escape.py

@@ -358,7 +358,6 @@ class BGALink(Circuit):
                         lane.signal_via_fence_shape,
                         layer=spec.upper_ref_fence_pour_layer,
                         rank=_ANTIPAD_FENCE_POUR_RANK,
-                        isolate=0.0,
                     )
                     spec.upper_ref_fence_tag.assign(p)
                     signal_via_fence_pours.append(p)
@@ -367,7 +366,6 @@ class BGALink(Circuit):
                     lane.deskew_fence_pour_shape,
                     layer=spec.deskew_antipad_fence_pour_layer,
                     rank=_DESKEW_ANTIPAD_FENCE_POUR_RANK,
-                    isolate=0.0,
                 )
                 spec.deskew_antipad_fence_tag.assign(dp)
                 deskew_fence_pours.append(dp)
@@ -389,13 +387,21 @@ class BGALink(Circuit):
         n_conductors = len(substrate.stackup.conductors)
         gnd_pour_shape = rectangle(48, 48, radius=4)
         self.gnd_pours = [
-            Pour(gnd_pour_shape, layer=layer, rank=1, isolate=0.0)
-            for layer in range(n_conductors)
+            Pour(gnd_pour_shape, layer=layer, rank=1) for layer in range(n_conductors)
         ]
 
         # GND-via stitching around every BGA GND ball. The site-planning
         # helper returns pure data; this Circuit constructs the actual
         # Via instances and owns them as a named structural member.
+        # These stay code-placed rather than a ``stitch_via`` rule: each is
+        # via-in-pad at a GND ball centre, and its via class reaches the
+        # reference plane below that row pair's signal layer. The
+        # code-placed vias also count as same-net objects for the GND pours
+        # on the layers they span: a pour with no pad or via of its own net
+        # inside it comes back empty (measured on jitx 4.6). A stitch
+        # rule's own vias do not hold such a pour: the runtime still places
+        # them on the removed pour's footprint, with no issue (measured on
+        # jitx 4.6).
         self.gnd_stitching_vias = [
             substrate.gnd_via[signal_layer]().at(*bga.ball_center(row, col))
             for row, col, signal_layer in gnd_pad_via_sites()

{jitxexamples-2.0.0 → jitxexamples-2.1.0}/src/jitxexamples/demos/si_bga_optimization/substrate.py

@@ -97,7 +97,6 @@ def _rs_uncoupled_layer(signal_layer: int) -> "RoutingStructure.Layer":
             clearance=0.135,
             velocity=VEL_STRIPLINE,
             insertion_loss=0.018,
-            neck_down=RoutingStructure.NeckDown(trace_width=0.10, clearance=0.135),
         )
         .reference(signal_layer - 1, 1.0)
         .reference(signal_layer + 1, 1.0)

jitxexamples-2.1.0/src/jitxexamples/jumpstart_kits/js4_si_constraints/__init__.py

@@ -0,0 +1,14 @@
+"""JS4 reference solution: SI constraints on the JS1 VP1002 driving a Micron
+LPDDR4X device.
+
+- :py:mod:`.constraint`: UG863's skew limits and trace length budget as a
+  reusable constraint.
+- :py:mod:`.models`: package delay pin models from a package delay file,
+  and microvia delay models from the stackup.
+- :py:mod:`.main`: the shipping design, with no routes.
+- :py:mod:`.proof`: code-routed verification designs that measure the
+  constraints, before and after a tighter limit.
+
+The FPGA's pin offer is a supplied part,
+:py:mod:`jitxexamples.jumpstart_kits.vp1002_lpddr4x`.
+"""