jitxexamples 1.6.2__tar.gz → 2.0.0__tar.gz

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Files changed (359) hide show
  1. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/.github/workflows/build.yaml +3 -0
  2. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/.github/workflows/mirror-main.yml +4 -3
  3. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/.gitignore +1 -3
  4. jitxexamples-2.0.0/CLAUDE.md +111 -0
  5. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/PKG-INFO +6 -7
  6. jitxexamples-2.0.0/README.md +157 -0
  7. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/docs/Makefile +3 -2
  8. jitxexamples-2.0.0/docs/requirements.txt +8 -0
  9. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/docs/source/conf.py +1 -1
  10. jitxexamples-2.0.0/docs/source/index.rst +11 -0
  11. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/jumpstart-kits/README.md +7 -9
  12. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/jumpstart-kits/js0-setup/JS0_Environment_Setup.md +20 -17
  13. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/jumpstart-kits/js0-setup/JS0_Reference_Companion.md +4 -4
  14. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/jumpstart-kits/js0-setup/JS0_Setup_Runbook.md +4 -4
  15. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/jumpstart-kits/js0-setup/README.md +1 -8
  16. jitxexamples-2.0.0/jumpstart-kits/js1-stackup-components/README.md +59 -0
  17. jitxexamples-2.0.0/jumpstart-kits/js1-stackup-components/part1-stackup/JS1_Part1_Stackup-from-Fab-CSV_Runbook.md +67 -0
  18. jitxexamples-2.0.0/jumpstart-kits/js1-stackup-components/part1-stackup/README.md +59 -0
  19. jitxexamples-1.6.2/jumpstart-kits/js1-stackup-components/part3-versal-fpga/JS1_Part3_Reference_Companion.md → jitxexamples-2.0.0/jumpstart-kits/js1-stackup-components/part2-versal-fpga/JS1_Part2_Reference_Companion.md +11 -11
  20. jitxexamples-1.6.2/jumpstart-kits/js1-stackup-components/part3-versal-fpga/JS1_Part3_Versal-FPGA-from-Pin-File_Runbook.md → jitxexamples-2.0.0/jumpstart-kits/js1-stackup-components/part2-versal-fpga/JS1_Part2_Versal-FPGA-from-Pin-File_Runbook.md +37 -37
  21. {jitxexamples-1.6.2/jumpstart-kits/js1-stackup-components/part3-versal-fpga → jitxexamples-2.0.0/jumpstart-kits/js1-stackup-components/part2-versal-fpga}/README.md +33 -19
  22. jitxexamples-2.0.0/jumpstart-kits/js2-circuits/JS2_Circuits-from-Datasheet_Runbook.md +93 -0
  23. jitxexamples-2.0.0/jumpstart-kits/js2-circuits/README.md +65 -0
  24. jitxexamples-2.0.0/jumpstart-kits/js3-pin-assignment/README.md +39 -0
  25. jitxexamples-2.0.0/jumpstart-kits/js3-pin-assignment/part1-mcu-muxing/JS3_Part1_MCU-Peripheral-Muxing_Runbook.md +71 -0
  26. jitxexamples-2.0.0/jumpstart-kits/js3-pin-assignment/part1-mcu-muxing/README.md +58 -0
  27. jitxexamples-2.0.0/jumpstart-kits/js3-pin-assignment/part2-usb-esd/JS3_Part2_USB-through-ESD_Runbook.md +83 -0
  28. jitxexamples-2.0.0/jumpstart-kits/js3-pin-assignment/part2-usb-esd/README.md +71 -0
  29. jitxexamples-2.0.0/jumpstart-kits/js4-fpga-lpddr4x/README.md +34 -0
  30. jitxexamples-2.0.0/jumpstart-kits/js4-fpga-lpddr4x/part1-lpddr4x-pins/JS4_Part1_LPDDR4X-Pin-Assignment_Runbook.md +90 -0
  31. jitxexamples-2.0.0/jumpstart-kits/js4-fpga-lpddr4x/part1-lpddr4x-pins/README.md +86 -0
  32. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/lint.log +1 -1
  33. jitxexamples-2.0.0/parts.lock.json +413 -0
  34. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/pyproject.toml +28 -23
  35. jitxexamples-2.0.0/src/jitxexamples/components/__init__.py +3 -0
  36. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/audio_amps/PAM8302AADCR.py +26 -19
  37. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/battery_managers/BQ24078RGTR.py +94 -43
  38. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/battery_managers/PH2_0_2PWB.py +4 -0
  39. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/bjts/BJT_2N3904S_RTKPS.py +4 -0
  40. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/buttons/PTS810SJM250SMTRLFS.py +20 -14
  41. jitxexamples-2.0.0/src/jitxexamples/components/buttons/__init__.py +3 -0
  42. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/buttons/xunpu_TS_1088_AR02016.py +3 -5
  43. jitxexamples-2.0.0/src/jitxexamples/components/connectors/__init__.py +3 -0
  44. jitxexamples-2.0.0/src/jitxexamples/components/connectors/bel_fuse_0826_1G1T_23_F.py +358 -0
  45. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/connectors/hirose_electric_co_ltd_U_FL_R_SMT_10.py +17 -16
  46. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/connectors/molex_2012670005.py +67 -58
  47. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/connectors/myoung_MY_1632_03.py +4 -0
  48. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/connectors/pulse_electronics_JD0_0001NL.py +7 -9
  49. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/connectors/q_j_CR2032_BS_6_1.py +4 -0
  50. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/crystals/HC_49SM12MHz20pF30ppm.py +4 -0
  51. jitxexamples-2.0.0/src/jitxexamples/components/crystals/__init__.py +3 -0
  52. jitxexamples-2.0.0/src/jitxexamples/components/crystals/seiko_epson_TSX_3225.csv +265 -0
  53. jitxexamples-2.0.0/src/jitxexamples/components/crystals/seiko_epson_TSX_3225.py +424 -0
  54. jitxexamples-2.0.0/src/jitxexamples/components/digital_isolators/PUSB3FR4.py +143 -0
  55. jitxexamples-2.0.0/src/jitxexamples/components/ethernet_phys/__init__.py +3 -0
  56. jitxexamples-2.0.0/src/jitxexamples/components/ethernet_phys/microchip_KSZ9031RNX.py +408 -0
  57. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/fets_n_ch/BSN20.py +4 -0
  58. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/fets_n_ch/BSS138.py +4 -0
  59. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/fets_p_ch/AO3401A.py +6 -2
  60. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/fets_p_ch/AO6409.py +5 -1
  61. jitxexamples-2.0.0/src/jitxexamples/components/fets_p_ch/NTF6P02T3G.py +169 -0
  62. jitxexamples-2.0.0/src/jitxexamples/components/flash/__init__.py +3 -0
  63. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/flash/winbond_W25Q128JVSIQ.py +23 -22
  64. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/isolators/texas_instruments_ISO1211.py +32 -33
  65. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/led_drivers/IS31FL3236A_QFLS2_TR.py +4 -0
  66. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/leds/KT_0603G.py +8 -10
  67. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/leds/KT_0603R.py +8 -10
  68. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/leds/KT_0603W.py +8 -10
  69. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/leds/KT_0603Y.py +8 -10
  70. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/leds/WS2816C_2121.py +4 -0
  71. jitxexamples-2.0.0/src/jitxexamples/components/leds/__init__.py +3 -0
  72. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/leds/foshan_nationstar_optoelectronics_FM_B2020RGBA_HG.py +4 -0
  73. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/level_translators/logic_level_shifter.py +15 -8
  74. jitxexamples-2.0.0/src/jitxexamples/components/logic/__init__.py +3 -0
  75. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/logic/texas_instruments_SN74HC14PWR.py +22 -16
  76. jitxexamples-2.0.0/src/jitxexamples/components/mcus/__init__.py +3 -0
  77. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/mcus/nordic_NRF52840_QIAA_R.py +62 -49
  78. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/mcus/raspberry_pi_RP2040.py +148 -107
  79. jitxexamples-2.0.0/src/jitxexamples/components/memories/MT40A1G16TB_062E_F.py +269 -0
  80. jitxexamples-2.0.0/src/jitxexamples/components/memories/MT53E1G32D2FW_046_WT_B.py +322 -0
  81. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/memories/W25Q128JVSIQTR.py +4 -0
  82. jitxexamples-2.0.0/src/jitxexamples/components/microphones/__init__.py +3 -0
  83. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/microphones/allpower_AP3722AT.py +15 -11
  84. jitxexamples-2.0.0/src/jitxexamples/components/opamps/__init__.py +3 -0
  85. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/opamps/stmicroelectronics_TS971ILT.py +10 -8
  86. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/opamps/texas_instruments_TLV314IDBVR.py +13 -12
  87. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/passives/RK09K1130AP5.py +4 -0
  88. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/power_linear_regulators/AP2125K_2_8TRG1.py +19 -17
  89. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/power_linear_regulators/NCP1117LPST33T3G.py +18 -16
  90. jitxexamples-2.0.0/src/jitxexamples/components/power_linear_regulators/__init__.py +3 -0
  91. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/power_linear_regulators/analog_devices_LT1763CS8.py +48 -50
  92. jitxexamples-2.0.0/src/jitxexamples/components/power_linear_regulators/texas_instruments_LM1117LD.py +109 -0
  93. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/power_switches/high_side_switch.py +14 -8
  94. jitxexamples-2.0.0/src/jitxexamples/components/power_switchmode/__init__.py +3 -0
  95. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/power_switchmode/texas_instruments_TPS62933DRLR.py +121 -88
  96. jitxexamples-2.0.0/src/jitxexamples/components/sensors/__init__.py +3 -0
  97. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/sensors/stmicroelectronics_LIS3DHTR.py +40 -24
  98. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/sensors_distance/VL53L0CXV0DH_1.py +16 -10
  99. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/switches/MK_12C02_G025.py +4 -0
  100. jitxexamples-2.0.0/src/jitxexamples/components/timers/__init__.py +3 -0
  101. jitxexamples-2.0.0/src/jitxexamples/components/transceivers/__init__.py +3 -0
  102. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/transceivers/texas_instruments_SN65HVD1781DR.py +36 -34
  103. jitxexamples-2.0.0/src/jitxexamples/components/transistors/__init__.py +3 -0
  104. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/components/transistors/on_semiconductor_NTA4151PT1G.py +4 -0
  105. jitxexamples-2.0.0/src/jitxexamples/demos/__init__.py +3 -0
  106. jitxexamples-2.0.0/src/jitxexamples/demos/si_bga_optimization/__init__.py +3 -0
  107. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/demos/si_bga_optimization/bga_escape.py +6 -4
  108. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/__init__.py +3 -0
  109. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js1_stackup_components/__init__.py +3 -0
  110. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/jumpstart_kits/js1_stackup_components/hdi_stackup/board.py +143 -70
  111. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/jumpstart_kits/js1_stackup_components/hdi_stackup/main.py +2 -1
  112. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js1_stackup_components/versal_fpga/__init__.py +43 -0
  113. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/jumpstart_kits/js1_stackup_components/versal_fpga/circuit.py +43 -30
  114. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/jumpstart_kits/js1_stackup_components/versal_fpga/main.py +2 -3
  115. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/jumpstart_kits/js1_stackup_components/versal_fpga/symbols.py +45 -0
  116. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js1_stackup_components/versal_fpga/tools/__init__.py +3 -0
  117. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/jumpstart_kits/js1_stackup_components/versal_fpga/tools/generate_pinout.py +103 -7
  118. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/jumpstart_kits/js1_stackup_components/versal_fpga/xcvp1002.py +202 -3
  119. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js2_circuits/__init__.py +9 -0
  120. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js2_circuits/main.py +179 -0
  121. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js2_circuits/phy.py +461 -0
  122. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js2_circuits/straps.py +124 -0
  123. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js3_pin_assignment/mcu_muxing/main.py +144 -0
  124. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js3_pin_assignment/mcu_muxing/verify.py +86 -0
  125. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js3_pin_assignment/usb_esd/esd.py +62 -0
  126. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js3_pin_assignment/usb_esd/main.py +114 -0
  127. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js3_pin_assignment/usb_esd/verify.py +198 -0
  128. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js4_fpga_lpddr4x/__init__.py +13 -0
  129. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js4_fpga_lpddr4x/bundles.py +54 -0
  130. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js4_fpga_lpddr4x/constraint.py +64 -0
  131. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js4_fpga_lpddr4x/fpga.py +84 -0
  132. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js4_fpga_lpddr4x/main.py +114 -0
  133. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js4_fpga_lpddr4x/pinout.py +506 -0
  134. jitxexamples-2.0.0/src/jitxexamples/jumpstart_kits/js4_fpga_lpddr4x/proof.py +176 -0
  135. jitxexamples-2.0.0/src/jitxexamples/parts/example-passives.csv +1305 -0
  136. jitxexamples-2.0.0/src/jitxexamples/patterns/__init__.py +3 -0
  137. jitxexamples-2.0.0/src/jitxexamples/patterns/fenced_pour_outline.py +110 -0
  138. jitxexamples-2.0.0/src/jitxexamples/patterns/pin_lane_polarity.py +305 -0
  139. jitxexamples-2.0.0/src/jitxexamples/patterns/pin_series_array.py +289 -0
  140. jitxexamples-2.0.0/src/jitxexamples/patterns/si_bundle_skew.py +114 -0
  141. jitxexamples-2.0.0/src/jitxexamples/patterns/si_daisy_chain.py +105 -0
  142. jitxexamples-2.0.0/src/jitxexamples/patterns/si_diff_pair.py +114 -0
  143. jitxexamples-2.0.0/src/jitxexamples/patterns/si_parts.py +117 -0
  144. jitxexamples-2.0.0/src/jitxexamples/patterns/si_point_to_point.py +99 -0
  145. jitxexamples-2.0.0/src/jitxexamples/patterns/si_series_part.py +102 -0
  146. jitxexamples-2.0.0/src/jitxexamples/patterns/si_signal_constraint.py +237 -0
  147. jitxexamples-2.0.0/src/jitxexamples/patterns/si_via_model.py +108 -0
  148. jitxexamples-2.0.0/src/jitxexamples/patterns/si_via_structure.py +107 -0
  149. jitxexamples-2.0.0/src/jitxexamples/protocols/__init__.py +78 -0
  150. jitxexamples-2.0.0/src/jitxexamples/protocols/memory/__init__.py +9 -0
  151. jitxexamples-2.0.0/src/jitxexamples/protocols/memory/ddr4.py +512 -0
  152. jitxexamples-2.0.0/src/jitxexamples/protocols/memory/ddr4_example.py +131 -0
  153. jitxexamples-2.0.0/src/jitxexamples/protocols/memory/lpddr4.py +383 -0
  154. jitxexamples-2.0.0/src/jitxexamples/protocols/memory/lpddr4_example.py +147 -0
  155. jitxexamples-2.0.0/src/jitxexamples/substrates/__init__.py +3 -0
  156. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/src/jitxexamples/substrates/generic_20layer.py +6 -4
  157. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/test.err +1 -1
  158. jitxexamples-2.0.0/test.log +541 -0
  159. jitxexamples-2.0.0/tests/conftest.py +12 -0
  160. jitxexamples-2.0.0/tests/parts.py +55 -0
  161. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/tests/test_AO3401A.py +3 -3
  162. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/tests/test_AO6409.py +3 -3
  163. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/tests/test_AP2125K_2_8TRG1.py +3 -3
  164. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/tests/test_BJT_2N3904S_RTKPS.py +3 -3
  165. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/tests/test_BQ24078RGTR.py +3 -3
  166. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/tests/test_BSN20.py +3 -3
  167. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/tests/test_BSS138.py +3 -3
  168. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/tests/test_HC_49SM12MHz20pF30ppm.py +3 -3
  169. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/tests/test_IS31FL3236A_QFLS2_TR.py +3 -3
  170. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/tests/test_KT_0603G.py +3 -3
  171. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/tests/test_KT_0603R.py +3 -3
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  354. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/tests/test_q_j_cr2032_bs_6_1.py +0 -0
  355. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/tests/test_togialed_tj_s3210sw5tglc2r_a5.py +0 -0
  356. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/tests/test_xunpu_ts_1088_ar02016.py +0 -0
  357. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/tests/test_yangxing_tech_x322512msb4si.py +0 -0
  358. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/typecheck.err +0 -0
  359. {jitxexamples-1.6.2 → jitxexamples-2.0.0}/typecheck.log +0 -0
@@ -56,6 +56,9 @@ jobs:
56
56
  uses: ./pybuild-action # from checkout above
57
57
  with:
58
58
  python-version: "${{ matrix.python-version }}"
59
+ # internal-test-designs main as of 2026-10-20: the v1 tag predates the
60
+ # test updates for jitx 4.6 and fails 6 reverse-flow tests on 4.6.0rc2.
61
+ internal-test-designs-ref: 07853dd2207c4dd17eda842af33c19854ef8919c
59
62
  run-publish: true
60
63
  hatch-index-user: ${{ vars.HATCH_INDEX_USER }}
61
64
  hatch-index-auth: ${{ secrets.HATCH_INDEX_AUTH }}
@@ -67,9 +67,10 @@ jobs:
67
67
  git clone --branch main "$REMOTE" "$MIRROR"
68
68
 
69
69
  # Replace the public tree with the released tree (tracked files only,
70
- # via git archive), then drop the trees that stay internal: .github
71
- # (our workflows) and internal (maintainer-only kit specs, program
72
- # TODOs, and deck-production tooling). Wiping first lets the subsequent
70
+ # via git archive), then drop .github (our workflows) and internal,
71
+ # which no longer exists and is removed here as a guard in case a
72
+ # maintainer-only tree of that name is added again. Wiping first lets
73
+ # the subsequent
73
74
  # "git add -A" record deletions/renames, so main accumulates a normal,
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  # diffable commit each release.
75
76
  find "$MIRROR" -mindepth 1 -maxdepth 1 ! -name '.git' -exec rm -rf {} +
@@ -5,7 +5,7 @@
5
5
 
6
6
  # Build / cache outputs.
7
7
  **/cache/
8
- # `jitx build` output: <repo-root>/designs/<module.path.design_name>/{design-info,temp,...}
8
+ # `jitx design build` output: <repo-root>/designs/<module.path.design_name>/{design-info,temp,...}
9
9
  # The `designs` directory name is chosen by JITX, not by us — hence the Python
10
10
  # package is `demos`. Anchored: only the repo-root output tree.
11
11
  /designs/
@@ -16,5 +16,3 @@ __pycache__/
16
16
  # `hatch build` output.
17
17
  /dist/
18
18
 
19
- # Deck-build dependencies, restored with `npm install` from the committed lockfile.
20
- node_modules/
@@ -0,0 +1,111 @@
1
+ # CLAUDE.md
2
+
3
+ Guidance for Claude Code (claude.ai/code) working in this repository.
4
+
5
+ ## Read README.md first
6
+
7
+ `README.md` is the single source of truth for what this repo is, its layout, the commands, and the
8
+ demo build target. Read it — do not restate it here. This file holds only the things that are
9
+ specifically about working *with an agent* in this repo.
10
+
11
+ ## Repo-specific rules
12
+
13
+ - **`designs/` at the repo root is JITX build output, not source.** `jitx design build` creates
14
+ `<repo-root>/designs/<module.path.design_name>/` (`design-info/`, `temp/`, ...). That name is
15
+ chosen by JITX. The Python demo sources live in `src/jitxexamples/demos/` for exactly this reason.
16
+ Never add source under a root `designs/`, and never rename `demos/` back to `designs/`.
17
+
18
+ - **Tests must subclass `jitx.test.TestCase`, never plain `unittest.TestCase`.**
19
+ `jitx.test.TestCase.setUpClass` activates the JITX *instantiation context*; without it, JITX class
20
+ members are not instantiated and assertions silently operate on placeholder objects rather than
21
+ real design elements.
22
+
23
+ - **`jitx.test.TestCase` does not need the JITX runtime.** It only activates the instantiation
24
+ context, so instantiating a `SampleDesign` works offline. Only `jitx design build` / `jitx ui` need
25
+ `jitx runtime start`; `jitx design build --dry <target>` translates a design without one.
26
+
27
+ - **The repo targets the jitx 4.6 line.** `pyproject.toml` requires `jitx>=4.6.0rc2,<4.7` and
28
+ `jitxlib-standard>=4.6.0rc2,<4.7`. The cap matters: the floor is a pre-release, so without it a
29
+ resolve on the internal index takes the newest pre-release, a 4.7 alpha. Two surfaces have to
30
+ agree (a 4.6 package against a 4.5 runtime is not a working install), so `jitx design build` also
31
+ needs the runtime (`~/.jitx/current`, check with `jitx runtime introspect`) on the same line as
32
+ the library. Before concluding demo code is broken, check which `jitx` you actually resolved on
33
+ both. When jitx 4.7.0 is released, raise both caps and rerun the suite: left in place, the cap
34
+ makes pip downgrade a 4.7 project's jitx or fall back to an older `jitxexamples`.
35
+
36
+ - **A maintainer machine does not resolve what a customer resolves.** Developer setups here carry an
37
+ internal index and a pre-release opt-in, and they are not all environment variables —
38
+ `~/.pip/pip.conf` can set `extra-index-url` and `pre = true`, which `env -u PIP_EXTRA_INDEX_URL`
39
+ does not strip. To reproduce a customer's resolution, neutralise the config file as well:
40
+
41
+ ```bash
42
+ env -u PIP_PRE -u PIP_EXTRA_INDEX_URL -u UV_PRERELEASE -u UV_EXTRA_INDEX_URL \
43
+ PIP_CONFIG_FILE=/dev/null hatch test --cover
44
+ ```
45
+
46
+ Confirm what you got (`pip list | grep jitx`) rather than assuming. While the floors in
47
+ `pyproject.toml` are pre-releases that public PyPI does not carry, an isolated resolve fails
48
+ outright; once they are public releases, a `.dev`, `a` or `rc` suffix means the isolation did not
49
+ hold. Without it the `hatch` envs resolve *ahead* of the public line.
50
+
51
+ - **Parts tests resolve through the project's parts chain.** `[tool.jitx.parts]` in
52
+ `pyproject.toml` names `src/jitxexamples/parts/example-passives.csv` followed by `ideal`. Tests that resolve
53
+ passives subclass `tests/parts.py:PartsTestDesign`, which loads that same chain from the project
54
+ its own file sits in (so pytest can start from any directory) and disables locking.
55
+ In a build, `ideal` needs the value pinned to one number, snaps it to E24, honors `case` and
56
+ `tolerance` (0402 where no case is pinned, 1% where no tolerance is), and ignores every other filter
57
+ (`mounting`, `type`, a rating, a dielectric, a current or a frequency), so a rated query the CSV
58
+ cannot meet resolves to an `IDEAL-*` part with no rating. `PartsTestDesign` swaps in
59
+ `PlainValueIdeal`, which declines any query carrying such a filter, so in tests that query fails
60
+ and a gap in the CSV cannot pass silently. A passing test still does not mean every part is
61
+ orderable: plain value, case and tolerance queries the CSV cannot answer get `IDEAL-*` parts.
62
+ A query `ideal` declines (an exact non-E24 value such as 30.9 kohm, a value range, or a tolerance
63
+ limit under 1%) needs a real part in the CSV. `tests/test_parts_chain.py` checks the chain order,
64
+ that the CSV answers before `ideal`, that a rated query fails rather than falling to `ideal`,
65
+ and the CSV's tolerance and unit format. Do not add tests that require live parts-source access.
66
+
67
+ - **`src/jitxexamples/` is an implicit namespace package** (no `__init__.py`). Some `components/*`
68
+ subdirectories have an empty `__init__.py` and some do not. That inconsistency is known and
69
+ intentionally untouched — do not "fix" it as a drive-by.
70
+
71
+ - **This repo is publicly mirrored** to `JITx-Inc/jitx-examples` on release
72
+ (`.github/workflows/mirror-main.yml` archives everything tracked except `.github/`). Keep
73
+ comments, docs, and placeholder text customer-appropriate.
74
+
75
+ - **Every tracked file reaches a deployment surface; there is no maintainer-only tree.** Three
76
+ surfaces publish out of this repo and all three work from tracked files: the sdist, the public
77
+ mirror, and docs.jitx.com, which only ever extracts `jumpstart-kits/` out of that sdist. Keep
78
+ kit specs and program TODOs out of the repo; git history holds the ones that used to be here.
79
+ The sdist's `exclude = ["internal"]` and the mirror's `rm -rf "$MIRROR/internal"` stay as guards
80
+ in case such a tree is added again. A file placed in `jumpstart-kits/` **publishes**: there is
81
+ no per-file opt-out, because the docs build's `exclude_patterns` is empty by contract. After
82
+ touching the sdist config, verify: `hatch build -t sdist`, then
83
+ `tar tzf dist/jitxexamples-*.tar.gz` must list one `jumpstart-kits/` entry per tracked file under
84
+ `jumpstart-kits/` (26 today) and no `internal` entry.
85
+
86
+ - **Kits carry no presentation decks.** The JS0 and JS1 decks and their deck tooling were
87
+ removed on 2026-10-22; a kit is its README pages, runbooks, reference companions and supplied
88
+ inputs. `git log -- internal/deck-tooling` recovers the old tooling from history.
89
+
90
+ - **Merge a `develop` → `main` release PR with "Create a merge commit", never "Squash and merge".**
91
+ Feature PRs into `develop` are squashed as usual; the release PR is the exception. Squashing
92
+ `develop` onto `main` collapses its history into one commit and erases the ancestry link, so git
93
+ falls back to a stale merge base and the *next* release PR reports every file both branches
94
+ touched as a spurious add/add conflict. Resolving those by hand also silently resurrects files
95
+ `develop` deliberately renamed or deleted, which is the trap — the conflicts look real.
96
+
97
+ - **If a release ever does land on `main` as a squash, sync it back before opening the next one.**
98
+ Compare `git rev-parse origin/main^{tree}` against the tree of the `develop` commit that was
99
+ squashed. If the two OIDs match, `main` holds nothing `develop` lacks, so
100
+ `git merge -s ours origin/main` restores the ancestry without touching content; confirm with
101
+ `git diff --quiet origin/develop HEAD` before pushing. If the OIDs *differ*, something landed on
102
+ `main` directly — do a normal merge and resolve it for real.
103
+
104
+ ## Verification
105
+
106
+ Run the commands in README.md's Commands section. Do not invent alternatives:
107
+ `hatch test --cover`, `hatch fmt --check`, `hatch run types:check`.
108
+
109
+ Note that the `pre-commit` hook is **not installed by default** (`core.hooksPath` is unset), and it
110
+ invokes bare `python`, which may not be on PATH. Never treat a successful commit as evidence that
111
+ the tests passed — run `hatch test --cover` explicitly.
@@ -1,15 +1,14 @@
1
1
  Metadata-Version: 2.5
2
2
  Name: jitxexamples
3
- Version: 1.6.2
3
+ Version: 2.0.0
4
4
  Summary: Library of example JITX components, substrates, and demo designs
5
5
  Project-URL: Homepage, https://jitx.com
6
6
  Project-URL: Documentation, https://docs.jitx.com
7
7
  Author: JITX
8
8
  Maintainer: JITX
9
9
  Requires-Python: >=3.12
10
- Requires-Dist: eseries
11
- Requires-Dist: jitx<5,>=4.4.0
12
- Requires-Dist: jitxlib-parts<2,>=1.3.0
13
- Requires-Dist: jitxlib-standard<5,>=4.4.0
14
- Requires-Dist: jitxlib-voltage-divider<2,>=1.0.0
15
- Requires-Dist: pytest
10
+ Requires-Dist: eseries<2,>=1.2.1
11
+ Requires-Dist: jitx<4.7,>=4.6.0rc2
12
+ Requires-Dist: jitxlib-parts<3,>=2.0.0rc1
13
+ Requires-Dist: jitxlib-standard<4.7,>=4.6.0rc2
14
+ Requires-Dist: shapely<3,>=2.1
@@ -0,0 +1,157 @@
1
+ # jitx-examples
2
+
3
+ ## What this is
4
+
5
+ `jitxexamples` is a library of example JITX package contents:
6
+
7
+ - **Components**: Python classes that model real, sourceable electronic parts (op-amps, FETs, MCUs, regulators, connectors, sensors, etc.) for use with the JITX PCB design framework.
8
+ - **Substrates**: reusable PCB stackups, via definitions, and fabrication constraints.
9
+ - **Patterns**: small single-technique modules, each with a design that translates.
10
+ - **Demos**: buildable example boards that compose package components, substrates, routing rules, and geometry into complete JITX designs.
11
+
12
+ ## Commands
13
+
14
+ ```bash
15
+ hatch test --cover # run the test suite with coverage (canonical, per README)
16
+ hatch fmt --check # check formatting/lint (ruff 0.14.9, config in pyproject)
17
+ hatch run types:check # pyright type check
18
+ hatch run types:stats # pyright stats
19
+
20
+ pytest tests/test_AO3401A.py # run a single test file
21
+ pytest tests/test_AO3401A.py -k ao3401a # run a single test
22
+ ```
23
+
24
+ ### Run demos
25
+
26
+ JITX design builds require an installed and running JITX runtime. From the project root:
27
+
28
+ ```bash
29
+ jitx runtime start --background
30
+ jitx design find
31
+ jitx design build jitxexamples.demos.si_bga_optimization.bga_escape.bga_optimization_design
32
+ jitx ui open --board --design jitxexamples.demos.si_bga_optimization.bga_escape.bga_optimization_design
33
+ ```
34
+
35
+ Build the explicit non-test design target above; do not substitute similarly named targets from
36
+ `test`, `tests`, or a test file listed by `jitx design find`.
37
+
38
+ `jitx design build` writes its output to `<repo-root>/designs/<module.path.design_name>/`
39
+ (`design-info/`, `temp/`, ...). That directory name is chosen by JITX, not by this repo, and is
40
+ git-ignored — which is why the Python sources live in `src/jitxexamples/demos/` rather than
41
+ `src/jitxexamples/designs/`.
42
+
43
+ The git `pre-commit` hook (`hooks/pre-commit`) runs `ruff check`, `ruff format --diff`, and `python -m unittest discover` on staged Python files. Install it with `git config core.hooksPath hooks` (or symlink into `.git/hooks/`).
44
+
45
+ Lint is intentionally narrow: ruff `select = ["E","F","W","A","B","C"]` with `E501`, `A005`, `C901`, `A002` ignored. Line length 88, double quotes.
46
+
47
+ ## Architecture
48
+
49
+ ### Component definitions (`src/jitxexamples/components/<category>/`)
50
+ Components are grouped into category packages (`opamps/`, `fets_n_ch/`, `mcus/`, `connectors/`, ...). Each `.py` file defines one component as a subclass of `jitx.Component`. The `__init__.py` files are empty — components are imported by their full module path (e.g. `from jitxexamples.components.fets_p_ch.AO3401A import AO3401A`).
51
+
52
+ A component class is declarative. The standard shape (see `components/opamps/texas_instruments_OPA189.py`):
53
+ - Metadata class attributes: `mpn`, `manufacturer`, `reference_designator_prefix`, `datasheet`.
54
+ - `Port()` attributes for each pin/signal.
55
+ - A `landpattern` built from a footprint generator (`jitxlib.landpatterns.generators.*`, e.g. `SOT23_5`) configured with `LeadProfile` and `jitx.Toleranced` dimensions.
56
+ - A `symbol` from `jitxlib.symbols.*`.
57
+ - A `mappings` list of `jitx.PadMapping` (port → `landpattern.p[n]`) and `jitx.SymbolMapping` (port → symbol pin).
58
+
59
+ Some files ship an accompanying `.stp` (3D STEP model) alongside the `.py`. Some components also alias the class as `Device: type[...] = ...`.
60
+
61
+ ### JumpStart kit reference solutions (`src/jitxexamples/jumpstart_kits/`)
62
+ Importable reference solutions for the JumpStart kit runbooks published from `jumpstart-kits/`
63
+ (one package per kit, e.g. `js1_stackup_components/`, with one subpackage per task deliverable:
64
+ `hdi_stackup/`, `versal_fpga/`). These are covered by the same ruff, pyright, and pytest gates as
65
+ the rest of the package. The learner-facing runbooks and supplied inputs live in `jumpstart-kits/`
66
+ at the repo root (published to the docs site), not here.
67
+
68
+ ### Substrate definitions (`src/jitxexamples/substrates/`)
69
+ Substrates define reusable PCB construction details. `generic_20layer.py` provides `Generic_Substrate`, a generic 20-layer stackup with dielectric/conductor materials, fabrication constraints, and via classes that designs can use directly or specialize.
70
+
71
+ ### Pattern definitions (`src/jitxexamples/patterns/`)
72
+ Patterns are small modules that each show one technique, written to be read; each ends in a design that translates with `jitx design build --dry`. `fenced_pour_outline.py` fences an arbitrary closed outline (an antipad, an RF cavity, a BGA breakout) with vias: a `Tag`, a `design_constraint(...).fence_via(...)` rule on the substrate, and a tagged `Pour` inside a `FencedOutline` circuit whose `GND` port connects to the board's ground net. A `KeepOut` over the same outline, which keeps pours and auto-placed vias out of the opening, is optional; the module adds one. Its design target is `jitxexamples.patterns.fenced_pour_outline.fenced_pour_outline_design`. To see the fence, run a full build (`jitx design build <target>`, which needs the runtime) and open the board with `jitx ui open --board --design <target>`.
73
+
74
+ The `si_*` modules each show one signal-integrity constraint on jitx 4.6, on plain nets with code routes that close the path, and their docstrings paste the design-issues output they produced: `si_point_to_point` (timing and loss with a `TerminatingPinModel`), `si_series_part` (a `BridgingPinModel` through a series part), `si_via_model` (a via with `models`), `si_diff_pair` (intra-pair skew), `si_bundle_skew` (skew across pairs with `ConstrainReferenceDifference`), `si_daisy_chain` (an ordered chain with `>>`), `si_via_structure` (a via structure from `jitxlib.via_structures`) and `si_signal_constraint` (a `SignalConstraint` subclass); `si_parts` holds their fictional parts. The `pin_*` modules show SI constraints on pin-assigned paths: `pin_lane_polarity` (lane choice and P/N inversion on a provider that is one end of the path) and `pin_series_array` (channel choice through a pass-through part, both sides in one mapping). The `jitx-interconnect-constraints` and `jitx-pin-assignment` skills point at them as worked patterns.
75
+
76
+ ### Protocol definitions (`src/jitxexamples/protocols/`)
77
+ High-speed protocols that `jitxlib.protocols` does not ship: port bundles plus a `SignalConstraint` whose skew limits cite their source and its scope in the module docstring. Each protocol module has a worked example beside it named `<protocol>_example.py`, a `SampleDesign` that nets a fictional controller to a real memory part and applies the constraint without `>>`. Today that is `memory/lpddr4.py` (Micron MT53E1G32D2FW-046 WT:B, an LPDDR4X/LPDDR4 part, target `jitxexamples.protocols.memory.lpddr4_example.LPDDR4ExampleDesign`) and `memory/ddr4.py` (Micron MT40A1G16TB-062E:F, target `jitxexamples.protocols.memory.ddr4_example.DDR4ExampleDesign`). The examples are not routed, so the design issues (each example's docstring shows the `issues(satisfied=True)` call) list each constrained path as `Unconnected Topology` until the board is routed.
78
+
79
+ ### Demo definitions (`src/jitxexamples/demos/`)
80
+ Demos are buildable JITX `SampleDesign` classes. The SI BGA optimization example lives under `demos/si_bga_optimization/`; its build target is `jitxexamples.demos.si_bga_optimization.bga_escape.bga_optimization_design`.
81
+
82
+ Within that demo package, `constraints.py` defines the design-rule `Tag` subclasses and the antipad fence-via `design_constraint` rules; `substrate.py` specializes the generic substrate with the 85 ohm stripline routing structure and per-signal-layer launch profiles (`BGAEscapeSubstrate`), anchoring the fence rules into the design tree; `si_geometry.py` builds the per-lane signal-via antipad, deskew-arc, GND-stitching, and board-level SI-cutout geometry, including the HFSS-instrumented-lane override; and `bga_escape.py` assembles the per-lane `EscapeLane` circuits into the top-level `BGALink` and holds the buildable `bga_optimization_design` entry point. `generic_bga.py` defines the reusable hex-grid BGA component used by the design, and `deskew.py` contains support geometry for the BGA diff-pair deskew copper.
83
+
84
+ ### Tests (`tests/`)
85
+ One `test_*.py` per component. Tests subclass `jitx.test.TestCase` (a `unittest.TestCase` that activates the JITX *instantiation context* in `setUpClass` — required so that JITX class members instantiate correctly; do not use plain `unittest.TestCase` for code that builds design elements). A test typically defines a `SampleDesign` subclass containing an `@inline class circuit(Circuit)` that instantiates the component, then asserts on the built design.
86
+
87
+ ## Dependencies & environment
88
+
89
+ Requires Python ≥3.12; the test matrix covers 3.12/3.13/3.14. Built with hatchling + hatch-vcs (version derived from git tags). Core deps: `jitx>=4.6.0rc2,<4.7`, `jitxlib-standard>=4.6.0rc2,<4.7`, `jitxlib-parts>=2.0.0rc1,<3`, `eseries>=1.2.1,<2`, and `shapely>=2.1,<3`. The wheel packages `src/jitxexamples`; `docs/` and `tests/` are excluded from `[tool.jitx]` discovery, while `docs/` is also excluded from pyright.
90
+
91
+ ## Parts configuration
92
+
93
+ Some component circuits here create `jitxlib.parts.Resistor`, `Capacitor`, or `Inductor` from
94
+ electrical constraints with no MPN named, and each query goes to the providers of a parts chain in
95
+ order ([jitxlib-parts docs](https://github.com/JITx-Inc/jitxlib-parts#readme)). Your project owns
96
+ that chain: the `jitxexamples` wheel carries the example CSV but no chain, and without a chain
97
+ resolution stops with `NoChainConfigured`. This repository's `pyproject.toml` sets:
98
+
99
+ ```toml
100
+ [tool.jitx.parts]
101
+ chain = ["csv:src/jitxexamples/parts/example-passives.csv", "ideal"]
102
+ ```
103
+
104
+ The `csv:` path is relative to this repository's root, so it names the source file in a checkout;
105
+ a project that installed `jitxexamples` copies the file out instead (below). That CSV is asked
106
+ first. It holds real resistors, capacitors, and inductors as an example. Every resistor row has a
107
+ `max_power`, except the 0 ohm jumpers, which the datasheet rates by current: their `max_current` is
108
+ that rated current. Every inductor row has a `max_current`: the DC current the part carries within
109
+ both its temperature-rise and saturation ratings, the lower of the two where the datasheet gives
110
+ both. On a resistor row, `rated_voltage_dc` is the datasheet's maximum working (limiting element)
111
+ voltage. The voltage across a resistor at its rated power, sqrt(P x R), is lower than that for low
112
+ values, so state a resistor's dissipation with `max_power`. The example CSV is not a qualified
113
+ approved-vendor list. Columns other than `category`, `mpn`, `manufacturer`, and `datasheet` are
114
+ attributes a query can filter or rank on. A bare number gets a unit only in `resistance`,
115
+ `capacitance`, `inductance`, `rated_voltage_dc`, `max_current`, `max_power`, and `area`; elsewhere
116
+ write the unit (`6.2 GHz`), or a query with units on that column fails with a dimension mismatch.
117
+
118
+ `ideal` answers only what the CSV could not. Its parts have an MPN starting `IDEAL-`, no
119
+ manufacturer, and cannot be ordered. It needs the value pinned to one number and snaps it to E24. It
120
+ takes the `case` the query names (the first, if it names several), or 0402 if it names none, and an
121
+ exact `tolerance`, or 1% otherwise. It ignores every other filter, including ratings, dielectric,
122
+ `mounting`, and `mpn`. So a query the example CSV cannot meet and that names no `case`, such as a 10
123
+ µF capacitor rated 56 V or a 10 µH inductor rated 1 A, comes back as an 0402 part with no rating. `ideal`
124
+ declines a value range, and a query its snapped value, case, or tolerance does not meet (an exact
125
+ 4.99 kohm, or a tolerance limit under 1%); such a query must match a CSV row or resolution fails. A
126
+ `csv:` path that names no file reads as an empty catalogue with no error, so every query `ideal` can
127
+ meet gets an `ideal` part.
128
+
129
+ `PartsTestDesign` in `tests/parts.py` uses the same chain with locking off, and limits `ideal` to
130
+ queries on value, case, and tolerance, so a test fails where a build would drop a filter.
131
+
132
+ With no `lock` keys set, a build here records the passives it resolves in `parts.lock.json` at the
133
+ repository root, `ideal` parts included, and later builds reuse those entries. Adding the real part
134
+ to the CSV does not replace an `ideal` part already in the lockfile; delete `parts.lock.json` to
135
+ resolve again, and search it or the BOM for `IDEAL-` to see what is left. For a board you intend to
136
+ order:
137
+
138
+ ```toml
139
+ [tool.jitx.parts]
140
+ chain = ["csv:parts/approved-parts.csv"]
141
+ lock = "parts.lock.json"
142
+ lock-mode = "read-write"
143
+ ```
144
+
145
+ A project that installed `jitxexamples` can copy the example in to try these circuits: pass
146
+ `importlib.resources.files("jitxexamples") / "parts" / "example-passives.csv"` to `shutil.copy`
147
+ with the destination `parts/approved-parts.csv` (the `parts/` directory must exist). The copy is
148
+ not an approved list. Every row needs your approval before you order a board built from it.
149
+ Point `csv:` at your approved-parts list, starting from the example header: these circuits filter or
150
+ rank on `case`, `mounting`, `tolerance`, `type`, `temperature_coefficient_code`, `rated_voltage_dc`,
151
+ `max_current`, `self_resonant_frequency`, `quality_factor`, and `material_core`, plus the value
152
+ columns. Remove `"ideal"` so that a query your list cannot meet, a column your list lacks, or a
153
+ wrong CSV path fails instead of resolving to a part that ignores the filters asked for. Commit the
154
+ `parts.lock.json` a build writes, so a catalogue change cannot silently change an existing board;
155
+ the `lock` lines spell out the defaults, with paths relative to the project root. To share a
156
+ catalogue as package data, use `jitxlib.parts.providers.CsvParts.from_package(...)` or publish a
157
+ chain through the `jitxlib-parts-policy` entry point.
@@ -6,6 +6,7 @@ SHELL := /bin/bash
6
6
  # You can set these variables from the command line, and also
7
7
  # from the environment for the first three.
8
8
  PIPOPTS ?= --extra-index-url "https://pypi.jitx.com/jitx/main/+simple"
9
+ PYTHON ?= python3
9
10
  SPHINXOPTS ?= --jobs 1 --write-all --fresh-env --warning-file build.out
10
11
  SPHINXAPIDOC ?= sphinx-apidoc
11
12
  SPHINXBUILD ?= sphinx-build
@@ -21,7 +22,7 @@ all: html archive
21
22
 
22
23
  # create python venv
23
24
  .venv: requirements.txt
24
- python -m venv .venv \
25
+ $(PYTHON) -m venv .venv \
25
26
  && source .venv/bin/activate \
26
27
  && pip install $(PIPOPTS) -r requirements.txt \
27
28
  && touch .venv
@@ -52,4 +53,4 @@ archive:
52
53
  # clean up
53
54
  .PHONY: clean
54
55
  clean:
55
- rm -rf .venv "source/jitxlib" "$(BUILDDIR)" build.out "$(ARCHIVENAME)"
56
+ rm -rf .venv "source/jitxexamples" "$(BUILDDIR)" build.out "$(ARCHIVENAME)"
@@ -0,0 +1,8 @@
1
+ sphinx>=8.1.0,<9.0
2
+ sphinx_autodoc_typehints
3
+
4
+ jitx>=4.6.0rc2,<4.7
5
+ jitxlib-standard>=4.6.0rc2,<4.7
6
+ jitxlib-parts>=2.0.0rc1,<3
7
+ eseries>=1.2.1,<2
8
+ shapely>=2.1,<3
@@ -40,7 +40,7 @@ exclude_patterns = []
40
40
  # https://www.sphinx-doc.org/en/master/usage/configuration.html#options-for-html-output
41
41
 
42
42
  html_theme = "alabaster"
43
- html_static_path = ["_static"]
43
+ html_static_path = []
44
44
 
45
45
  # -- Don't show "Bases: object" in api docs ----------------------------------
46
46
  # https://stackoverflow.com/questions/46279030/how-can-i-prevent-sphinx-from-listing-object-as-a-base-class
@@ -0,0 +1,11 @@
1
+ .. jitxexamples documentation master file
2
+
3
+ jitxexamples documentation
4
+ ==========================
5
+
6
+
7
+ .. toctree::
8
+ :maxdepth: 3
9
+ :caption: Contents:
10
+
11
+ jitxexamples/components/modules
@@ -9,16 +9,14 @@ landing page itself.
9
9
 
10
10
  ## What belongs here
11
11
 
12
- Learner-facing narrative and collateral only: runbooks, reference companions, supplied inputs, and
13
- decks. Importable solution code lives under `src/jitxexamples/jumpstart_kits/` where the repo's
12
+ Learner-facing narrative and collateral only: runbooks, reference companions, and supplied inputs.
13
+ Kits carry no presentation decks. Importable solution code lives under `src/jitxexamples/jumpstart_kits/` where the repo's
14
14
  ruff, pyright, and pytest gates cover it.
15
15
 
16
- Internal material stays in `internal/` at the repo root: requirement specs, program TODOs, and
17
- deck-production tooling. That tree is excluded from the sdist and from the public mirror, so it
18
- reaches no deployment surface. **Every `.md` placed here, by contrast, will be published to
19
- docs.jitx.com and into the site-root `llms.txt`** once the docs build picks up this section — so
20
- write everything here as public from the outset, and never link from here into `internal/` (the
21
- link would 404 on the docs site).
16
+ **Every `.md` placed here will be published to docs.jitx.com and into the site-root `llms.txt`**
17
+ once the docs build picks up this section, so write everything here as public from the outset,
18
+ and link only to pages and files that are published too (any other link would 404 on the docs
19
+ site).
22
20
 
23
21
  ## Structure
24
22
 
@@ -32,7 +30,7 @@ link to one child.
32
30
 
33
31
  ## Linking collateral, and the one place Sphinx syntax is needed
34
32
 
35
- A plain relative markdown link is all you need for a deck, a PDF, or a supplied input: the docs build
33
+ A plain relative markdown link is all you need for a PDF or a supplied input: the docs build
36
34
  turns a link to a **non-document** file into a real download, served from
37
35
  `_downloads/<sha256-of-its-bytes>/<name>`.
38
36
 
@@ -243,43 +243,46 @@ to `@jitx <request to AI>` for general work). For example:
243
243
  ## Appendix A — Python dependencies
244
244
 
245
245
  Creating a project installs the packages below into the project virtual environment. The JS kits
246
- require **JITX 4.4.0 or newer**. The table is an **illustrative snapshot of the shape of the
247
- dependency set**, captured from a freshly scaffolded project on **JITX 4.4.0 with Python 3.12** —
248
- the versions are **not** the floor and they move with each release, so regenerate it for the version
249
- you are deploying with `pip list` in the project venv.
246
+ require **JITX 4.6.x**. The table is an **illustrative snapshot of the shape of the
247
+ dependency set**, captured from a freshly scaffolded project on Python 3.12.1 with pre-release 4.6
248
+ builds: jitx 4.6.0rc9.dev2+ga358849d8, jitxcore 4.6.0rc3 and jitxlib-standard
249
+ 4.6.0rc3.dev12+g2fd994d25. The capture machine's pip serves pre-releases, which is why protobuf
250
+ 7.37.0rc1 appears, and jitx and jitxlib-standard were pinned to 4.6 after
251
+ `jitx project dependencies upgrade` moved them past it. The versions are **not** the floor and they move with each
252
+ release, so regenerate it for the version you are deploying with `pip list` in the project venv.
250
253
 
251
254
  > Note: the JITX runtime and the `jitx` / `jitxcore` Python packages must sit on the **same release
252
- > line** — the same major.minor, e.g. a 4.4.x runtime with 4.4.x packages. Patch numbers can differ;
253
- > release lines cannot — a 4.4 package against a 4.2 runtime is not a working install. `jitx runtime
255
+ > line**: the same major.minor, e.g. a 4.6.x runtime with 4.6.x packages. Patch numbers can differ;
256
+ > release lines cannot: a 4.6 package against a 4.4 runtime is not a working install. `jitx runtime
254
257
  > introspect` reports the runtime, `pip show jitx` the package.
255
258
 
256
259
  | Package | Version |
257
260
  | --- | --- |
258
261
  | annotated-doc | 0.0.5 |
259
- | anyio | 4.14.2 |
260
- | certifi | 2026.7.22 |
262
+ | anyio | 4.15.1 |
263
+ | certifi | 2026.10.23 |
261
264
  | click | 8.5.0 |
262
265
  | flexcache | 0.3 |
263
266
  | flexparser | 0.4 |
264
267
  | h11 | 0.16.0 |
265
268
  | httpcore | 1.0.9 |
266
269
  | httpx | 0.28.1 |
267
- | idna | 3.19 |
268
- | jitx | 4.4.0 |
269
- | jitxcore | 4.4.0 |
270
- | jitxlib-standard | 4.4.0 |
270
+ | idna | 3.20 |
271
+ | jitx | 4.6.0rc9.dev2+ga358849d8 |
272
+ | jitxcore | 4.6.0rc3 |
273
+ | jitxlib-standard | 4.6.0rc3.dev12+g2fd994d25 |
271
274
  | markdown-it-py | 4.2.0 |
272
275
  | mdurl | 0.1.2 |
273
- | numpy | 2.5.2 |
276
+ | numpy | 2.5.4 |
274
277
  | packaging | 25.0 |
275
278
  | Pint | 0.24.4 |
276
- | pip | 25.0.1 |
277
- | platformdirs | 4.11.5 |
278
- | protobuf | 7.36.1 |
279
+ | pip | 23.2.1 |
280
+ | platformdirs | 4.14.0 |
281
+ | protobuf | 7.37.0rc1 |
279
282
  | psutil | 7.2.2 |
280
283
  | Pygments | 2.21.0 |
281
284
  | rich | 14.3.4 |
282
- | shapely | 2.1.2 |
285
+ | shapely | 2.2.0 |
283
286
  | shellingham | 1.5.4 |
284
287
  | typer | 0.25.1 |
285
288
  | typing_extensions | 4.16.0 |
@@ -1,4 +1,4 @@
1
- <!-- JITX Setup — Reference Companion (JS0) · rev 1.5 · 2026-09-08 -->
1
+ <!-- JITX Setup — Reference Companion (JS0) · rev 1.7 · 2026-10-28 -->
2
2
 
3
3
  # JITX Setup — Reference Companion (JS0)
4
4
 
@@ -16,9 +16,9 @@ Run these in a terminal — you'll get a working, authenticated install, proven
16
16
  2. **Install the JITX CLI.** `pip install jitx`. If you hit the PEP 668 "externally-managed-environment" error — the Python packaging rule that stops `pip` writing into a system-managed interpreter — install `uv` (https://astral.sh/uv) and run `uv tool install jitx` instead. Verify: `jitx --version`.
17
17
  3. **Install the runtime.** `jitx runtime install` — do this **before** signing in. **On Windows**, this launches an MSI installer in a separate popup window (possibly behind others) — complete it to finish. If it fails with `not tested on Linux distribution '<x>'`, retry as `jitx runtime install --target ubuntu`; the Ubuntu build runs on most glibc Linux. Check it with `jitx runtime introspect`, which works anywhere — `jitx runtime status` is project-scoped and fails with `No pyproject.toml found` until you create the project in step 5.
18
18
  4. **Sign in.** `jitx auth login` prints an activation link and a code; open it in any browser, approve, and the command completes on its own. It does not launch the browser for you, which matters on a headless or remote machine. **The link expires in 10 minutes** — re-run the command if it lapses. In the browser, **Sign in with Google** is simplest; if you're **not** using a Google-enabled account, enter your registered email and JITX password. Confirm with `jitx auth show`: **`Authorized: yes`** is the field that matters, and an `Expires` in the past is normal — the value shown is always the pre-refresh one, because the authorization check that renews the token runs after the claims are read.
19
- 5. **Validate with two builds.** The global CLI (step 2) has no `pip`, so run this inside each project once it exists. Create and activate a virtual environment — `python3 -m venv .venv && source .venv/bin/activate` on macOS or Linux, or `$env:PYTHONUTF8 = "1"; py -3 -m venv .venv` then `.\.venv\Scripts\Activate.ps1` in Windows PowerShell — then `pip install jitx`, `jitx project dependencies upgrade`, `jitx runtime start --background`, and `jitx find`. After the upgrade, `pip show jitx` and `jitx runtime introspect` should report the same release line (4.4.x with 4.4.x). **On Windows**, `PYTHONUTF8=1` keeps the `cp1252` console from choking on `Ω`; and a `WinError 32` from the upgrade means pip is replacing the running `jitx.exe` — run `.\.venv\Scripts\python.exe -m pip install --upgrade jitx` and re-run the upgrade.
20
- - **Simplest.** Create a new project with `jitx project layout init` (this seeds a two-resistor sample design). Build the seeded non-test target from `jitx find` — ignore any target whose module path comes from `test`, `tests`, or a test file. **Take the target verbatim from `jitx find`** — the two halves are derived differently, so don't assemble it yourself: the package is the directory lowercased with hyphens and spaces turned into underscores, while the design class is that same name in CapWords. A directory called `my-first-board` builds as `jitx build my_first_board.main.MyFirstBoard`. Then open the views with `jitx ui open --schematic` and `jitx ui open --board`.
21
- - **Full.** Clone `https://github.com/JITx-Inc/jitx-examples` and build the [`si_bga_optimization`](https://github.com/JITx-Inc/jitx-examples/tree/main/src/jitxexamples/demos/si_bga_optimization) design, taking the target verbatim from `jitx find` as above — expect `jitxexamples.demos.si_bga_optimization.bga_escape.bga_optimization_design`. Open the board view to confirm.
19
+ 5. **Validate with two builds.** The global CLI (step 2) has no `pip`, so run this inside each project once it exists. Create and activate a virtual environment: `python3 -m venv .venv && source .venv/bin/activate` on macOS or Linux, or `$env:PYTHONUTF8 = "1"; py -3 -m venv .venv` then `.\.venv\Scripts\Activate.ps1` in Windows PowerShell. Then run `pip install jitx`, `jitx project dependencies upgrade`, `jitx runtime start --background`, and `jitx design find`. After the upgrade, `pip show jitx` and `jitx runtime introspect` should report the same release line (4.6 and 4.6, say). **On Windows**, `PYTHONUTF8=1` keeps the `cp1252` console from choking on `Ω`; and a `WinError 32` from the upgrade means pip is replacing the running `jitx.exe`: run `.\.venv\Scripts\python.exe -m pip install --upgrade jitx` and re-run the upgrade.
20
+ - **Simplest.** Create a new project with `jitx project layout init` (this seeds a two-resistor sample design). Build the seeded non-test target from `jitx design find` — ignore any target whose module path comes from `test`, `tests`, or a test file. **Take the target verbatim from `jitx design find`** — the two halves are derived differently, so don't assemble it yourself: the package is the directory lowercased with hyphens and spaces turned into underscores, while the design class is that same name in CapWords. A directory called `my-first-board` builds as `jitx design build my_first_board.main.MyFirstBoard`. Then open the views with `jitx ui open --schematic` and `jitx ui open --board`.
21
+ - **Full.** Clone `https://github.com/JITx-Inc/jitx-examples` and build the [`si_bga_optimization`](https://github.com/JITx-Inc/jitx-examples/tree/main/src/jitxexamples/demos/si_bga_optimization) design, taking the target verbatim from `jitx design find` as above — expect `jitxexamples.demos.si_bga_optimization.bga_escape.bga_optimization_design`. Open the board view to confirm.
22
22
  - **`jitx ui open` holds the terminal** while its window is open — use a second terminal, or background it, for the next command. Later calls return straight away and add their windows to the JITX app already running; there's no limit on how many views can be open at once, so leave the Simplest build's windows up.
23
23
  - **If the command comes straight back, it crashed — it didn't open.** The slow-first-view note below applies only while `jitx ui open` is still running.
24
24
  - **The first view may be slow — if it's still running.** The very first board or schematic window can take a few minutes to appear — more likely on macOS. If it doesn't show up straight away, wait it out rather than re-running. If nothing shows after **5 minutes**, something is wrong. Later views come up faster.
@@ -1,5 +1,5 @@
1
1
  <!--
2
- JITX Setup Runbook (JS0) · rev 1.5 · 2026-09-08
2
+ JITX Setup Runbook (JS0) · rev 1.7 · 2026-10-28
3
3
  Paste this file into your AI coding agent (Claude Code, Codex / GPT, or Devin), or upload it,
4
4
  and tell the agent to follow it.
5
5
  -->
@@ -85,11 +85,11 @@ $env:PYTHONUTF8 = "1"; py -3 -m venv .venv; .\.venv\Scripts\Activate.ps1
85
85
  pip install jitx
86
86
  jitx project dependencies upgrade
87
87
  jitx runtime start --background
88
- jitx find
88
+ jitx design find
89
89
  ```
90
90
 
91
- - **5a — Simplest build.** Run `jitx project layout init` to create a new JITX project seeded with a two-resistor sample design (Devin users: you made this project in step 4). Then run the setup commands above and build the seeded non-test target from `jitx find` — ignore any target whose module path comes from `test`, `tests`, or a test file. **Take the target verbatim from `jitx find`** — the two halves are derived differently, so don't assemble it yourself: the package is the directory lowercased with hyphens and spaces turned into underscores, while the design class is that same name in CapWords. A directory called `my-first-board` builds as `jitx build my_first_board.main.MyFirstBoard`. Then show me the schematic and board views.
92
- - **5b — Full build.** Clone `https://github.com/JITx-Inc/jitx-examples`, run the setup commands above, and **take the `si_bga_optimization` target verbatim from `jitx find`** — the same rule as 5a, so a repo reorganisation can't strand you on a stale module path. Expect `jitxexamples.demos.si_bga_optimization.bga_escape.bga_optimization_design`. Two things about this repo's output: `jitx find` also prints an `errors: import failed` block for the repo's `tests/` modules — expected here (its tests aren't a package) and not a fault; the `designs:` list is what you take the target from. And after `jitx project dependencies upgrade`, `pip show jitx` and `jitx runtime introspect` must report the same release line (4.4.x with 4.4.x) — if the upgrade moved `jitx` to a different line than the runtime, stop and tell me rather than building. Build it, confirm it builds, and display the board UI windows for me.
91
+ - **5a: Simplest build.** Run `jitx project layout init` to create a new JITX project seeded with a two-resistor sample design (Devin users: you made this project in step 4). Then run the setup commands above and build the seeded non-test target from `jitx design find`; ignore any target whose module path comes from `test`, `tests`, or a test file. **Take the target verbatim from `jitx design find`**. The two halves are derived differently, so don't assemble it yourself: the package is the directory lowercased with hyphens and spaces turned into underscores, while the design class is that same name in CapWords. A directory called `my-first-board` builds as `jitx design build my_first_board.main.MyFirstBoard`. Then show me the schematic and board views.
92
+ - **5b: Full build.** Clone `https://github.com/JITx-Inc/jitx-examples`, run the setup commands above, and **take the `si_bga_optimization` target verbatim from `jitx design find`**, the same rule as 5a, so a repo reorganisation can't strand you on a stale module path. Expect `jitxexamples.demos.si_bga_optimization.bga_escape.bga_optimization_design`. If `jitx design find` also prints a warning, or an `errors:` block naming only test modules (`test_*`, `conftest`), that is not a fault here: take the target from the `designs:` list. If the target is not there, or the `errors:` block names any other module, stop and show me the `errors:` lines. And after `jitx project dependencies upgrade`, `pip show jitx` and `jitx runtime introspect` must report the same release line (4.6 and 4.6, say); if the upgrade moved `jitx` to a different line than the runtime, stop and tell me rather than building. Build it, confirm it builds, and display the board UI windows for me.
93
93
 
94
94
  > **If a build fails with "You are not authenticated. Please sign in through the JITX Sidebar in VSCode"**, that means step 3 didn't complete — re-run `jitx auth login`, don't go looking for VSCode. `jitx runtime start --background` succeeds while unauthenticated, so a green step 2 is not proof of sign-in, and the real one-line cause arrives underneath two Python tracebacks.
95
95
 
@@ -8,17 +8,10 @@ steps that need you. Everything below is the context around it.
8
8
  Takes you from scratch to a configured, authenticated, skills-enabled JITX environment — proven by
9
9
  two real builds and a closing design-as-code change. Work through JS0 before JS1.
10
10
 
11
- Requires JITX 4.4.0 or newer.
11
+ Requires JITX 4.6.x.
12
12
 
13
13
  ## Start here — the JS0 walkthrough
14
14
 
15
- You can get oriented by reading this page or alternatively downloading the 5-slide deck.
16
- Instruction content is also available as a PDF or PPTX for reference or distribution, from the
17
- [Presentation](presentation/) page:
18
-
19
- - [JS0_Presentation.pdf](presentation/JS0_Presentation.pdf) — read-only, opens anywhere
20
- - [JS0_Presentation.pptx](presentation/JS0_Presentation.pptx) — editable PowerPoint
21
-
22
15
  ### The goal — get JITX set up and AI-enabled correctly
23
16
 
24
17
  You finish with the JITX CLI and runtime installed, an authenticated session, the JITX skills