hwcomponents-cacti 1.0.21__tar.gz

hwcomponents_cacti-1.0.21/.github/workflows/publish.yaml

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+name: Upload Python Package to PyPI
+
+on:
+  push:
+    branches:
+      - main
+      - master
+  release:
+    types: [created]
+
+jobs:
+  pypi-publish:
+    name: Publish package to PyPI
+    runs-on: ubuntu-latest
+    environment:
+      name: pypi
+      url: https://pypi.org/p/hwcomponents-cacti
+    permissions:
+      id-token: write
+    steps:
+      - uses: actions/checkout@v4
+        with:
+          fetch-depth: 0  # Fetch all history and tags for setuptools-scm
+          submodules: recursive  # Check out all submodules
+      - name: Initialize and update submodules
+        run: |
+          git submodule update --init --recursive
+      - name: Set up Python
+        uses: actions/setup-python@v4
+        with:
+          python-version: "3.12"
+      - name: Install dependencies
+        run: |
+          python -m pip install --upgrade pip
+          pip install build
+      - name: Build package
+        working-directory: .
+        env:
+          PYTHONPATH: ${{ github.workspace }}
+        run: |
+          python -m build
+      - name: Publish package distributions to PyPI
+        uses: pypa/gh-action-pypi-publish@release/v1

hwcomponents_cacti-1.0.21/.gitignore

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+# Python bytecode
+__pycache__/
+*.py[cod]
+*$py.class
+
+# Distribution / packaging
+dist/
+build/
+*.egg-info/
+*.egg
+
+# Virtual environments
+venv/
+env/
+.env/
+.venv/
+ENV/
+
+# IDE specific files
+.idea/
+.vscode/
+*.swp
+*.swo
+.DS_Store
+
+# Jupyter Notebook
+.ipynb_checkpoints
+
+# Testing
+.coverage
+htmlcov/
+.pytest_cache/
+.tox/
+nosetests.xml
+coverage.xml
+*.cover
+
+# mypy
+.mypy_cache/
+.dmypy.json
+dmypy.json
+
+# pip
+pip-log.txt
+pip-delete-this-directory.txt
+
+# Logs
+*.log
+logs/
+
+# Local development settings
+.env
+.env.local
+.env.*.local
+
+# Documentation
+docs/_build/
+site/
+
+# Temporary files
+*.tmp
+*.bak
+*.swp
+*~ 

hwcomponents_cacti-1.0.21/.gitmodules

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+[submodule "hwcomponents_cacti/cacti"]
+	path = hwcomponents_cacti/cacti
+	url = https://github.com/HewlettPackard/cacti.git

hwcomponents_cacti-1.0.21/Makefile

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+.PHONY: all test clean
+
+build:
+	cd hwcomponents_cacti/cacti && make clean && make
+	chmod -R 775 hwcomponents_cacti/cacti || true
+	test -x hwcomponents_cacti/cacti/cacti
+
+install:
+	make build
+	pip3 install .

hwcomponents_cacti-1.0.21/PKG-INFO

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+Metadata-Version: 2.4
+Name: hwcomponents_cacti
+Version: 1.0.21
+Summary: A package for estimating the energy and area of memories with CACTI
+Author-email: Tanner Andrulis <andrulis@mit.edu>
+License-Expression: MIT
+Keywords: accelerator,hardware,energy,estimation,CACTI
+Classifier: Development Status :: 3 - Alpha
+Classifier: Programming Language :: Python :: 3
+Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
+Requires-Python: >=3.12
+Description-Content-Type: text/markdown
+Requires-Dist: hwcomponents
+
+# HWComponents-Cacti
+
+This model connects CACTI to the HWComponents. It provides models for SRAM, DRAM, and
+caches. This is adapted from the Accelergy CACTI plug-in.
+
+These models are for use with the HWComponents package, found at
+https://accelergy-project.github.io/hwcomponents/.
+
+## Installation
+
+Install from PyPI:
+
+```bash
+pip install hwcomponents-cacti
+
+# Check that the installation is successful
+hwc --list | grep SRAM
+hwc --list | grep DRAM
+hwc --list | grep Cache
+```
+
+## Citation
+
+If you use this library in your work, please cite the following:
+
+```bibtex
+@INPROCEEDINGS{cimloop,
+  author={Andrulis, Tanner and Emer, Joel S. and Sze, Vivienne},
+  booktitle={2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)},
+  title={CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool},
+  year={2024},
+  volume={},
+  number={},
+  pages={10-23},
+  doi={10.1109/ISPASS61541.2024.00012}
+}
+@inproceedings{accelergy,
+  author      = {Wu, Yannan Nellie and Emer, Joel S and Sze, Vivienne},
+  booktitle   = {2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
+  title       = {Accelergy: An architecture-level energy estimation methodology for accelerator designs},
+  year        = {2019},
+}
+@article{shivakumar2001cacti,
+  title={Cacti 3.0: An integrated cache timing, power, and area model},
+  author={Shivakumar, Premkishore and Jouppi, Norman P},
+  year={2001},
+  publisher={Technical Report 2001/2, Compaq Computer Corporation}
+}
+@ARTICLE{wilton1996cacti,
+  title={CACTI: an enhanced cache access and cycle time model},
+  author={Wilton, S.J.E. and Jouppi, N.P.},
+  journal={IEEE Journal of Solid-State Circuits},
+  year={1996},
+  volume={31},
+  number={5},
+  pages={677-688},
+  keywords={Driver circuits;Costs;Decoding;Analytical models;Stacking;Delay estimation;Computer architecture;Equations;Councils;Wiring},
+  doi={10.1109/4.509850}
+}
+@article{balasubramonian2017cacti,
+  author = {Balasubramonian, Rajeev and Kahng, Andrew B. and Muralimanohar, Naveen and Shafiee, Ali and Srinivas, Vaishnav},
+  title = {CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories},
+  year = {2017},
+  issue_date = {June 2017},
+  publisher = {Association for Computing Machinery},
+  address = {New York, NY, USA},
+  volume = {14},
+  number = {2},
+  issn = {1544-3566},
+  url = {https://doi.org/10.1145/3085572},
+  doi = {10.1145/3085572},
+  journal = {ACM Trans. Archit. Code Optim.},
+  month = jun,
+  articleno = {14},
+  numpages = {25},
+  keywords = {DRAM, Memory, NVM, interconnects, tools}
+}
+```

hwcomponents_cacti-1.0.21/README.md

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+# HWComponents-Cacti
+
+This model connects CACTI to the HWComponents. It provides models for SRAM, DRAM, and
+caches. This is adapted from the Accelergy CACTI plug-in.
+
+These models are for use with the HWComponents package, found at
+https://accelergy-project.github.io/hwcomponents/.
+
+## Installation
+
+Install from PyPI:
+
+```bash
+pip install hwcomponents-cacti
+
+# Check that the installation is successful
+hwc --list | grep SRAM
+hwc --list | grep DRAM
+hwc --list | grep Cache
+```
+
+## Citation
+
+If you use this library in your work, please cite the following:
+
+```bibtex
+@INPROCEEDINGS{cimloop,
+  author={Andrulis, Tanner and Emer, Joel S. and Sze, Vivienne},
+  booktitle={2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)},
+  title={CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool},
+  year={2024},
+  volume={},
+  number={},
+  pages={10-23},
+  doi={10.1109/ISPASS61541.2024.00012}
+}
+@inproceedings{accelergy,
+  author      = {Wu, Yannan Nellie and Emer, Joel S and Sze, Vivienne},
+  booktitle   = {2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
+  title       = {Accelergy: An architecture-level energy estimation methodology for accelerator designs},
+  year        = {2019},
+}
+@article{shivakumar2001cacti,
+  title={Cacti 3.0: An integrated cache timing, power, and area model},
+  author={Shivakumar, Premkishore and Jouppi, Norman P},
+  year={2001},
+  publisher={Technical Report 2001/2, Compaq Computer Corporation}
+}
+@ARTICLE{wilton1996cacti,
+  title={CACTI: an enhanced cache access and cycle time model},
+  author={Wilton, S.J.E. and Jouppi, N.P.},
+  journal={IEEE Journal of Solid-State Circuits},
+  year={1996},
+  volume={31},
+  number={5},
+  pages={677-688},
+  keywords={Driver circuits;Costs;Decoding;Analytical models;Stacking;Delay estimation;Computer architecture;Equations;Councils;Wiring},
+  doi={10.1109/4.509850}
+}
+@article{balasubramonian2017cacti,
+  author = {Balasubramonian, Rajeev and Kahng, Andrew B. and Muralimanohar, Naveen and Shafiee, Ali and Srinivas, Vaishnav},
+  title = {CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories},
+  year = {2017},
+  issue_date = {June 2017},
+  publisher = {Association for Computing Machinery},
+  address = {New York, NY, USA},
+  volume = {14},
+  number = {2},
+  issn = {1544-3566},
+  url = {https://doi.org/10.1145/3085572},
+  doi = {10.1145/3085572},
+  journal = {ACM Trans. Archit. Code Optim.},
+  month = jun,
+  articleno = {14},
+  numpages = {25},
+  keywords = {DRAM, Memory, NVM, interconnects, tools}
+}
+```

hwcomponents_cacti-1.0.21/hwcomponents_cacti/__init__.py

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+from .hwcomponents_cacti import *

hwcomponents_cacti-1.0.21/hwcomponents_cacti/_version.py

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+# file generated by setuptools-scm
+# don't change, don't track in version control
+
+__all__ = [
+    "__version__",
+    "__version_tuple__",
+    "version",
+    "version_tuple",
+    "__commit_id__",
+    "commit_id",
+]
+
+TYPE_CHECKING = False
+if TYPE_CHECKING:
+    from typing import Tuple
+    from typing import Union
+
+    VERSION_TUPLE = Tuple[Union[int, str], ...]
+    COMMIT_ID = Union[str, None]
+else:
+    VERSION_TUPLE = object
+    COMMIT_ID = object
+
+version: str
+__version__: str
+__version_tuple__: VERSION_TUPLE
+version_tuple: VERSION_TUPLE
+commit_id: COMMIT_ID
+__commit_id__: COMMIT_ID
+
+__version__ = version = '1.0.21'
+__version_tuple__ = version_tuple = (1, 0, 21)
+
+__commit_id__ = commit_id = 'g017430f53'

hwcomponents_cacti-1.0.21/hwcomponents_cacti/cacti/2DDRAM_Samsung2GbDDR2.cfg

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+# Cache size
+//-size (bytes) 528
+//-size (bytes) 4096
+//-size (bytes) 262144
+//-size (bytes) 1048576
+//-size (bytes) 2097152
+//-size (bytes) 4194304
+//-size (bytes) 8388608
+//-size (bytes) 16777216
+//-size (bytes) 33554432
+//-size (bytes) 134217728
+//-size (bytes) 268435456
+//-size (bytes) 536870912
+//-size (bytes) 67108864
+//-size (bytes) 536870912
+//-size (bytes) 1073741824
+# For 3D DRAM memory please use Gb as units
+-size (Gb) 2
+
+# Line size
+//-block size (bytes) 8
+-block size (bytes) 128
+
+# To model Fully Associative cache, set associativity to zero
+//-associativity 0
+//-associativity 2
+//-associativity 4
+-associativity 1
+//-associativity 16
+
+-read-write port 1
+-exclusive read port 0
+-exclusive write port 0
+-single ended read ports 0
+
+# Multiple banks connected using a bus
+-UCA bank count 16
+//-technology (u) 0.032
+//-technology (u) 0.040
+//-technology (u) 0.065
+//-technology (u) 0.078
+-technology (u) 0.080
+
+# following three parameters are meaningful only for main memories
+
+//-page size (bits) 8192 
+-burst length 4
+-internal prefetch width 1
+
+# following parameter can have one of five values -- (itrs-hp, itrs-lstp, itrs-lop, lp-dram, comm-dram)
+//-Data array cell type - "itrs-hp"
+//-Data array cell type - "itrs-lstp"
+//-Data array cell type - "itrs-lop"
+-Data array cell type - "comm-dram"
+
+# following parameter can have one of three values -- (itrs-hp, itrs-lstp, itrs-lop)
+//-Data array peripheral type - "itrs-hp"
+-Data array peripheral type - "itrs-lstp"
+//-Data array peripheral type - "itrs-lop"
+
+# following parameter can have one of five values -- (itrs-hp, itrs-lstp, itrs-lop, lp-dram, comm-dram)
+-Tag array cell type - "itrs-hp"
+//-Tag array cell type - "itrs-lstp"
+
+# following parameter can have one of three values -- (itrs-hp, itrs-lstp, itrs-lop)
+-Tag array peripheral type - "itrs-hp"
+//-Tag array peripheral type - "itrs-lstp"
+
+# Bus width include data bits and address bits required by the decoder
+//-output/input bus width 16
+//-output/input bus width 64
+-output/input bus width 64
+
+// 300-400 in steps of 10
+-operating temperature (K) 350
+
+# Type of memory - cache (with a tag array) or ram (scratch ram similar to a register file) 
+# or main memory (no tag array and every access will happen at a page granularity Ref: CACTI 5.3 report)
+//-cache type "cache"
+//-cache type "ram"
+//-cache type "main memory"
+-cache type "3D memory or 2D main memory"
+
+# Parameters for 3D DRAM
+//-page size (bits) 16384 
+-page size (bits) 8192
+//-page size (bits) 4096
+-burst depth 4
+-IO width 4
+-system frequency (MHz) 266
+
+-stacked die count 1
+-partitioning granularity 0 // 0: coarse-grained rank-level; 1: fine-grained rank-level
+//-TSV projection 1 // 0: ITRS aggressive; 1: industrial conservative
+
+## End of parameters for 3D DRAM
+
+# to model special structure like branch target buffers, directory, etc. 
+# change the tag size parameter
+# if you want cacti to calculate the tagbits, set the tag size to "default"
+-tag size (b) "default"
+//-tag size (b) 45
+
+# fast - data and tag access happen in parallel
+# sequential - data array is accessed after accessing the tag array
+# normal - data array lookup and tag access happen in parallel
+#          final data block is broadcasted in data array h-tree 
+#          after getting the signal from the tag array
+-access mode (normal, sequential, fast) - "fast"
+//-access mode (normal, sequential, fast) - "normal"
+//-access mode (normal, sequential, fast) - "sequential"
+
+
+# DESIGN OBJECTIVE for UCA (or banks in NUCA)
+-design objective (weight delay, dynamic power, leakage power, cycle time, area) 0:0:0:0:100
+
+# Percentage deviation from the minimum value 
+# Ex: A deviation value of 10:1000:1000:1000:1000 will try to find an organization
+# that compromises at most 10% delay. 
+# NOTE: Try reasonable values for % deviation. Inconsistent deviation
+# percentage values will not produce any valid organizations. For example,
+# 0:0:100:100:100 will try to identify an organization that has both
+# least delay and dynamic power. Since such an organization is not possible, CACTI will
+# throw an error. Refer CACTI-6 Technical report for more details
+-deviate (delay, dynamic power, leakage power, cycle time, area) 50:100000:100000:100000:1000000
+
+# Objective for NUCA
+-NUCAdesign objective (weight delay, dynamic power, leakage power, cycle time, area) 0:0:0:0:100
+-NUCAdeviate (delay, dynamic power, leakage power, cycle time, area) 10:10000:10000:10000:10000
+
+# Set optimize tag to ED or ED^2 to obtain a cache configuration optimized for
+# energy-delay or energy-delay sq. product
+# Note: Optimize tag will disable weight or deviate values mentioned above
+# Set it to NONE to let weight and deviate values determine the 
+# appropriate cache configuration
+//-Optimize ED or ED^2 (ED, ED^2, NONE): "ED"
+//-Optimize ED or ED^2 (ED, ED^2, NONE): "ED^2"
+-Optimize ED or ED^2 (ED, ED^2, NONE): "NONE"
+
+-Cache model (NUCA, UCA)  - "UCA"
+//-Cache model (NUCA, UCA)  - "NUCA"
+
+# In order for CACTI to find the optimal NUCA bank value the following
+# variable should be assigned 0.
+-NUCA bank count 0
+
+# NOTE: for nuca network frequency is set to a default value of 
+# 5GHz in time.c. CACTI automatically
+# calculates the maximum possible frequency and downgrades this value if necessary
+
+# By default CACTI considers both full-swing and low-swing 
+# wires to find an optimal configuration. However, it is possible to 
+# restrict the search space by changing the signaling from "default" to 
+# "fullswing" or "lowswing" type.
+-Wire signaling (fullswing, lowswing, default) - "Global_5"
+//-Wire signaling (fullswing, lowswing, default) - "default"
+//-Wire signaling (fullswing, lowswing, default) - "lowswing"
+
+//-Wire inside mat - "global"
+-Wire inside mat - "semi-global"
+-Wire outside mat - "global"
+//-Wire outside mat - "semi-global"
+
+-Interconnect projection - "conservative"
+//-Interconnect projection - "aggressive"
+
+# Contention in network (which is a function of core count and cache level) is one of
+# the critical factor used for deciding the optimal bank count value
+# core count can be 4, 8, or 16
+//-Core count 4
+-Core count 8
+//-Core count 16
+-Cache level (L2/L3) - "L3"
+
+-Add ECC - "false"
+
+//-Print level (DETAILED, CONCISE) - "CONCISE"
+-Print level (DETAILED, CONCISE) - "DETAILED"
+
+# for debugging
+//-Print input parameters - "true"
+-Print input parameters - "false"
+# force CACTI to model the cache with the 
+# following Ndbl, Ndwl, Nspd, Ndsam,
+# and Ndcm values
+-Force cache config - "true"
+//-Force cache config - "false"
+-Ndwl 128
+-Ndbl 32
+-Nspd 1
+-Ndcm 1
+-Ndsam1 1
+-Ndsam2 1
+