haadic 0.6.0__tar.gz

haadic-0.6.0/PKG-INFO

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+Metadata-Version: 2.3
+Name: haadic
+Version: 0.6.0
+Summary: A package for parametric layout design.
+Author: Patarimi
+Author-email: Patarimi <<38954040+Patarimi@users.noreply.github.com>>
+Requires-Dist: ciel>=2.5.1
+Requires-Dist: cyclopts>=4.14.0
+Requires-Dist: klayout>=0.30.2
+Requires-Dist: lark>=1.2.2
+Requires-Dist: matplotlib>=3.10.3
+Requires-Dist: numpy>=2.5.0
+Requires-Dist: pandas>=2.3.1
+Requires-Dist: pydantic>=2.13.4
+Requires-Dist: pyqt6>=6.11.0 ; sys_platform == 'linux'
+Requires-Dist: python-dotenv>=1.1.1
+Requires-Dist: rich>=13.9.4
+Requires-Dist: scikit-rf>=1.12.0
+Requires-Dist: scipy>=1.18.0
+Requires-Dist: tabulate>=0.9.0
+Requires-Python: >3.12, <3.14
+Description-Content-Type: text/markdown
+
+# HAADIC
+
+**Highly-Automated Analog Designer for Integrated Circuits**
+
+This project is a prototype. Its goal is to create a technological and
+software-agnostic design flow, from device sizing to layout and implementation.
+
+## How to get started
+
+This application needs nix, uv and python3. For windows, please install NixOS as shown [here](https://nixos.wiki/wiki/WSL).
+
+Installation using [uvx](https://docs.astral.sh/uv/getting-started/installation/) is recommended.
+
+The following command check if everything is correctly setup :
+
+```shell
+uvx --with="git+https://github.com/Patarimi/haadic.git" haadic smoke-test
+```
+
+## Setting up a new Project
+
+A directory with the required files can be generated using :
+
+```shell
+haadic new
+```
+
+## GDS Generation
+
+First update the layout fonction in the design.py file created in the previous step. Some helpfull fonctions can be found in [design:layouts](reference/haadic/design/layouts/index.md).
+Then run the following command :
+
+```shell
+uv run --script design.py
+```
+
+The [Design flow](#design-flow) is run.
+
+Dimensions in the layout can be changed by editing the `dim` variable.
+Post-simulation computation can be done by editing the `evaluate` function.
+
+## Design Flow
+
+The following flow is run using the informations given in a _design_ python file (See [Setup a new Project](#setting-up-a-new-project)). The flow has 2 entry points :
+
+- `flow.run_from_dim` : Only requires a `dim` variables which defines the value of each parameters of the layout function.
+- `flow.run_from_target` : Requires both a `target`and an `local_model` function. The `local_model` is an implementation of the design methodology which output the layout parameters value required to obtains the `target`.
+
+```mermaid
+flowchart TD
+    s1{Start #2}
+    s2{Start #1}
+    app["Physical Model
+(design:local_model)"]
+    pl["Parametric Layout
+(klayout + design:layout)"]
+    be_ext["RC extraction
+(steps.extraction + Magic-VLSI)"]
+    sim["Spice simulation
+(steps.spice_sim + NGSpice)"]
+    spec["Performances Evaluation
+(design:post_processors)"]
+
+    s1 -- "design:specifications" --> app
+    s2 -- "design:dimensions" --> pl
+    app --"dimensions (step.Dim)" --> pl
+    pl --"geometries (.gds)" --> be_ext
+    be_ext --"netlist (.cir)" --> sim
+    sim --"raw simulation (step.SimRes)" --> spec
+    spec --"performances (.csv)" --> st{stop}
+```
+
+When finished, a _.gds_ file is available for further design and a _.csv_ file with the performances of the design.
+
+## PDKs configuration
+
+A techno.json file can be created in the working dir or the haadic root with the following structure:
+
+```json
+{
+"techno_name": {
+  "base_dir": "path to the pdk directory root",
+  "layermap": "path to the layermap (relative to the base_dir)",
+  "techlef": "path to the tlef file",
+  "magic_rc": "path to the configuration file of magic",
+  "lib_spice": "path to the spice model library",
+  "section": "name of the section to import in the spice library typical",
+  "source_url": "url to be use for download (set to "ciel" for ciel installation)",
+  "version": "version id (only required if source_url is set to "ciel")"
+}
+}
+```
+
+A techno.json file with three open source PDK and a mock PDK are already supplied.
+
+## For developpers
+
+Install haadic with optional group dev :
+
+```shell
+uv install git+https://github.com/Patarimi/haadic --with dev
+```
+
+Then run pytest in a shell
+
+```shell
+uvx run poe test
+```

haadic-0.6.0/docs/README.md

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+# HAADIC
+
+**Highly-Automated Analog Designer for Integrated Circuits**
+
+This project is a prototype. Its goal is to create a technological and
+software-agnostic design flow, from device sizing to layout and implementation.
+
+## How to get started
+
+This application needs nix, uv and python3. For windows, please install NixOS as shown [here](https://nixos.wiki/wiki/WSL).
+
+Installation using [uvx](https://docs.astral.sh/uv/getting-started/installation/) is recommended.
+
+The following command check if everything is correctly setup :
+
+```shell
+uvx --with="git+https://github.com/Patarimi/haadic.git" haadic smoke-test
+```
+
+## Setting up a new Project
+
+A directory with the required files can be generated using :
+
+```shell
+haadic new
+```
+
+## GDS Generation
+
+First update the layout fonction in the design.py file created in the previous step. Some helpfull fonctions can be found in [design:layouts](reference/haadic/design/layouts/index.md).
+Then run the following command :
+
+```shell
+uv run --script design.py
+```
+
+The [Design flow](#design-flow) is run.
+
+Dimensions in the layout can be changed by editing the `dim` variable.
+Post-simulation computation can be done by editing the `evaluate` function.
+
+## Design Flow
+
+The following flow is run using the informations given in a _design_ python file (See [Setup a new Project](#setting-up-a-new-project)). The flow has 2 entry points :
+
+- `flow.run_from_dim` : Only requires a `dim` variables which defines the value of each parameters of the layout function.
+- `flow.run_from_target` : Requires both a `target`and an `local_model` function. The `local_model` is an implementation of the design methodology which output the layout parameters value required to obtains the `target`.
+
+```mermaid
+flowchart TD
+    s1{Start #2}
+    s2{Start #1}
+    app["Physical Model
+(design:local_model)"]
+    pl["Parametric Layout
+(klayout + design:layout)"]
+    be_ext["RC extraction
+(steps.extraction + Magic-VLSI)"]
+    sim["Spice simulation
+(steps.spice_sim + NGSpice)"]
+    spec["Performances Evaluation
+(design:post_processors)"]
+
+    s1 -- "design:specifications" --> app
+    s2 -- "design:dimensions" --> pl
+    app --"dimensions (step.Dim)" --> pl
+    pl --"geometries (.gds)" --> be_ext
+    be_ext --"netlist (.cir)" --> sim
+    sim --"raw simulation (step.SimRes)" --> spec
+    spec --"performances (.csv)" --> st{stop}
+```
+
+When finished, a _.gds_ file is available for further design and a _.csv_ file with the performances of the design.
+
+## PDKs configuration
+
+A techno.json file can be created in the working dir or the haadic root with the following structure:
+
+```json
+{
+"techno_name": {
+  "base_dir": "path to the pdk directory root",
+  "layermap": "path to the layermap (relative to the base_dir)",
+  "techlef": "path to the tlef file",
+  "magic_rc": "path to the configuration file of magic",
+  "lib_spice": "path to the spice model library",
+  "section": "name of the section to import in the spice library typical",
+  "source_url": "url to be use for download (set to "ciel" for ciel installation)",
+  "version": "version id (only required if source_url is set to "ciel")"
+}
+}
+```
+
+A techno.json file with three open source PDK and a mock PDK are already supplied.
+
+## For developpers
+
+Install haadic with optional group dev :
+
+```shell
+uv install git+https://github.com/Patarimi/haadic --with dev
+```
+
+Then run pytest in a shell
+
+```shell
+uvx run poe test
+```

haadic-0.6.0/haadic/__init__.py

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+"""
+A Python framework for analog IC design automation.
+
+# Haadic structure:
+
+ - core
+    - flow: for defining and running design flows
+    - steps: for defining the core steps in the design flow, such as layout generation, extraction, simulation, etc.
+    - techno: for handling technology-specific information and operations.
+ - io
+    - readers: files readers (spice, raw, etc.)
+    - writers: files writers (spice)
+    - wrappers: for external tools (e.g., magic, netgen, etc.)
+ - design
+    - layouts: for layout generation and manipulation
+    - models: for device and circuit modeling
+    - evaluators: for performance evaluation
+    - components: parameterized components (e.g., common sources) and design helpers (e.g., EKV model).
+"""
+
+name = "haadic"

haadic-0.6.0/haadic/_config.py

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+from pathlib import Path
+
+ROOT_DIR = Path(__file__).parent
+DATA_DIR = ROOT_DIR / "data"
+REF_PATH = ROOT_DIR.parent / "tests" / "ref_files"

haadic-0.6.0/haadic/core/__init__.py

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+"""Module for the haadic core functionality: run analog flow."""

haadic-0.6.0/haadic/core/flow.py

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+"""Module defining the Flow class, which composes multiple steps (layout generation, extraction, simulation, post-processing) into a complete design flow."""
+
+import logging
+from pathlib import Path
+from typing import Callable, Iterable
+from dataclasses import dataclass, field
+from tabulate import tabulate
+
+import haadic.core.steps.step as step
+from haadic.core.steps.extraction import Extract, ConfigExtract
+from haadic.core.steps.layout_generation import Layout, ConfigLayout, LayoutFunc
+from haadic.core.steps.spice_simulation import BenchSim, ConfigSim
+from haadic.core.steps.post_process import PostProcess, ConfigPostProc, PostProcessFunc
+from haadic.core.techno import Available_PDK
+from haadic.io.wrappers.magic import ExtractLevels
+
+
+@dataclass
+class ConfigFlow:
+    """
+    Configuration for a Flow execution.
+
+    :param techno: Selected PDK name.
+    :param reload: Whether to reload intermediate files when available (e.g., layout, spice netlist) or to recompute them.
+    :param run_dir: Base directory where results are written.
+    :param extract_level: Extraction level used by the Extract step.
+    :param sweep_folder: If True, create a separate folder per sweep value when using the run_from_* methods.
+    """
+
+    techno: Available_PDK = "sky130"
+    reload: bool = True
+    run_dir: Path = Path("./results")
+    extract_level: ExtractLevels = "RC"
+    sweep_folder: bool = True
+
+
+@dataclass
+class Flow:
+    """
+    Flow dataclass.
+
+    :param layout: function that generates the layout. It takes as argument a klayout Cell, a LayerStack and the dimensions of the layout to generate.
+     It should return a klayout Cell with the generated layout.
+    :param benches: list of bench files to run. The flow will look for these files in the current folder and run them with the extracted spice netlist.
+     They can be absolute or relative to the running folder.
+    :param postprocess: function that evaluates the performances of the circuit. It takes as argument the simulation results of the benches and the dimensions of the layout.
+     It should return a dictionary with the performance metrics to optimize as keys and their values as values.
+    :param config: flow options, such as the technology to use, whether to reload the layout if it already exists, and the folder to run the flow in.
+    """
+
+    layout: LayoutFunc
+    benches: Iterable[Path]
+    postprocess: Iterable[PostProcessFunc]
+    config: ConfigFlow = field(default_factory=ConfigFlow)
+
+    def run_from_dim(self, dimensions: step.Dim) -> step.Dim:
+        """
+        Run the composed flow starting from explicit dimensions.
+
+        Args:
+            dimensions: a `Dim` instance describing layout dimensions/parameters.
+
+        Returns:
+            A `Dim`-like object containing aggregated performance metrics produced by the postprocess steps.
+
+        """
+        datas = step.Dim()
+        d_benches = [f.resolve() for f in self.benches]
+        for bench, eval in zip(d_benches, self.postprocess):
+            start = step.init_step(
+                dimensions, self.config.run_dir, self.config.sweep_folder
+            )
+            flow = step.compose(
+                Layout(ConfigLayout(self.layout, self.config.techno)),
+                Extract(ConfigExtract(self.config.techno, self.config.extract_level)),
+                BenchSim(ConfigSim(bench, self.config.techno)),
+                reload=self.config.reload,
+            )
+            output_file = flow.run(start)
+            pp = PostProcess(ConfigPostProc(eval))
+            data = pp.run(output_file, dimensions)
+            for key in data.dct:
+                datas[key] = data[key]
+        return datas
+
+    def run_from_target(
+        self,
+        target: step.Dim,
+        local_model: Callable[[step.Dim], step.Dim],
+    ) -> step.Dim:
+        """
+        Run the flow from a target specification using a local model.
+
+        Args:
+            target: A `Dim` describing desired target values.
+            local_model: Callable that maps the `target` to actual layout `Dim` parameters.
+
+        Returns:
+            A `Dim`-like object containing aggregated performance metrics produced by the postprocess steps.
+
+        """
+        perf = self.run_from_dim(local_model(target))
+        res = [(key, perf.dct[key], target.dct.get(key, "N/A")) for key in perf.dct]
+        logging.info(
+            "\n" + tabulate(res, headers=["obtained", "targeted"], tablefmt="grid")
+        )
+
+        logging.info("compare performances to targets")
+        cost = step.compare_to(perf.dct, target.dct)
+        logging.info(f"current cost: {cost}")
+        return perf

haadic-0.6.0/haadic/core/steps/__init__.py

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+"""Module for the core steps in the design flow."""

haadic-0.6.0/haadic/core/steps/extraction.py

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+"""Module defining the Extract step, which performs layout extraction to generate a SPICE netlist from a GDSII layout."""
+
+from haadic.core.steps.step import Step
+from dataclasses import dataclass, field
+from typing import Sequence
+from haadic.io.wrappers.magic import ExtractLevels, extract_spice
+from pathlib import Path
+from haadic.core.techno import get_file, Available_PDK
+
+
+@dataclass
+class ConfigExtract:
+    """
+    Configuration for the Extract step.
+
+    :param techno: technology to use for extraction (e.g., "sky130", "gf180mcu").
+    :param level: extraction level to use (e.g., "NoPar", "RC").
+    """
+
+    techno: Available_PDK = "sky130"
+    level: ExtractLevels = "RC"
+
+
+@dataclass
+class Extract(Step):
+    """
+    Extract step dataclass.
+
+    :param config: configuration for the Extract step, including the technology to use and the extraction level.
+    :param input_suffixes: list of suffixes for the expected input file(s) (default: [".gds"]).
+    :param output_suffix: suffix for the output file (default: ".cir").
+    """
+
+    config: ConfigExtract = field(default_factory=ConfigExtract)
+    input_suffixes: Sequence[str] = field(default_factory=lambda: [".gds"])
+    output_suffix: str = ".cir"
+
+    def run(self, input_file: Path = Path("top.gds")) -> Path:
+        """
+        Extract a netlist from a given layout.
+
+        :param Path input_file: input gds file.
+        :return Path: extracted spice circuit.
+        """
+        output_path = self.output_file(input_file)
+        rc_file = get_file(self.config.techno, "magic_rc")
+        return extract_spice(
+            input_file,
+            rc_file,
+            input_file.stem,
+            output_path,
+            options=self.config.level,
+        )

haadic-0.6.0/haadic/core/steps/layout_generation.py

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+"""Module defining the Layout step for generating layouts from parametric descriptions."""
+
+import logging
+from haadic.core.techno import Available_PDK
+from pathlib import Path
+from typing import Callable, Sequence
+from dataclasses import field, dataclass
+import json
+
+from haadic.design.layouts.base_cell import BaseCell
+from haadic.core.steps.step import Dim, Step
+
+type LayoutFunc = Callable[[BaseCell, Dim], BaseCell]
+
+
+@dataclass
+class ConfigLayout:
+    """
+    Configuration for the Layout step.
+
+    :param layout: function that generates the layout.
+    :param techno: technology to be used.
+    """
+
+    layout: LayoutFunc
+    techno: Available_PDK = "sky130"
+
+
+@dataclass
+class Layout(Step):
+    """
+    Step to generate a layout from a parametric description.
+
+    :param config: configuration for the layout generation step, including the layout function and the technology to use.
+    :param input_suffixes: list of expected suffixes for the input files. By default, it is set to [".json"].
+    :param output_suffix: suffix for the output file. By default, it is set to ".gds".
+    """
+
+    config: ConfigLayout
+    input_suffixes: Sequence[str] = field(default_factory=lambda: [".json"])
+    output_suffix: str = ".gds"
+
+    def run(self, input_file: Path) -> Path:
+        """
+        Generate a layout in the requested techologies with the given parametric layout and the given set of parameters.
+
+        :param input_file: set of parameters for the layout.
+        """
+        with input_file.open() as f:
+            dimensions = json.load(f)
+        output_file = self.output_file(input_file)
+        logging.info("layout generation with geometry: " + str(dimensions))
+
+        cellb = BaseCell(self.config.techno, input_file.stem)
+
+        self.config.layout(cellb, dimensions)
+
+        cellb.write(output_file)
+        return output_file

haadic-0.6.0/haadic/core/steps/post_process.py

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+"""Module defining the PostProcess step for post-processing simulation results and extracting performance metrics."""
+
+from haadic.io.readers.raw import parse_out
+from typing import Callable, Sequence
+from dataclasses import field, dataclass
+from pathlib import Path
+import pandas as pd
+
+from haadic.core.steps.step import Dim
+
+SimRes = pd.DataFrame
+
+type PostProcessFunc = Callable[[SimRes, Dim, Path], Dim]
+
+
+@dataclass
+class ConfigPostProc:
+    """
+    Configuration for the PostProcess step.
+
+    :param evaluate: function that evaluates the performances of the circuit.
+        It takes as argument the simulation results of the benches and the dimensions of the layout.
+        It should return a Dim class with the performance metrics.
+    """
+
+    evaluate: PostProcessFunc
+
+
+@dataclass
+class PostProcess:
+    """
+    Step to post-process the simulation results and extract performance metrics.
+
+    This step is meant to be run after a spice simulation step, and it takes as input the raw output file of the simulation (with suffix .raw)
+    and produces as output a Dim class with the performance metrics.
+
+    :param config: configuration for the post-processing step.
+    :param input_suffixes: list of expected suffixes for the input files. By default, it is set to [".raw"].
+    :param output_suffix: suffix for the output file. By default, it is set to "".
+    """
+
+    config: ConfigPostProc
+    input_suffixes: Sequence[str] = field(default_factory=lambda: [".raw"])
+    output_suffix: str = ""
+
+    def run(self, data_file: Path = Path("top.raw"), dimensions: Dim = Dim()) -> Dim:
+        """
+        Run the post-processing step.
+
+        This method reads the raw simulation output file, evaluates the performance metrics using the provided evaluate function, and returns a Dim class with the performance metrics.
+
+        :param data_file: path to the raw simulation output file.
+        :param dimensions: dimensions of the layout.
+        :return Dim: performance metrics.
+        """
+        data = parse_out(data_file)
+        base_dir = data_file.parent
+        return self.config.evaluate(data, dimensions, base_dir)

haadic-0.6.0/haadic/core/steps/spice_simulation.py

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+"""Spice simulation step for the haadic design flow."""
+
+from typing import Sequence
+from dataclasses import dataclass, field
+from pathlib import Path
+from haadic.io.handlers.netlist import Netlist
+from haadic.io.wrappers.ngspice import compute
+from haadic.io.wrappers.tools import to_wsl
+from haadic.core.techno import get_file, load_pdk, Available_PDK
+from haadic.core.steps.step import can_skip, Step
+
+
+@dataclass
+class ConfigSim:
+    """
+    Configuration for the BenchSim step.
+
+    :param bench: path to the bench file to simulate, defaults to "bench.cir"."
+    :param techno: name of the technology to use for the simulation, defaults to "sky130".
+    """
+
+    bench: Path = Path("bench.cir")
+    techno: Available_PDK = "sky130"
+
+
+@dataclass
+class BenchSim(Step):
+    """
+    Step to run a spice simulation using ngspice.
+
+    :param config: configuration for the BenchSim step.
+    :param input_suffixes: list of accepted input file suffixes for this step, defaults to [".cir"].
+    :param output_suffix: suffix for the output file generated by this step, defaults to ".raw".
+    """
+
+    config: ConfigSim = field(default_factory=ConfigSim)
+    input_suffixes: Sequence[str] = field(default_factory=lambda: [".cir"])
+    output_suffix: str = ".raw"
+
+    def run(self, input_file: Path = Path("top.cir")) -> Path:
+        """
+        Run the given netlist using the requested technologie.
+
+        :param input_file: spice netlist bench to be simulated, defaults to "bench.cir"
+        :return Path: path to the output raw file generated by ngspice.
+        """
+        bench = self.config.bench
+        data_file = (
+            Path(input_file).with_name(bench.name).with_suffix(self.output_suffix)
+        )
+        if can_skip(bench, data_file) and can_skip(input_file, data_file):
+            return data_file
+        techno = self.config.techno
+
+        spice = Netlist().load(bench)
+        section = load_pdk(techno).get("section", "tt")
+        spice.add_lib(to_wsl(get_file(techno, "lib_spice")), section)
+
+        spice.add_include(input_file)
+        spice.write(data_file.with_name(bench.name))
+
+        compute(data_file.with_name(bench.name), data_file)
+        return data_file